mirror of
https://github.com/pascallanger/DIY-Multiprotocol-TX-Module.git
synced 2025-02-04 21:48:12 +00:00
374 lines
11 KiB
C++
374 lines
11 KiB
C++
/*
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This project is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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Multiprotocol is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Multiprotocol. If not, see <http://www.gnu.org/licenses/>.
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*/
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#if defined(FRSKYX_RX_CC2500_INO)
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#include "iface_cc2500.h"
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#define FRSKYX_FCC_LENGTH (30+2)
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#define FRSKYX_LBT_LENGTH (33+2)
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enum {
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FRSKYX_RX_TUNE_START,
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FRSKYX_RX_TUNE_LOW,
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FRSKYX_RX_TUNE_HIGH,
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FRSKYX_RX_BIND,
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FRSKYX_RX_DATA,
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};
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static uint8_t frskyx_rx_chanskip;
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static uint8_t frskyx_rx_disable_lna;
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static uint8_t frskyx_rx_data_started;
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static int8_t frskyx_rx_finetune;
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static void __attribute__((unused)) frskyx_rx_strobe_rx()
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{
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CC2500_Strobe(CC2500_SIDLE);
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CC2500_Strobe(CC2500_SFRX);
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CC2500_Strobe(CC2500_SRX);
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}
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static void __attribute__((unused)) FrSkyX_Rx_initialise() {
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CC2500_Reset();
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CC2500_WriteReg(CC2500_02_IOCFG0, 0x01);
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CC2500_WriteReg(CC2500_18_MCSM0, 0x18);
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CC2500_WriteReg(CC2500_07_PKTCTRL1, 0x04);
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CC2500_WriteReg(CC2500_3E_PATABLE, 0xFF);
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CC2500_WriteReg(CC2500_0C_FSCTRL0, 0);
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CC2500_WriteReg(CC2500_0D_FREQ2, 0x5C);
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CC2500_WriteReg(CC2500_13_MDMCFG1, 0x23);
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CC2500_WriteReg(CC2500_14_MDMCFG0, 0x7A);
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CC2500_WriteReg(CC2500_19_FOCCFG, 0x16);
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CC2500_WriteReg(CC2500_1A_BSCFG, 0x6C);
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CC2500_WriteReg(CC2500_1B_AGCCTRL2, 0x03);
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CC2500_WriteReg(CC2500_1C_AGCCTRL1, 0x40);
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CC2500_WriteReg(CC2500_1D_AGCCTRL0, 0x91);
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CC2500_WriteReg(CC2500_21_FREND1, 0x56);
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CC2500_WriteReg(CC2500_22_FREND0, 0x10);
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CC2500_WriteReg(CC2500_23_FSCAL3, 0xA9);
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CC2500_WriteReg(CC2500_24_FSCAL2, 0x0A);
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CC2500_WriteReg(CC2500_25_FSCAL1, 0x00);
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CC2500_WriteReg(CC2500_26_FSCAL0, 0x11);
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CC2500_WriteReg(CC2500_29_FSTEST, 0x59);
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CC2500_WriteReg(CC2500_2C_TEST2, 0x88);
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CC2500_WriteReg(CC2500_2D_TEST1, 0x31);
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CC2500_WriteReg(CC2500_2E_TEST0, 0x0B);
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CC2500_WriteReg(CC2500_03_FIFOTHR, 0x07);
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CC2500_WriteReg(CC2500_09_ADDR, 0x00);
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switch (sub_protocol) {
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case FRSKYX_FCC:
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CC2500_WriteReg(CC2500_17_MCSM1, 0x0C);
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CC2500_WriteReg(CC2500_0E_FREQ1, 0x76);
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CC2500_WriteReg(CC2500_0F_FREQ0, 0x27);
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CC2500_WriteReg(CC2500_06_PKTLEN, 0x1E);
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CC2500_WriteReg(CC2500_08_PKTCTRL0, 0x01);
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CC2500_WriteReg(CC2500_0B_FSCTRL1, 0x0A);
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CC2500_WriteReg(CC2500_10_MDMCFG4, 0x7B);
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CC2500_WriteReg(CC2500_11_MDMCFG3, 0x61);
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CC2500_WriteReg(CC2500_12_MDMCFG2, 0x13);
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CC2500_WriteReg(CC2500_15_DEVIATN, 0x51);
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break;
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case FRSKYX_LBT:
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CC2500_WriteReg(CC2500_17_MCSM1, 0x0E);
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CC2500_WriteReg(CC2500_0E_FREQ1, 0x80);
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CC2500_WriteReg(CC2500_0F_FREQ0, 0x00);
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CC2500_WriteReg(CC2500_06_PKTLEN, 0x23);
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CC2500_WriteReg(CC2500_08_PKTCTRL0, 0x01);
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CC2500_WriteReg(CC2500_0B_FSCTRL1, 0x08);
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CC2500_WriteReg(CC2500_10_MDMCFG4, 0x7B);
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CC2500_WriteReg(CC2500_11_MDMCFG3, 0xF8);
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CC2500_WriteReg(CC2500_12_MDMCFG2, 0x03);
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CC2500_WriteReg(CC2500_15_DEVIATN, 0x53);
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break;
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}
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frskyx_rx_disable_lna = IS_POWER_FLAG_on;
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CC2500_SetTxRxMode(frskyx_rx_disable_lna ? TXRX_OFF : RX_EN); // lna disable / enable
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frskyx_rx_strobe_rx();
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CC2500_WriteReg(CC2500_0A_CHANNR, 0); // bind channel
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delayMicroseconds(1000); // wait for RX to activate
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}
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static void __attribute__((unused)) frskyx_rx_set_channel(uint8_t channel)
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{
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CC2500_WriteReg(CC2500_0A_CHANNR, hopping_frequency[channel]);
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CC2500_WriteReg(CC2500_25_FSCAL1, calData[channel]);
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frskyx_rx_strobe_rx();
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}
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static void __attribute__((unused)) frskyx_rx_calibrate()
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{
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frskyx_rx_strobe_rx();
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for (unsigned c = 0; c < 47; c++)
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{
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CC2500_Strobe(CC2500_SIDLE);
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CC2500_WriteReg(CC2500_0A_CHANNR, hopping_frequency[c]);
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CC2500_Strobe(CC2500_SCAL);
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delayMicroseconds(900);
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calData[c] = CC2500_ReadReg(CC2500_25_FSCAL1);
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}
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}
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static uint8_t __attribute__((unused)) frskyx_rx_check_crc()
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{
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uint8_t limit = packet_length - 4;
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uint16_t lcrc = frskyX_crc_x(&packet[3], limit - 3); // computed crc
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uint16_t rcrc = (packet[limit] << 8) | (packet[limit + 1] & 0xff); // received crc
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return lcrc == rcrc;
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}
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static void __attribute__((unused)) frskyx_rx_build_telemetry_packet()
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{
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static uint16_t frskyx_rx_rc_chan[16];
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uint16_t pxx_channel[8];
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uint32_t bits = 0;
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uint8_t bitsavailable = 0;
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uint8_t idx = 0;
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// decode PXX channels
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pxx_channel[0] = ((packet[10] << 8) & 0xF00) | packet[9];
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pxx_channel[1] = ((packet[11] << 4) & 0xFF0) | (packet[10] >> 4);
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pxx_channel[2] = ((packet[13] << 8) & 0xF00) | packet[12];
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pxx_channel[3] = ((packet[14] << 4) & 0xFF0) | (packet[13] >> 4);
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pxx_channel[4] = ((packet[16] << 8) & 0xF00) | packet[15];
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pxx_channel[5] = ((packet[17] << 4) & 0xFF0) | (packet[16] >> 4);
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pxx_channel[6] = ((packet[19] << 8) & 0xF00) | packet[18];
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pxx_channel[7] = ((packet[20] << 4) & 0xFF0) | (packet[19] >> 4);
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for (unsigned i = 0; i < 8; i++) {
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uint8_t shifted = (pxx_channel[i] & 0x800)>0;
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uint16_t channel_value = pxx_channel[i] & 0x7FF;
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if (channel_value < 64)
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frskyx_rx_rc_chan[shifted ? i + 8 : i] = 0;
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else
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frskyx_rx_rc_chan[shifted ? i + 8 : i] = min(((channel_value - 64) << 4) / 15, 2047);
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}
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// buid telemetry packet
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pkt[idx++] = RX_LQI;
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pkt[idx++] = RX_RSSI;
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pkt[idx++] = 0; // start channel
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pkt[idx++] = 16; // number of channels in packet
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// pack channels
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for (int i = 0; i < 16; i++) {
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bits |= frskyx_rx_rc_chan[i] << bitsavailable;
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bitsavailable += 11;
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while (bitsavailable >= 8) {
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pkt[idx++] = bits & 0xff;
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bits >>= 8;
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bitsavailable -= 8;
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}
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}
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}
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uint16_t initFrSkyX_Rx()
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{
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FrSkyX_Rx_initialise();
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state = 0;
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frskyx_rx_chanskip = 1;
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hopping_frequency_no = 0;
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frskyx_rx_data_started = 0;
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frskyx_rx_finetune = 0;
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telemetry_link = 0;
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if (IS_BIND_IN_PROGRESS) {
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phase = FRSKYX_RX_TUNE_START;
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}
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else {
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uint16_t temp = FRSKYX_RX_EEPROM_OFFSET;
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rx_tx_addr[0] = eeprom_read_byte((EE_ADDR)temp++);
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rx_tx_addr[1] = eeprom_read_byte((EE_ADDR)temp++);
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rx_tx_addr[2] = eeprom_read_byte((EE_ADDR)temp++);
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frskyx_rx_finetune = eeprom_read_byte((EE_ADDR)temp++);
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for(uint8_t ch = 0; ch < 47; ch++)
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hopping_frequency[ch] = eeprom_read_byte((EE_ADDR)temp++);
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frskyx_rx_calibrate();
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CC2500_WriteReg(CC2500_18_MCSM0, 0x08); // FS_AUTOCAL = manual
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CC2500_WriteReg(CC2500_09_ADDR, rx_tx_addr[0]); // set address
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CC2500_WriteReg(CC2500_07_PKTCTRL1, 0x05); // check address
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if (option == 0)
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CC2500_WriteReg(CC2500_0C_FSCTRL0, frskyx_rx_finetune);
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else
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CC2500_WriteReg(CC2500_0C_FSCTRL0, option);
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frskyx_rx_set_channel(hopping_frequency_no);
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phase = FRSKYX_RX_DATA;
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}
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packet_length = (sub_protocol == FRSKYX_LBT) ? FRSKYX_LBT_LENGTH : FRSKYX_FCC_LENGTH;
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return 1000;
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}
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uint16_t FrSkyX_Rx_callback()
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{
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static uint32_t pps_timer=0;
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static uint8_t pps_counter=0;
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static int8_t read_retry = 0;
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static int8_t tune_low, tune_high;
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uint8_t len, ch;
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if ((prev_option != option) && (phase >= FRSKYX_RX_DATA)) {
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if (option == 0)
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CC2500_WriteReg(CC2500_0C_FSCTRL0, frskyx_rx_finetune);
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else
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CC2500_WriteReg(CC2500_0C_FSCTRL0, option);
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prev_option = option;
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}
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if (frskyx_rx_disable_lna != IS_POWER_FLAG_on) {
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frskyx_rx_disable_lna = IS_POWER_FLAG_on;
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CC2500_SetTxRxMode(frskyx_rx_disable_lna ? TXRX_OFF : RX_EN);
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}
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len = CC2500_ReadReg(CC2500_3B_RXBYTES | CC2500_READ_BURST) & 0x7F;
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switch(phase) {
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case FRSKYX_RX_TUNE_START:
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if (len >= packet_length) {
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CC2500_ReadData(packet, packet_length);
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if(packet[1] == 0x03 && packet[2] == 0x01) {
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if(frskyx_rx_check_crc()) {
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frskyx_rx_finetune = -127;
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CC2500_WriteReg(CC2500_0C_FSCTRL0, frskyx_rx_finetune);
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phase = FRSKYX_RX_TUNE_LOW;
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frskyx_rx_strobe_rx();
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return 1000;
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}
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}
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}
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frskyx_rx_finetune += 10;
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CC2500_WriteReg(CC2500_0C_FSCTRL0, frskyx_rx_finetune);
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frskyx_rx_strobe_rx();
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return 18000;
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case FRSKYX_RX_TUNE_LOW:
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if (len >= packet_length) {
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CC2500_ReadData(packet, packet_length);
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if (frskyx_rx_check_crc()) {
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tune_low = frskyx_rx_finetune;
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frskyx_rx_finetune = 127;
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CC2500_WriteReg(CC2500_0C_FSCTRL0, frskyx_rx_finetune);
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phase = FRSKYX_RX_TUNE_HIGH;
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frskyx_rx_strobe_rx();
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return 1000;
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}
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}
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frskyx_rx_finetune += 1;
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CC2500_WriteReg(CC2500_0C_FSCTRL0, frskyx_rx_finetune);
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frskyx_rx_strobe_rx();
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return 18000;
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case FRSKYX_RX_TUNE_HIGH:
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if (len >= packet_length) {
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CC2500_ReadData(packet, packet_length);
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if (frskyx_rx_check_crc()) {
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tune_high = frskyx_rx_finetune;
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frskyx_rx_finetune = (tune_low + tune_high) / 2;
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CC2500_WriteReg(CC2500_0C_FSCTRL0, (int8_t)frskyx_rx_finetune);
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if(tune_low < tune_high)
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phase = FRSKYX_RX_BIND;
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else
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phase = FRSKYX_RX_TUNE_START;
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frskyx_rx_strobe_rx();
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return 1000;
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}
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}
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frskyx_rx_finetune -= 1;
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CC2500_WriteReg(CC2500_0C_FSCTRL0, frskyx_rx_finetune);
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frskyx_rx_strobe_rx();
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return 18000;
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case FRSKYX_RX_BIND:
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if(len >= packet_length) {
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CC2500_ReadData(packet, packet_length);
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if (frskyx_rx_check_crc()) {
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if (packet[5] <= 0x2D) {
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for (ch = 0; ch < 5; ch++)
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hopping_frequency[packet[5]+ch] = packet[6+ch];
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state |= 1 << (packet[5] / 5);
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}
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}
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if (state == 0x3ff) {
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debugln("bind complete");
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frskyx_rx_calibrate();
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rx_tx_addr[0] = packet[3]; // TXID
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rx_tx_addr[1] = packet[4]; // TXID
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rx_tx_addr[2] = packet[12]; // RX #
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CC2500_WriteReg(CC2500_18_MCSM0, 0x08); // FS_AUTOCAL = manual
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CC2500_WriteReg(CC2500_09_ADDR, rx_tx_addr[0]); // set address
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CC2500_WriteReg(CC2500_07_PKTCTRL1, 0x05); // check address
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phase = FRSKYX_RX_DATA;
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frskyx_rx_set_channel(hopping_frequency_no);
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// store txid and channel list
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uint16_t temp = FRSKYX_RX_EEPROM_OFFSET;
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eeprom_write_byte((EE_ADDR)temp++, rx_tx_addr[0]);
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eeprom_write_byte((EE_ADDR)temp++, rx_tx_addr[1]);
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eeprom_write_byte((EE_ADDR)temp++, rx_tx_addr[2]);
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eeprom_write_byte((EE_ADDR)temp++, frskyx_rx_finetune);
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for (ch = 0; ch < 47; ch++)
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eeprom_write_byte((EE_ADDR)temp++, hopping_frequency[ch]);
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BIND_DONE;
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}
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frskyx_rx_strobe_rx();
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}
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return 1000;
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case FRSKYX_RX_DATA:
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if (len >= packet_length) {
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CC2500_ReadData(packet, packet_length);
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if (packet[1] == rx_tx_addr[0] && packet[2] == rx_tx_addr[1] && packet[6] == rx_tx_addr[2] && frskyx_rx_check_crc()) {
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RX_RSSI = packet[packet_length-2];
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if(RX_RSSI >= 128)
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RX_RSSI -= 128;
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else
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RX_RSSI += 128;
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// hop to next channel
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frskyx_rx_chanskip = ((packet[4] & 0xC0) >> 6) | ((packet[5] & 0x3F) << 2);
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hopping_frequency_no = (hopping_frequency_no + frskyx_rx_chanskip) % 47;
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frskyx_rx_set_channel(hopping_frequency_no);
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if(packet[7] == 0 && telemetry_link == 0) { // standard packet, send channels to TX
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frskyx_rx_build_telemetry_packet();
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telemetry_link = 1;
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}
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frskyx_rx_data_started = 1;
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read_retry = 0;
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pps_counter++;
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}
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}
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// packets per second
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if (millis() - pps_timer >= 1000) {
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pps_timer = millis();
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debugln("%ld pps", pps_counter);
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RX_LQI = pps_counter;
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pps_counter = 0;
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}
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// skip channel if no packet received in time
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if (read_retry++ >= 9) {
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hopping_frequency_no = (hopping_frequency_no + frskyx_rx_chanskip) % 47;
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frskyx_rx_set_channel(hopping_frequency_no);
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if(frskyx_rx_data_started)
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read_retry = 0;
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else
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read_retry = -50; // retry longer until first packet is catched
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}
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break;
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}
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return 1000;
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}
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#endif
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