mirror of
https://github.com/pascallanger/DIY-Multiprotocol-TX-Module.git
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524 lines
18 KiB
C
524 lines
18 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2010 Perry Hung.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file libmaple/include/libmaple/usart.h
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* @author Marti Bolivar <mbolivar@leaflabs.com>,
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* Perry Hung <perry@leaflabs.com>
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* @brief USART definitions and prototypes
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*/
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#ifndef _LIBMAPLE_USART_H_
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#define _LIBMAPLE_USART_H_
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#ifdef __cplusplus
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extern "C"{
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#endif
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#include <libmaple/libmaple_types.h>
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#include <libmaple/util.h>
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#include <libmaple/rcc.h>
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#include <libmaple/nvic.h>
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#include <libmaple/ring_buffer.h>
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/* Roger clark. Replaced with line below #include <series/usart.h>*/
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#include "stm32f1/include/series/usart.h"
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/*
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* Register map (common across supported STM32 series).
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*/
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/** USART register map type */
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typedef struct usart_reg_map {
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__io uint32 SR; /**< Status register */
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__io uint32 DR; /**< Data register */
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__io uint32 BRR; /**< Baud rate register */
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__io uint32 CR1; /**< Control register 1 */
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__io uint32 CR2; /**< Control register 2 */
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__io uint32 CR3; /**< Control register 3 */
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__io uint32 GTPR; /**< Guard time and prescaler register */
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} usart_reg_map;
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/*
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* Register bit definitions
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*/
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/* Status register */
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/** Clear to send bit */
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#define USART_SR_CTS_BIT 9
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/** Line break detection bit */
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#define USART_SR_LBD_BIT 8
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/** Transmit data register empty bit */
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#define USART_SR_TXE_BIT 7
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/** Transmission complete bit */
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#define USART_SR_TC_BIT 6
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/** Read data register not empty bit */
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#define USART_SR_RXNE_BIT 5
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/** IDLE line detected bit */
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#define USART_SR_IDLE_BIT 4
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/** Overrun error bit */
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#define USART_SR_ORE_BIT 3
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/** Noise error bit */
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#define USART_SR_NE_BIT 2
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/**
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* @brief Synonym for USART_SR_NE_BIT.
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*
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* Some series (e.g. STM32F2) use "NF" for "noise flag" instead of the
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* original "NE" for "noise error". The meaning of the bit is
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* unchanged, but the NF flag can be disabled when the line is
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* noise-free.
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*
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* @see USART_SR_NE_BIT
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*/
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#define USART_SR_NF_BIT USART_SR_NE_BIT
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/** Framing error bit */
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#define USART_SR_FE_BIT 1
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/** Parity error bit */
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#define USART_SR_PE_BIT 0
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/** Clear to send mask */
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#define USART_SR_CTS BIT(USART_SR_CTS_BIT)
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/** Line break detected mask */
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#define USART_SR_LBD BIT(USART_SR_LBD_BIT)
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/** Transmit data register empty mask */
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#define USART_SR_TXE BIT(USART_SR_TXE_BIT)
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/** Transmission complete mask */
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#define USART_SR_TC BIT(USART_SR_TC_BIT)
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/** Read data register not empty mask */
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#define USART_SR_RXNE BIT(USART_SR_RXNE_BIT)
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/** IDLE line detected mask */
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#define USART_SR_IDLE BIT(USART_SR_IDLE_BIT)
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/** Overrun error mask */
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#define USART_SR_ORE BIT(USART_SR_ORE_BIT)
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/** Noise error mask */
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#define USART_SR_NE BIT(USART_SR_NE_BIT)
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/**
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* @brief Synonym for USART_SR_NE.
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* @see USART_SR_NF_BIT
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*/
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#define USART_SR_NF USART_SR_NE
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/** Framing error mask */
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#define USART_SR_FE BIT(USART_SR_FE_BIT)
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/** Parity error mask */
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#define USART_SR_PE BIT(USART_SR_PE_BIT)
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/* Data register */
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/** Data register data value mask */
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#define USART_DR_DR 0xFF
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/* Baud rate register */
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/** Mantissa of USARTDIV mask */
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#define USART_BRR_DIV_MANTISSA (0xFFF << 4)
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/** Fraction of USARTDIV mask */
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#define USART_BRR_DIV_FRACTION 0xF
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/* Control register 1 */
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/** USART enable bit */
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#define USART_CR1_UE_BIT 13
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/** Word length bit */
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#define USART_CR1_M_BIT 12
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/** Wakeup method bit */
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#define USART_CR1_WAKE_BIT 11
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/** Parity control enable bit */
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#define USART_CR1_PCE_BIT 10
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/** Parity selection bit */
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#define USART_CR1_PS_BIT 9
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/** Parity error interrupt enable bit */
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#define USART_CR1_PEIE_BIT 8
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/** Transmit data regsiter not empty interrupt enable bit */
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#define USART_CR1_TXEIE_BIT 7
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/** Transmission complete interrupt enable bit */
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#define USART_CR1_TCIE_BIT 6
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/** RXNE interrupt enable bit */
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#define USART_CR1_RXNEIE_BIT 5
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/** IDLE interrupt enable bit */
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#define USART_CR1_IDLEIE_BIT 4
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/** Transmitter enable bit */
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#define USART_CR1_TE_BIT 3
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/** Receiver enable bit */
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#define USART_CR1_RE_BIT 2
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/** Receiver wakeup bit */
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#define USART_CR1_RWU_BIT 1
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/** Send break bit */
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#define USART_CR1_SBK_BIT 0
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/** USART enable mask */
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#define USART_CR1_UE BIT(USART_CR1_UE_BIT)
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/** Word length mask */
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#define USART_CR1_M BIT(USART_CR1_M_BIT)
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/** Word length: 1 start bit, 8 data bits, n stop bit */
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#define USART_CR1_M_8N1 (0 << USART_CR1_M_BIT)
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/** Word length: 1 start bit, 9 data bits, n stop bit */
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#define USART_CR1_M_9N1 (1 << USART_CR1_M_BIT)
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/** Wakeup method mask */
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#define USART_CR1_WAKE BIT(USART_CR1_WAKE_BIT)
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/** Wakeup on idle line */
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#define USART_CR1_WAKE_IDLE (0 << USART_CR1_WAKE_BIT)
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/** Wakeup on address mark */
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#define USART_CR1_WAKE_ADDR (1 << USART_CR1_WAKE_BIT)
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/** Parity control enable mask */
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#define USART_CR1_PCE BIT(USART_CR1_PCE_BIT)
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/** Parity selection mask */
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#define USART_CR1_PS BIT(USART_CR1_PS_BIT)
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/** Parity selection: even parity */
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#define USART_CR1_PS_EVEN (0 << USART_CR1_PS_BIT)
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/** Parity selection: odd parity */
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#define USART_CR1_PS_ODD (1 << USART_CR1_PS_BIT)
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/** Parity error interrupt enable mask */
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#define USART_CR1_PEIE BIT(USART_CR1_PEIE_BIT)
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/** Transmit data register empty interrupt enable mask */
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#define USART_CR1_TXEIE BIT(USART_CR1_TXEIE_BIT)
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/** Transmission complete interrupt enable mask */
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#define USART_CR1_TCIE BIT(USART_CR1_TCIE_BIT)
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/** RXNE interrupt enable mask */
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#define USART_CR1_RXNEIE BIT(USART_CR1_RXNEIE_BIT)
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/** IDLE line interrupt enable mask */
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#define USART_CR1_IDLEIE BIT(USART_CR1_IDLEIE_BIT)
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/** Transmitter enable mask */
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#define USART_CR1_TE BIT(USART_CR1_TE_BIT)
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/** Receiver enable mask */
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#define USART_CR1_RE BIT(USART_CR1_RE_BIT)
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/** Receiver wakeup mask */
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#define USART_CR1_RWU BIT(USART_CR1_RWU_BIT)
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/** Receiver wakeup: receiver in active mode */
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#define USART_CR1_RWU_ACTIVE (0 << USART_CR1_RWU_BIT)
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/** Receiver wakeup: receiver in mute mode */
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#define USART_CR1_RWU_MUTE (1 << USART_CR1_RWU_BIT)
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/** Send break */
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#define USART_CR1_SBK BIT(USART_CR1_SBK_BIT)
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/* Control register 2 */
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/** LIN mode enable bit */
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#define USART_CR2_LINEN_BIT 14
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/** Clock enable bit */
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#define USART_CR2_CLKEN_BIT 11
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/** Clock polarity bit */
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#define USART_CR2_CPOL_BIT 10
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/** Clock phase bit */
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#define USART_CR2_CPHA_BIT 9
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/** Last bit clock pulse bit */
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#define USART_CR2_LBCL_BIT 8
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/** LIN break detection interrupt enable bit */
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#define USART_CR2_LBDIE_BIT 6
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/** LIN break detection length bit */
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#define USART_CR2_LBDL_BIT 5
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/** LIN mode enable mask */
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#define USART_CR2_LINEN BIT(USART_CR2_LINEN_BIT)
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/** STOP bits mask */
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#define USART_CR2_STOP (0x3 << 12)
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/** STOP bits: 1 stop bit */
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#define USART_CR2_STOP_BITS_1 (0x0 << 12)
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/**
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* @brief STOP bits: 0.5 stop bits
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* Not available on UART4, UART5. */
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#define USART_CR2_STOP_BITS_POINT_5 (0x1 << 12)
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/** STOP bits: 2 stop bits */
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#define USART_CR2_STOP_BITS_2 (0x2 << 12)
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/**
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* @brief STOP bits: 1.5 stop bits
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* Not available on UART4, UART5. */
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#define USART_CR2_STOP_BITS_1_POINT_5 (0x3 << 12)
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/**
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* @brief Clock enable.
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* Not available on UART4, UART5 */
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#define USART_CR2_CLKEN BIT(USART_CR2_CLKEN_BIT)
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/**
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* @brief Clock polarity mask.
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* Not available on UART4, UART5 */
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#define USART_CR2_CPOL BIT(USART_CR2_CPOL_BIT)
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/** Clock polarity: low */
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#define USART_CR2_CPOL_LOW (0x0 << USART_CR2_CLKEN_BIT)
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/** Clock polarity: high */
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#define USART_CR2_CPOL_HIGH (0x1 << USART_CR2_CLKEN_BIT)
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/**
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* @brief Clock phase mask.
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* Not available on UART4, UART5 */
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#define USART_CR2_CPHA BIT(USART_CR2_CPHA_BIT)
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/**
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* @brief Clock phase: first
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* First clock transition is the first data capture edge. */
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#define USART_CR2_CPHA_FIRST (0x0 << USART_CR2_CPHA_BIT)
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/**
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* @brief Clock phase: second
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* Second clock transition is the first data capture edge. */
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#define USART_CR2_CPHA_SECOND (0x1 << USART_CR2_CPHA_BIT)
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/**
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* @brief Last bit clock pulse mask.
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*
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* When set, the last bit transmitted causes a clock pulse in
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* synchronous mode.
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*
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* Not available on UART4, UART5 */
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#define USART_CR2_LBCL BIT(USART_CR2_LBCL_BIT)
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/** LIN break detection interrupt enable mask. */
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#define USART_CR2_LBDIE BIT(USART_CR2_LBDIE_BIT)
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/** LIN break detection length. */
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#define USART_CR2_LBDL BIT(USART_CR2_LBDL_BIT)
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/** LIN break detection length: 10 bits */
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#define USART_CR2_LBDL_10_BIT (0 << USART_CR2_LBDL_BIT)
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/** LIN break detection length: 11 bits */
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#define USART_CR2_LBDL_11_BIT (1 << USART_CR2_LBDL_BIT)
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/**
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* @brief Address of the USART node
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* This is useful during multiprocessor communication. */
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#define USART_CR2_ADD 0xF
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/* Control register 3 */
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/** Clear to send interrupt enable bit */
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#define USART_CR3_CTSIE_BIT 10
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/** Clear to send enable bit */
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#define USART_CR3_CTSE_BIT 9
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/** Ready to send enable bit */
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#define USART_CR3_RTSE_BIT 8
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/** DMA enable transmitter bit */
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#define USART_CR3_DMAT_BIT 7
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/** DMA enable receiver bit */
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#define USART_CR3_DMAR_BIT 6
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/** Smartcard mode enable bit */
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#define USART_CR3_SCEN_BIT 5
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/** Smartcard NACK enable bit */
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#define USART_CR3_NACK_BIT 4
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/** Half-duplex selection bit */
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#define USART_CR3_HDSEL_BIT 3
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/** IrDA low power bit */
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#define USART_CR3_IRLP_BIT 2
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/** IrDA mode enable bit */
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#define USART_CR3_IREN_BIT 1
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/** Error interrupt enable bit */
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#define USART_CR3_EIE_BIT 0
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/**
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* @brief Clear to send interrupt enable
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* Not available on UART4, UART5. */
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#define USART_CR3_CTSIE BIT(USART_CR3_CTSIE_BIT)
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/**
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* @brief Clear to send enable
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* Not available on UART4, UART5. */
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#define USART_CR3_CTSE BIT(USART_CR3_CTSE_BIT)
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/**
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* @brief Ready to send enable
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* Not available on UART4, UART5. */
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#define USART_CR3_RTSE BIT(USART_CR3_RTSE_BIT)
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/**
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* @brief DMA enable transmitter
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* Not available on UART5. */
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#define USART_CR3_DMAT BIT(USART_CR3_DMAT_BIT)
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/**
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* @brief DMA enable receiver
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* Not available on UART5. */
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#define USART_CR3_DMAR BIT(USART_CR3_DMAR_BIT)
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/**
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* @brief Smartcard mode enable
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* Not available on UART4, UART5. */
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#define USART_CR3_SCEN BIT(USART_CR3_SCEN_BIT)
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/**
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* @brief Smartcard NACK enable
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* Not available on UART4, UART5. */
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#define USART_CR3_NACK BIT(USART_CR3_NACK_BIT)
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/**
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* @brief Half-duplex selection
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* When set, single-wire half duplex mode is selected.
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*/
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#define USART_CR3_HDSEL BIT(USART_CR3_HDSEL_BIT)
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/** IrDA low power mode */
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#define USART_CR3_IRLP BIT(USART_CR3_IRLP_BIT)
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/** IrDA mode: normal */
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#define USART_CR3_IRLP_NORMAL (0U << USART_CR3_IRLP_BIT)
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/** IrDA mode: low power */
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#define USART_CR3_IRLP_LOW_POWER (1U << USART_CR3_IRLP_BIT)
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/** IrDA mode enable */
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#define USART_CR3_IREN BIT(USART_CR3_IREN_BIT)
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/** Error interrupt enable */
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#define USART_CR3_EIE BIT(USART_CR3_EIE_BIT)
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/* Guard time and prescaler register */
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/**
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* @brief Guard time value mask
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* Used in Smartcard mode. Not available on UART4, UART5. */
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#define USART_GTPR_GT (0xFF << 8)
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/**
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* @brief Prescaler value mask
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* Restrictions on this value apply, depending on the USART mode. Not
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* available on UART4, UART5. */
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#define USART_GTPR_PSC 0xFF
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/*
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* Devices
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*/
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#ifndef USART_RX_BUF_SIZE
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#define USART_RX_BUF_SIZE 64
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#endif
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#ifndef USART_TX_BUF_SIZE
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#define USART_TX_BUF_SIZE 64
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#endif
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/** USART device type */
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typedef struct usart_dev {
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usart_reg_map *regs; /**< Register map */
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ring_buffer *rb; /**< RX ring buffer */
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ring_buffer *wb; /**< TX ring buffer */
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uint32 max_baud; /**< @brief Deprecated.
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* Maximum baud rate. */
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uint8 rx_buf[USART_RX_BUF_SIZE]; /**< @brief Deprecated.
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* Actual RX buffer used by rb.
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* This field will be removed in
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* a future release. */
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uint8 tx_buf[USART_TX_BUF_SIZE]; /**< Actual TX buffer used by wb */
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rcc_clk_id clk_id; /**< RCC clock information */
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nvic_irq_num irq_num; /**< USART NVIC interrupt */
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} usart_dev;
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void usart_init(usart_dev *dev);
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struct gpio_dev; /* forward declaration */
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/* FIXME [PRE 0.0.13] decide if flags are necessary */
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/**
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* @brief Configure GPIOs for use as USART TX/RX.
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* @param udev USART device to use
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* @param rx_dev RX pin gpio_dev
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* @param rx RX pin bit on rx_dev
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* @param tx_dev TX pin gpio_dev
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* @param tx TX pin bit on tx_dev
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* @param flags Currently ignored
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*/
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extern void usart_config_gpios_async(usart_dev *udev,
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struct gpio_dev *rx_dev, uint8 rx,
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struct gpio_dev *tx_dev, uint8 tx,
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unsigned flags);
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#define USART_USE_PCLK 0
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void usart_set_baud_rate(usart_dev *dev, uint32 clock_speed, uint32 baud);
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void usart_enable(usart_dev *dev);
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void usart_disable(usart_dev *dev);
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void usart_foreach(void (*fn)(usart_dev *dev));
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uint32 usart_tx(usart_dev *dev, const uint8 *buf, uint32 len);
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uint32 usart_rx(usart_dev *dev, uint8 *buf, uint32 len);
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void usart_putudec(usart_dev *dev, uint32 val);
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/**
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* @brief Disable all serial ports.
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*/
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static inline void usart_disable_all(void) {
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usart_foreach(usart_disable);
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}
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/**
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* @brief Transmit one character on a serial port.
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*
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* This function blocks until the character has been queued
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* for transmission.
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*
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* @param dev Serial port to send on.
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* @param byte Byte to transmit.
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*/
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static inline void usart_putc(usart_dev* dev, uint8 byte) {
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while (!usart_tx(dev, &byte, 1))
|
|
;
|
|
}
|
|
|
|
/**
|
|
* @brief Transmit a character string on a serial port.
|
|
*
|
|
* This function blocks until str is completely transmitted.
|
|
*
|
|
* @param dev Serial port to send on
|
|
* @param str String to send
|
|
*/
|
|
static inline void usart_putstr(usart_dev *dev, const char* str) {
|
|
uint32 i = 0;
|
|
while (str[i] != '\0') {
|
|
usart_putc(dev, str[i++]);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Read one character from a serial port.
|
|
*
|
|
* It's not safe to call this function if the serial port has no data
|
|
* available.
|
|
*
|
|
* @param dev Serial port to read from
|
|
* @return byte read
|
|
* @see usart_data_available()
|
|
*/
|
|
static inline uint8 usart_getc(usart_dev *dev) {
|
|
return rb_remove(dev->rb);
|
|
}
|
|
|
|
/*
|
|
* Roger Clark. 20141125,
|
|
* added peek function.
|
|
* @param dev Serial port to read from
|
|
* @return byte read
|
|
*/
|
|
static inline int usart_peek(usart_dev *dev)
|
|
{
|
|
return rb_peek(dev->rb);
|
|
}
|
|
|
|
|
|
/**
|
|
* @brief Return the amount of data available in a serial port's RX buffer.
|
|
* @param dev Serial port to check
|
|
* @return Number of bytes in dev's RX buffer.
|
|
*/
|
|
static inline uint32 usart_data_available(usart_dev *dev) {
|
|
return rb_full_count(dev->rb);
|
|
}
|
|
|
|
/**
|
|
* @brief Discard the contents of a serial port's RX buffer.
|
|
* @param dev Serial port whose buffer to empty.
|
|
*/
|
|
static inline void usart_reset_rx(usart_dev *dev) {
|
|
rb_reset(dev->rb);
|
|
}
|
|
|
|
/**
|
|
* @brief Discard the contents of a serial port's RX buffer.
|
|
* @param dev Serial port whose buffer to empty.
|
|
*/
|
|
static inline void usart_reset_tx(usart_dev *dev) {
|
|
rb_reset(dev->wb);
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
} // extern "C"
|
|
#endif
|
|
|
|
#endif
|