mirror of
https://github.com/pascallanger/DIY-Multiprotocol-TX-Module.git
synced 2025-02-04 22:38:14 +00:00
272 lines
7.3 KiB
C++
272 lines
7.3 KiB
C++
/*
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This project is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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Multiprotocol is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Multiprotocol. If not, see <http://www.gnu.org/licenses/>.
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*/
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/********************/
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/** A7105 routines **/
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/********************/
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#ifdef A7105_INSTALLED
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#include "iface_a7105.h"
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void A7105_WriteData(uint8_t len, uint8_t channel)
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{
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uint8_t i;
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A7105_CSN_off;
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SPI_Write(A7105_RST_WRPTR);
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SPI_Write(A7105_05_FIFO_DATA);
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for (i = 0; i < len; i++)
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SPI_Write(packet[i]);
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A7105_CSN_on;
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if(protocol!=MODE_FLYSKY)
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{
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A7105_Strobe(A7105_STANDBY); //Force standby mode, ie cancel any TX or RX...
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A7105_SetTxRxMode(TX_EN); //Switch to PA
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}
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A7105_WriteReg(A7105_0F_PLL_I, channel);
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A7105_Strobe(A7105_TX);
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}
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void A7105_ReadData(uint8_t len)
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{
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uint8_t i;
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A7105_Strobe(A7105_RST_RDPTR);
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A7105_CSN_off;
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SPI_Write(0x40 | A7105_05_FIFO_DATA); //bit 6 =1 for reading
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for (i=0;i<len;i++)
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packet[i]=SPI_SDI_Read();
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A7105_CSN_on;
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}
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void A7105_WriteReg(uint8_t address, uint8_t data) {
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A7105_CSN_off;
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SPI_Write(address);
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NOP();
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SPI_Write(data);
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A7105_CSN_on;
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}
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uint8_t A7105_ReadReg(uint8_t address)
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{
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uint8_t result;
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A7105_CSN_off;
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SPI_Write(address |=0x40); //bit 6 =1 for reading
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result = SPI_SDI_Read();
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A7105_CSN_on;
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return(result);
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}
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//------------------------
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void A7105_SetTxRxMode(uint8_t mode)
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{
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if(mode == TX_EN)
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{
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A7105_WriteReg(A7105_0B_GPIO1_PIN1, 0x33);
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A7105_WriteReg(A7105_0C_GPIO2_PIN_II, 0x31);
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}
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else
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if (mode == RX_EN)
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{
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A7105_WriteReg(A7105_0B_GPIO1_PIN1, 0x31);
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A7105_WriteReg(A7105_0C_GPIO2_PIN_II, 0x33);
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}
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else
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{
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//The A7105 seems to some with a cross-wired power-amp (A7700)
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//On the XL7105-D03, TX_EN -> RXSW and RX_EN -> TXSW
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//This means that sleep mode is wired as RX_EN = 1 and TX_EN = 1
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//If there are other amps in use, we'll need to fix this
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A7105_WriteReg(A7105_0B_GPIO1_PIN1, 0x33);
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A7105_WriteReg(A7105_0C_GPIO2_PIN_II, 0x33);
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}
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}
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//------------------------
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uint8_t A7105_Reset()
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{
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uint8_t result;
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A7105_WriteReg(A7105_00_MODE, 0x00);
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delayMilliseconds(1);
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A7105_SetTxRxMode(TXRX_OFF); //Set both GPIO as output and low
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result=A7105_ReadReg(A7105_10_PLL_II) == 0x9E; //check if is reset.
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A7105_Strobe(A7105_STANDBY);
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return result;
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}
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void A7105_WriteID(uint32_t ida)
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{
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A7105_CSN_off;
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SPI_Write(A7105_06_ID_DATA); //ex id=0x5475c52a ;txid3txid2txid1txid0
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SPI_Write((ida>>24)&0xff); //53
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SPI_Write((ida>>16)&0xff); //75
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SPI_Write((ida>>8)&0xff); //c5
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SPI_Write((ida>>0)&0xff); //2a
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A7105_CSN_on;
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}
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/*
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static void A7105_SetPower_Value(int power)
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{
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//Power amp is ~+16dBm so:
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//TXPOWER_100uW = -23dBm == PAC=0 TBG=0
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//TXPOWER_300uW = -20dBm == PAC=0 TBG=1
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//TXPOWER_1mW = -16dBm == PAC=0 TBG=2
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//TXPOWER_3mW = -11dBm == PAC=0 TBG=4
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//TXPOWER_10mW = -6dBm == PAC=1 TBG=5
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//TXPOWER_30mW = 0dBm == PAC=2 TBG=7
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//TXPOWER_100mW = 1dBm == PAC=3 TBG=7
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//TXPOWER_150mW = 1dBm == PAC=3 TBG=7
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uint8_t pac, tbg;
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switch(power) {
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case 0: pac = 0; tbg = 0; break;
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case 1: pac = 0; tbg = 1; break;
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case 2: pac = 0; tbg = 2; break;
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case 3: pac = 0; tbg = 4; break;
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case 4: pac = 1; tbg = 5; break;
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case 5: pac = 2; tbg = 7; break;
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case 6: pac = 3; tbg = 7; break;
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case 7: pac = 3; tbg = 7; break;
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default: pac = 0; tbg = 0; break;
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};
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A7105_WriteReg(0x28, (pac << 3) | tbg);
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}
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*/
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void A7105_SetPower()
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{
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uint8_t power=A7105_BIND_POWER;
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if(IS_BIND_DONE_on)
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#ifdef A7105_ENABLE_LOW_POWER
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power=IS_POWER_FLAG_on?A7105_HIGH_POWER:A7105_LOW_POWER;
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#else
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power=A7105_HIGH_POWER;
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#endif
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if(IS_RANGE_FLAG_on)
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power=A7105_RANGE_POWER;
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if(prev_power != power)
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{
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A7105_WriteReg(A7105_28_TX_TEST, power);
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prev_power=power;
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}
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}
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void A7105_Strobe(uint8_t address) {
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A7105_CSN_off;
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SPI_Write(address);
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A7105_CSN_on;
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}
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#ifdef HUBSAN_A7105_INO
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const uint8_t PROGMEM HUBSAN_A7105_regs[] = {
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0xFF, 0x63, 0xFF, 0x0F, 0xFF, 0xFF, 0xFF ,0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x05, 0x04, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x2B, 0xFF, 0xFF, 0x62, 0x80, 0xFF, 0xFF, 0x0A, 0xFF, 0xFF, 0x07,
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0x17, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x47, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF
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};
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#endif
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#ifdef FLYSKY_A7105_INO
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const uint8_t PROGMEM FLYSKY_A7105_regs[] = {
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0xff, 0x42, 0x00, 0x14, 0x00, 0xff, 0xff ,0x00, 0x00, 0x00, 0x00, 0x01, 0x21, 0x05, 0x00, 0x50,
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0x9e, 0x4b, 0x00, 0x02, 0x16, 0x2b, 0x12, 0x00, 0x62, 0x80, 0x80, 0x00, 0x0a, 0x32, 0xc3, 0x0f,
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0x13, 0xc3, 0x00, 0xff, 0x00, 0x00, 0x3b, 0x00, 0x17, 0x47, 0x80, 0x03, 0x01, 0x45, 0x18, 0x00,
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0x01, 0x0f
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};
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#endif
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#ifdef AFHDS2A_A7105_INO
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const uint8_t PROGMEM AFHDS2A_A7105_regs[] = {
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0xFF, 0x42 | (1<<5), 0x00, 0x25, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x01, 0x3c, 0x05, 0x00, 0x50, // 00 - 0f
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0x9e, 0x4b, 0x00, 0x02, 0x16, 0x2b, 0x12, 0x4f, 0x62, 0x80, 0xFF, 0xFF, 0x2a, 0x32, 0xc3, 0x1f, // 10 - 1f
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0x1e, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0x3b, 0x00, 0x17, 0x47, 0x80, 0x03, 0x01, 0x45, 0x18, 0x00, // 20 - 2f
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0x01, 0x0f // 30 - 31
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};
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#endif
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#define ID_NORMAL 0x55201041
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#define ID_PLUS 0xAA201041
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void A7105_Init(void)
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{
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uint8_t *A7105_Regs=0;
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#ifdef HUBSAN_A7105_INO
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if(protocol==MODE_HUBSAN)
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{
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A7105_WriteID(ID_NORMAL);
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A7105_Regs=(uint8_t*)HUBSAN_A7105_regs;
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}
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else
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#endif
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{
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A7105_WriteID(0x5475c52A);//0x2Ac57554
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#ifdef FLYSKY_A7105_INO
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if(protocol==MODE_FLYSKY)
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A7105_Regs=(uint8_t*)FLYSKY_A7105_regs;
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else
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#endif
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{
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#ifdef AFHDS2A_A7105_INO
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A7105_Regs=(uint8_t*)AFHDS2A_A7105_regs;
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#endif
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}
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}
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for (uint8_t i = 0; i < 0x32; i++)
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{
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uint8_t val=pgm_read_byte_near(&A7105_Regs[i]);
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#ifdef FLYSKY_A7105_INO
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if(protocol==MODE_FLYSKY && sub_protocol==CX20)
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{
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if(i==0x0E) val=0x01;
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if(i==0x1F) val=0x1F;
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if(i==0x20) val=0x1E;
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}
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#endif
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if( val != 0xFF)
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A7105_WriteReg(i, val);
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}
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A7105_Strobe(A7105_STANDBY);
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//IF Filter Bank Calibration
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A7105_WriteReg(A7105_02_CALC,1);
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while(A7105_ReadReg(A7105_02_CALC)); // Wait for calibration to end
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// A7105_ReadReg(A7105_22_IF_CALIB_I);
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// A7105_ReadReg(A7105_24_VCO_CURCAL);
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if(protocol!=MODE_HUBSAN)
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{
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//VCO Current Calibration
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A7105_WriteReg(A7105_24_VCO_CURCAL,0x13); //Recommended calibration from A7105 Datasheet
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//VCO Bank Calibration
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A7105_WriteReg(A7105_26_VCO_SBCAL_II,0x3b); //Recommended calibration from A7105 Datasheet
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}
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//VCO Bank Calibrate channel 0
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A7105_WriteReg(A7105_0F_CHANNEL, 0);
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A7105_WriteReg(A7105_02_CALC,2);
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while(A7105_ReadReg(A7105_02_CALC)); // Wait for calibration to end
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// A7105_ReadReg(A7105_25_VCO_SBCAL_I);
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//VCO Bank Calibrate channel A0
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A7105_WriteReg(A7105_0F_CHANNEL, 0xa0);
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A7105_WriteReg(A7105_02_CALC, 2);
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while(A7105_ReadReg(A7105_02_CALC)); // Wait for calibration to end
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// A7105_ReadReg(A7105_25_VCO_SBCAL_I);
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//Reset VCO Band calibration
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if(protocol!=MODE_HUBSAN)
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A7105_WriteReg(A7105_25_VCO_SBCAL_I,protocol==MODE_FLYSKY?0x08:0x0A);
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A7105_SetTxRxMode(TX_EN);
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A7105_SetPower();
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A7105_Strobe(A7105_STANDBY);
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}
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#endif |