mirror of
https://github.com/pascallanger/DIY-Multiprotocol-TX-Module.git
synced 2025-03-15 21:09:10 +00:00
232 lines
5.7 KiB
C++
232 lines
5.7 KiB
C++
/*
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This project is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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Multiprotocol is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Multiprotocol. If not, see <http://www.gnu.org/licenses/>.
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*/
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#if defined(SHENQI2_NRF24L01_INO)
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#include "iface_xn297.h"
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//#define FORCE_SHENQI2_ORIGINAL_ID
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#define SHENQI2_PAYLOAD_SIZE 8
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#define SHENQI2_RF_NUM_CHANNELS 16
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#define SHENQI2_BIND_COUNT 2000
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#define SHENQI2_WRITE_TIME 650
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#define SHENQI2_BIND_CHANNEL 44
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#define SHENQI2_PACKET_PERIOD 8210
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enum {
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SHENQI2_BIND = 0,
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SHENQI2_BIND_RX,
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SHENQI2_DATA,
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};
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static void __attribute__((unused)) SHENQI2_send_packet()
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{
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if(bind_counter)
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{
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bind_counter--;
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if(!bind_counter)
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BIND_DONE;
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}
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memset(packet, 0x00, SHENQI2_PAYLOAD_SIZE);
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packet_count &= 0x0F;
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packet[0] = packet_count;
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memcpy(&packet[1],rx_tx_addr,5);
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if(IS_BIND_DONE)
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{//Normal
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uint8_t val = convert_channel_8b(CH2);
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if(val < 0x70)
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val = 0x30;
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else if(val < 0x80)
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val = 0x00;
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else
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{
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val &= 0x7F;
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val >>= 2;
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}
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if(Channel_data[CH1] > 1024+50)
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val |= 0x40;
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else if(Channel_data[CH1] < 1024-50)
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val |= 0x80;
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packet[6] = val;
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//packet[7] = 0x00; // ??
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}
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else
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packet[0] |= 0x30;
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// Send
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XN297_SetPower();
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XN297_SetTxRxMode(TX_EN);
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XN297_WriteEnhancedPayload(packet, SHENQI2_PAYLOAD_SIZE, false);
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#ifdef DEBUG_SERIAL
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for(uint8_t i=0; i < SHENQI2_PAYLOAD_SIZE; i++)
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debug("%02X ", packet[i]);
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debugln();
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#endif
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}
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static void __attribute__((unused)) SHENQI2_initialize_txid()
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{
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#ifdef FORCE_SHENQI2_ORIGINAL_ID
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//TXID
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rx_tx_addr[0] = 0x51;
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rx_tx_addr[1] = 0x70;
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rx_tx_addr[2] = 0x02;
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//RXID
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rx_tx_addr[3] = 0x46;
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rx_tx_addr[4] = 0xBE;
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#endif
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rx_tx_addr[3] = 0x00;
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rx_tx_addr[4] = 0x00;
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//Freq
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memcpy(hopping_frequency,(uint8_t*)"\x05\x09\x0E\x0F\x17\x1C\x21\x27\x2A\x2C\x33\x39\x3D\x42\x48\x4C",16);
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}
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static void __attribute__((unused)) SHENQI2_RF_init()
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{
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XN297_Configure(XN297_CRCEN, XN297_SCRAMBLED, XN297_1M);
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//Address
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XN297_SetTXAddr((uint8_t*)"\x74\xD1\x3A\xF5\x6C", 5);
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XN297_SetRXAddr((uint8_t*)"\x74\xD1\x3A\xF5\x6C", SHENQI2_PAYLOAD_SIZE);
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XN297_RFChannel(SHENQI2_BIND_CHANNEL);
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}
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uint16_t SHENQI2_callback()
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{
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static bool rx=false;
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switch(phase)
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{
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case SHENQI2_BIND:
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rx = XN297_IsRX();
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XN297_SetTxRxMode(TXRX_OFF);
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SHENQI2_send_packet();
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packet_count++;
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if(rx)
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{
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uint8_t val=XN297_ReadEnhancedPayload(packet_in, SHENQI2_PAYLOAD_SIZE);
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if(val == SHENQI2_PAYLOAD_SIZE)
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{
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if(memcmp(rx_tx_addr, packet_in, 3) == 0)
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{//Good packet with our TXID
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BIND_DONE;
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rx_tx_addr[3] = packet_in[3];
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rx_tx_addr[4] = packet_in[4];
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packet_count = 0;
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phase = SHENQI2_DATA;
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}
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#ifdef DEBUG_SERIAL
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for(uint8_t i=0; i < SHENQI2_PAYLOAD_SIZE; i++)
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debug(" %02X", packet_in[i]);
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debugln();
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#endif
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}
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}
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phase++;
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return SHENQI2_WRITE_TIME;
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case SHENQI2_BIND_RX:
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XN297_SetTxRxMode(TXRX_OFF);
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XN297_SetTxRxMode(RX_EN);
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phase = SHENQI2_BIND;
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return SHENQI2_PACKET_PERIOD - SHENQI2_WRITE_TIME;
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default: //SHENQI2_DATA
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//Since I don't know the order of the channels, I'm hopping on all the channels quickly
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//Refresh rate from the motorcycle perspective is 32ms instead of 8ms...
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XN297_Hopping(hopping_frequency_no);
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hopping_frequency_no++;
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hopping_frequency_no &= 0x0F;
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SHENQI2_send_packet();
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if(hopping_frequency_no%4 == 0)
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packet_count++;
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return SHENQI2_PACKET_PERIOD/4;
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}
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return 0;
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}
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void SHENQI2_init()
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{
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BIND_IN_PROGRESS;
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SHENQI2_initialize_txid();
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SHENQI2_RF_init();
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bind_counter = SHENQI2_BIND_COUNT;
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phase = SHENQI2_BIND;
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hopping_frequency_no = 0;
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}
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#endif
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/*
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XN297 1Mb Enhanced,Acked,Scrambled
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Bind
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---
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RX on channel: 44, Time: 2890us P: 34 51 70 02 00 00 00 00
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RX on channel: 44, Time: 1780us P: 34 51 70 02 00 00 00 00
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RX on channel: 44, Time: 1773us P: 34 51 70 02 00 00 00 00
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RX on channel: 44, Time: 1772us P: 34 51 70 02 00 00 00 00
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RX on channel: 44, Time: 2889us P: 35 51 70 02 00 00 00 00
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RX on channel: 44, Time: 1769us P: 35 51 70 02 00 00 00 00
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RX on channel: 44, Time: 1774us P: 35 51 70 02 00 00 00 00
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RX on channel: 44, Time: 1771us P: 35 51 70 02 00 00 00 00
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RX on channel: 44, Time: 2894us P: 36 51 70 02 00 00 00 00
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A= 74 D1 3A F5 6C
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RF:44
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Timing: 1772µs between the same 4 packets, 2892µs to the next packet, 8208µs between 2 packets
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Request ack, if no ack repeat the packet 4 times
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P[0] = counter 00..0F | 30 bind
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P[1] = TXID[0]
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P[2] = TXID[1]
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P[3] = TXID[2]
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P[4] = RXID[0]
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P[5] = RXID[1]
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P[6] = TH 00..1F, Break 30, 40 ST_right, 80 ST_left
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P[7] = 00?
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Answer from motorcycle:
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P: 51 70 02 46 BE 00 00 00
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P[0] = TXID[0]
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P[1] = TXID[1]
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P[2] = TXID[2]
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P[3] = RXID[0]
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P[4] = RXID[1]
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P[5] = 00
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P[6] = 00
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P[7] = 00
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Normal packets
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---
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A= 74 D1 3A F5 6C
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RF:5,9,14,15,23,28,33,39,42,44,51,57,61,66,72,76
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RF:\x05\x09\x0E\x0F\x17\x1C\x21\x27\x2A\x2C\x33\x39\x3D\x42\x48\x4C
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- order of the channels is unknown and vary over time
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- send 16 times on each channel and switch (counter 00..0F)
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Timing:1772µs between the same 4 packets, 2892µs to the next packet, 8208µs between 2 packets
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Timing:8208 between packets if acked
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P: 00 51 70 02 46 BE 00 00
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P[0] = counter 00..0F
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P[1] = TXID[0]
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P[2] = TXID[1]
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P[3] = TXID[2]
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P[4] = RXID[0]
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P[5] = RXID[1]
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P[6] = TH 00..1F, Break 30, 40 ST_right, 80 ST_left
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P[7] = 00?
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*/ |