mirror of
https://github.com/pascallanger/DIY-Multiprotocol-TX-Module.git
synced 2025-02-04 20:38:14 +00:00
984aa3f413
- Change how PPM is handled with a resolution of 2048 and scaled to match serial input range. PPM is now fully scaled for all protocols which was not the case before. If you are using PPM, you might have to adjust the end points depending on the protocols. - Change all range conversions to use 2048 where possible - Updated all protocols with new range functions - Protocols which are taking advantage of 2048 are Assan, FrSky V/D/X, DSM, Devo, WK2x01 - Renamed AUX xto CHx for code readbility
92 lines
2.5 KiB
C
92 lines
2.5 KiB
C
//#define ARDUINO_AVR_PRO 1
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#define ORANGE_TX 1
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#include <stdlib.h>
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#include <string.h>
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#include <avr/interrupt.h>
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#define yield()
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#define clockCyclesPerMicrosecond() ( F_CPU / 1000000L )
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#define clockCyclesToMicroseconds(a) ( (a) / clockCyclesPerMicrosecond() )
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// the prescaler is set so that timer0 ticks every 64 clock cycles, and the
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// the overflow handler is called every 256 ticks.
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#define MICROSECONDS_PER_TIMER0_OVERFLOW (clockCyclesToMicroseconds(64 * 256))
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// the whole number of milliseconds per timer0 overflow
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#define MILLIS_INC (MICROSECONDS_PER_TIMER0_OVERFLOW / 1000)
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// the fractional number of milliseconds per timer0 overflow. we shift right
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// by three to fit these numbers into a byte. (for the clock speeds we care
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// about - 8 and 16 MHz - this doesn't lose precision.)
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#define FRACT_INC ((MICROSECONDS_PER_TIMER0_OVERFLOW % 1000) >> 3)
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#define FRACT_MAX (1000 >> 3)
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#ifndef cbi
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#define cbi(sfr, bit) (_SFR_BYTE(sfr) &= ~_BV(bit))
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#endif
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#ifndef sbi
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#define sbi(sfr, bit) (_SFR_BYTE(sfr) |= _BV(bit))
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#endif
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void init()
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{
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// this needs to be called before setup() or some functions won't
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// work there
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// Enable external oscillator (16MHz)
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OSC.XOSCCTRL = OSC_FRQRANGE_12TO16_gc | OSC_XOSCSEL_XTAL_256CLK_gc ;
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OSC.CTRL |= OSC_XOSCEN_bm ;
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while( ( OSC.STATUS & OSC_XOSCRDY_bm ) == 0 )
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/* wait */ ;
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// Enable PLL (*2 = 32MHz)
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OSC.PLLCTRL = OSC_PLLSRC_XOSC_gc | 2 ;
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OSC.CTRL |= OSC_PLLEN_bm ;
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while( ( OSC.STATUS & OSC_PLLRDY_bm ) == 0 )
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/* wait */ ;
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// Switch to PLL clock
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CPU_CCP = 0xD8 ;
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CLK.CTRL = CLK_SCLKSEL_RC2M_gc ;
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CPU_CCP = 0xD8 ;
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CLK.CTRL = CLK_SCLKSEL_PLL_gc ;
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PMIC.CTRL = 7 ; // Enable all interrupt levels
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sei();
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#if defined(ADCSRA)
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// set a2d prescale factor to 128
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// 16 MHz / 128 = 125 KHz, inside the desired 50-200 KHz range.
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// XXX: this will not work properly for other clock speeds, and
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// this code should use F_CPU to determine the prescale factor.
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sbi(ADCSRA, ADPS2);
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sbi(ADCSRA, ADPS1);
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sbi(ADCSRA, ADPS0);
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// enable a2d conversions
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sbi(ADCSRA, ADEN);
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#endif
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// the bootloader connects pins 0 and 1 to the USART; disconnect them
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// here so they can be used as normal digital i/o; they will be
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// reconnected in Serial.begin()
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#if defined(UCSRB)
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UCSRB = 0;
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#elif defined(UCSR0B)
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UCSR0B = 0;
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#endif
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// Dip Switch inputs
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PORTA.DIRCLR = 0xFF ;
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PORTA.PIN0CTRL = 0x18 ;
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PORTA.PIN1CTRL = 0x18 ;
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PORTA.PIN2CTRL = 0x18 ;
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PORTA.PIN3CTRL = 0x18 ;
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PORTA.PIN4CTRL = 0x18 ;
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PORTA.PIN5CTRL = 0x18 ;
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PORTA.PIN6CTRL = 0x18 ;
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PORTA.PIN7CTRL = 0x18 ;
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}
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