mirror of
https://github.com/pascallanger/DIY-Multiprotocol-TX-Module.git
synced 2025-02-04 20:58:10 +00:00
95 lines
2.8 KiB
C
95 lines
2.8 KiB
C
/*
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This project is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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Multiprotocol is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Multiprotocol. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _IFACE_A7105_H_
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#define _IFACE_A7105_H_
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enum A7105_State {
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A7105_SLEEP = 0x80,
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A7105_IDLE = 0x90,
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A7105_STANDBY = 0xA0,
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A7105_PLL = 0xB0,
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A7105_RX = 0xC0,
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A7105_TX = 0xD0,
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A7105_RST_WRPTR = 0xE0,
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A7105_RST_RDPTR = 0xF0,
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};
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enum {
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A7105_00_MODE = 0x00,
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A7105_01_MODE_CONTROL = 0x01,
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A7105_02_CALC = 0x02,
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A7105_03_FIFOI = 0x03,
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A7105_04_FIFOII = 0x04,
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A7105_05_FIFO_DATA = 0x05,
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A7105_06_ID_DATA = 0x06,
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A7105_07_RC_OSC_I = 0x07,
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A7105_08_RC_OSC_II = 0x08,
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A7105_09_RC_OSC_III = 0x09,
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A7105_0A_CK0_PIN = 0x0A,
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A7105_0B_GPIO1_PIN1 = 0x0B,
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A7105_0C_GPIO2_PIN_II = 0x0C,
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A7105_0D_CLOCK = 0x0D,
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A7105_0E_DATA_RATE = 0x0E,
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A7105_0F_PLL_I = 0x0F,
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A7105_10_PLL_II = 0x10,
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A7105_11_PLL_III = 0x11,
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A7105_12_PLL_IV = 0x12,
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A7105_13_PLL_V = 0x13,
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A7105_14_TX_I = 0x14,
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A7105_15_TX_II = 0x15,
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A7105_16_DELAY_I = 0x16,
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A7105_17_DELAY_II = 0x17,
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A7105_18_RX = 0x18,
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A7105_19_RX_GAIN_I = 0x19,
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A7105_1A_RX_GAIN_II = 0x1A,
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A7105_1B_RX_GAIN_III = 0x1B,
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A7105_1C_RX_GAIN_IV = 0x1C,
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A7105_1D_RSSI_THOLD = 0x1D,
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A7105_1E_ADC = 0x1E,
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A7105_1F_CODE_I = 0x1F,
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A7105_20_CODE_II = 0x20,
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A7105_21_CODE_III = 0x21,
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A7105_22_IF_CALIB_I = 0x22,
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A7105_23_IF_CALIB_II = 0x23,
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A7105_24_VCO_CURCAL = 0x24,
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A7105_25_VCO_SBCAL_I = 0x25,
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A7105_26_VCO_SBCAL_II = 0x26,
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A7105_27_BATTERY_DET = 0x27,
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A7105_28_TX_TEST = 0x28,
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A7105_29_RX_DEM_TEST_I = 0x29,
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A7105_2A_RX_DEM_TEST_II = 0x2A,
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A7105_2B_CPC = 0x2B,
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A7105_2C_XTAL_TEST = 0x2C,
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A7105_2D_PLL_TEST = 0x2D,
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A7105_2E_VCO_TEST_I = 0x2E,
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A7105_2F_VCO_TEST_II = 0x2F,
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A7105_30_IFAT = 0x30,
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A7105_31_RSCALE = 0x31,
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A7105_32_FILTER_TEST = 0x32,
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};
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#define A7105_0F_CHANNEL A7105_0F_PLL_I
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enum A7105_MASK {
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A7105_MASK_FBCF = 1 << 4,
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A7105_MASK_VBCF = 1 << 3,
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};
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enum {
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INIT_FLYSKY,
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INIT_HUBSAN
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};
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#endif |