mirror of
https://github.com/pascallanger/DIY-Multiprotocol-TX-Module.git
synced 2025-02-04 17:58:13 +00:00
277 lines
8.4 KiB
C++
277 lines
8.4 KiB
C++
/*
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This project is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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Multiprotocol is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Multiprotocol. If not, see <http://www.gnu.org/licenses/>.
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*/
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#if defined(NCC1701_NRF24L01_INO)
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#include "iface_nrf24l01.h"
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#define NCC_WRITE_WAIT 2000
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#define NCC_PACKET_INTERVAL 10333
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#define NCC_TX_PACKET_LEN 16
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#define NCC_RX_PACKET_LEN 13
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enum {
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NCC_BIND_TX1=0,
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NCC_BIND_RX1,
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NCC_BIND_TX2,
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NCC_BIND_RX2,
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NCC_TX3,
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NCC_RX3,
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};
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static void __attribute__((unused)) NCC_RF_init()
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{
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NRF24L01_Initialize();
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NRF24L01_SetTxRxMode(TX_EN);
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NRF24L01_WriteReg(NRF24L01_03_SETUP_AW, 0x03); // 5-byte RX/TX address
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NRF24L01_WriteRegisterMulti(NRF24L01_0A_RX_ADDR_P0, (uint8_t*)"\xE7\xE7\xC7\xD7\x67",5);
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NRF24L01_WriteRegisterMulti(NRF24L01_10_TX_ADDR, (uint8_t*)"\xE7\xE7\xC7\xD7\x67",5);
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NRF24L01_FlushTx();
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NRF24L01_FlushRx();
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NRF24L01_WriteReg(NRF24L01_07_STATUS, 0x70); // Clear data ready, data sent, and retransmit
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NRF24L01_WriteReg(NRF24L01_01_EN_AA, 0x00); // No Auto Acknowledgment on all data pipes
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NRF24L01_WriteReg(NRF24L01_02_EN_RXADDR, 0x01); // Enable data pipe 0 only
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NRF24L01_WriteReg(NRF24L01_11_RX_PW_P0, NCC_RX_PACKET_LEN); // Enable rx pipe 0
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NRF24L01_SetBitrate(NRF24L01_BR_250K); // NRF24L01_BR_1M, NRF24L01_BR_2M, NRF24L01_BR_250K
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NRF24L01_SetPower();
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NRF24L01_FlushRx();
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NRF24L01_WriteReg(NRF24L01_00_CONFIG, (0 << NRF24L01_00_EN_CRC) // switch to TX mode and disable CRC
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| (1 << NRF24L01_00_CRCO)
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| (1 << NRF24L01_00_PWR_UP)
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| (0 << NRF24L01_00_PRIM_RX));
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}
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const uint8_t NCC_xor[]={0x80, 0x44, 0x64, 0x75, 0x6C, 0x71, 0x2A, 0x36, 0x7C, 0xF1, 0x6E, 0x52, 0x09, 0x9D};
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static void __attribute__((unused)) NCC_Crypt_Packet()
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{
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crc=0;
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for(uint8_t i=0; i< NCC_TX_PACKET_LEN-2; i++)
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{
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packet[i]^=NCC_xor[i];
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crc16_update(packet[i], 8);
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}
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crc^=0x60DE;
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packet[NCC_TX_PACKET_LEN-2]=crc>>8;
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packet[NCC_TX_PACKET_LEN-1]=crc;
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}
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static boolean __attribute__((unused)) NCC_Decrypt_Packet()
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{
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crc=0;
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debug("RX: ");
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for(uint8_t i=0; i< NCC_RX_PACKET_LEN-2; i++)
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{
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crc16_update( packet[i], 8);
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packet[i]^=NCC_xor[i];
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debug("%02X ",packet[i]);
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}
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crc^=0xA950;
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if( (crc>>8)==packet[NCC_RX_PACKET_LEN-2] && (crc&0xFF)==packet[NCC_RX_PACKET_LEN-1] )
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{// CRC match
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debugln("OK");
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return true;
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}
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debugln("NOK");
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return false;
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}
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static void __attribute__((unused)) NCC_Write_Packet()
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{
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packet[0]=0xAA;
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packet[1]=rx_tx_addr[0];
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packet[2]=rx_tx_addr[1];
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packet[3]=rx_id[0];
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packet[4]=rx_id[1];
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packet[5]=convert_channel_8b(THROTTLE)>>2; // 00-3D
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packet[6]=convert_channel_8b(ELEVATOR); // original: 61-80-9F but works with 00-80-FF
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packet[7]=convert_channel_8b(AILERON ); // original: 61-80-9F but works with 00-80-FF
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packet[8]=convert_channel_8b(RUDDER ); // original: 61-80-9F but works with 00-80-FF
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packet[9]=rx_id[2];
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packet[10]=rx_id[3];
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packet[11]=rx_id[4];
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packet[12]=GET_FLAG(CH5_SW, 0x02); // Warp:0x00 -> 0x02
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packet[13]=packet[5]+packet[6]+packet[7]+packet[8]+packet[12];
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if(phase==NCC_BIND_TX1)
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{
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packet[0]=0xBB;
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packet[5]=0x01;
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packet[6]=rx_tx_addr[2];
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memset((void *)(packet+7),0x55,7);
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hopping_frequency_no^=1;
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}
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else
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{
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hopping_frequency_no++;
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if(hopping_frequency_no>2) hopping_frequency_no=0;
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}
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// change frequency
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NRF24L01_WriteReg(NRF24L01_05_RF_CH, hopping_frequency[hopping_frequency_no]);
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// switch to TX mode and disable CRC
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NRF24L01_SetTxRxMode(TXRX_OFF);
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NRF24L01_SetTxRxMode(TX_EN);
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NRF24L01_WriteReg(NRF24L01_00_CONFIG, (0 << NRF24L01_00_EN_CRC)
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| (1 << NRF24L01_00_CRCO)
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| (1 << NRF24L01_00_PWR_UP)
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| (0 << NRF24L01_00_PRIM_RX));
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// clear packet status bits and TX FIFO
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NRF24L01_WriteReg(NRF24L01_07_STATUS, 0x70);
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NRF24L01_FlushTx();
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// send packet
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NCC_Crypt_Packet();
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NRF24L01_WritePayload(packet,NCC_TX_PACKET_LEN);
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NRF24L01_SetPower();
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}
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uint16_t NCC_callback()
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{
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switch(phase)
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{
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case NCC_BIND_TX1:
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if( NRF24L01_ReadReg(NRF24L01_07_STATUS) & _BV(NRF24L01_07_RX_DR))
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{ // RX fifo data ready
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NRF24L01_ReadPayload(packet, NCC_RX_PACKET_LEN);
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if(NCC_Decrypt_Packet() && packet[1]==rx_tx_addr[0] && packet[2]==rx_tx_addr[1])
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{
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rx_id[0]=packet[3];
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rx_id[1]=packet[4];
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NRF24L01_WriteReg(NRF24L01_07_STATUS, 0x70); // Clear data ready, data sent, and retransmit
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phase=NCC_BIND_TX2;
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return NCC_PACKET_INTERVAL;
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}
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}
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NCC_Write_Packet();
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phase = NCC_BIND_RX1;
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return NCC_WRITE_WAIT;
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case NCC_BIND_RX1:
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// switch to RX mode and disable CRC
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NRF24L01_SetTxRxMode(TXRX_OFF);
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NRF24L01_SetTxRxMode(RX_EN);
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NRF24L01_WriteReg(NRF24L01_00_CONFIG, (0 << NRF24L01_00_EN_CRC)
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| (1 << NRF24L01_00_CRCO)
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| (1 << NRF24L01_00_PWR_UP)
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| (1 << NRF24L01_00_PRIM_RX));
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NRF24L01_FlushRx();
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phase = NCC_BIND_TX1;
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return NCC_PACKET_INTERVAL - NCC_WRITE_WAIT;
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case NCC_BIND_TX2:
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if( NRF24L01_ReadReg(NRF24L01_07_STATUS) & _BV(NRF24L01_07_RX_DR))
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{ // RX fifo data ready
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NRF24L01_ReadPayload(packet, NCC_RX_PACKET_LEN);
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if(NCC_Decrypt_Packet() && packet[1]==rx_tx_addr[0] && packet[2]==rx_tx_addr[1] && packet[3]==rx_id[0] && packet[4]==rx_id[1])
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{
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rx_id[2]=packet[8];
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rx_id[3]=packet[9];
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rx_id[4]=packet[10];
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NRF24L01_WriteReg(NRF24L01_07_STATUS, 0x70); // Clear data ready, data sent, and retransmit
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BIND_DONE;
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phase=NCC_TX3;
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return NCC_PACKET_INTERVAL;
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}
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}
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NCC_Write_Packet();
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phase = NCC_BIND_RX2;
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return NCC_WRITE_WAIT;
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case NCC_BIND_RX2:
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// switch to RX mode and disable CRC
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NRF24L01_SetTxRxMode(TXRX_OFF);
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NRF24L01_SetTxRxMode(RX_EN);
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NRF24L01_WriteReg(NRF24L01_00_CONFIG, (0 << NRF24L01_00_EN_CRC)
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| (1 << NRF24L01_00_CRCO)
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| (1 << NRF24L01_00_PWR_UP)
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| (1 << NRF24L01_00_PRIM_RX));
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NRF24L01_FlushRx();
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phase = NCC_BIND_TX2;
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return NCC_PACKET_INTERVAL - NCC_WRITE_WAIT;
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case NCC_TX3:
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#ifdef MULTI_SYNC
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telemetry_set_input_sync(NCC_PACKET_INTERVAL);
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#endif
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if( NRF24L01_ReadReg(NRF24L01_07_STATUS) & _BV(NRF24L01_07_RX_DR))
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{ // RX fifo data ready
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NRF24L01_ReadPayload(packet, NCC_RX_PACKET_LEN);
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if(NCC_Decrypt_Packet() && packet[1]==rx_tx_addr[0] && packet[2]==rx_tx_addr[1] && packet[3]==rx_id[0] && packet[4]==rx_id[1])
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{
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//Telemetry
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//packet[5] and packet[7] roll angle
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//packet[6] crash detect: 0x00 no crash, 0x02 crash
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#ifdef NCC1701_HUB_TELEMETRY
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v_lipo1 = packet[6]?0xFF:0x00; // Crash indication
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v_lipo2 = 0x00;
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RX_RSSI = 0x7F; // Dummy RSSI
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TX_RSSI = 0x7F; // Dummy RSSI
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telemetry_link=1;
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#endif
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}
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}
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NCC_Write_Packet();
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phase = NCC_RX3;
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return NCC_WRITE_WAIT;
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case NCC_RX3:
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// switch to RX mode and disable CRC
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NRF24L01_SetTxRxMode(TXRX_OFF);
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NRF24L01_SetTxRxMode(RX_EN);
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NRF24L01_WriteReg(NRF24L01_00_CONFIG, (0 << NRF24L01_00_EN_CRC)
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| (1 << NRF24L01_00_CRCO)
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| (1 << NRF24L01_00_PWR_UP)
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| (1 << NRF24L01_00_PRIM_RX));
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NRF24L01_FlushRx();
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phase = NCC_TX3;
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return NCC_PACKET_INTERVAL - NCC_WRITE_WAIT;
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}
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return 0;
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}
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const uint8_t PROGMEM NCC_TX_DATA[][6]= {
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{ 0x6D, 0x97, 0x04, 0x48, 0x43, 0x26 },
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{ 0x35, 0x4B, 0x80, 0x44, 0x4C, 0x0B },
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{ 0x50, 0xE2, 0x32, 0x2D, 0x4B, 0x0A },
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{ 0xBF, 0x34, 0xF3, 0x45, 0x4D, 0x0D },
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{ 0xDD, 0x7D, 0x5A, 0x46, 0x28, 0x23 },
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{ 0xED, 0x19, 0x06, 0x2C, 0x4A, 0x09 },
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{ 0xE9, 0xA8, 0x91, 0x2B, 0x49, 0x07 },
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{ 0x66, 0x17, 0x7D, 0x48, 0x43, 0x26 },
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{ 0xC2, 0x93, 0x55, 0x44, 0x4C, 0x0B },
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};
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void NCC_init(void)
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{
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BIND_IN_PROGRESS; // autobind protocol
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// Load TX data
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uint8_t rand=rx_tx_addr[3]%9;
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for(uint8_t i=0; i<3; i++)
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{
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rx_tx_addr[i]=pgm_read_byte_near(&NCC_TX_DATA[rand][i]);
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hopping_frequency[i]=pgm_read_byte_near(&NCC_TX_DATA[rand][i+3]);
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}
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// RX data is acquired during bind
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rx_id[0]=0x00;
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rx_id[1]=0x00;
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rx_id[2]=0x20;
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rx_id[3]=0x20;
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rx_id[4]=0x20;
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hopping_frequency[4]=0x08; // bind channel 1
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hopping_frequency[5]=0x2A; // bind channel 2
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hopping_frequency_no=4; // start with bind
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NCC_RF_init();
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phase=NCC_BIND_TX1;
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}
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#endif
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