mirror of
https://github.com/pascallanger/DIY-Multiprotocol-TX-Module.git
synced 2025-10-29 18:11:05 +00:00
c02f273d57
This new feature is available: - in serial mode and when binding from the GUI. As soon as the Bind window is closed = serial bind bit was set and cleared, the current bind operation will be terminated. - if the bind was initiated from the Bind on channel feature (bind channel goes high) then as soon as the bind channel goes low the current bind operation will be terminated. Tested on ersky9x which does open a bind window, not sure about OpenTX... Some protocols (Hubsan, Assan, FY326, Shenqi...) which are waiting for model/RX to reply will stay in bind mode.
151 lines
8.7 KiB
C
151 lines
8.7 KiB
C
/*
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This project is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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Multiprotocol is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Multiprotocol. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _IFACE_CC2500_H_
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#define _IFACE_CC2500_H_
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enum {
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CC2500_00_IOCFG2 = 0x00, // GDO2 output pin configuration
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CC2500_01_IOCFG1 = 0x01, // GDO1 output pin configuration
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CC2500_02_IOCFG0 = 0x02, // GDO0 output pin configuration
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CC2500_03_FIFOTHR = 0x03, // RX FIFO and TX FIFO thresholds
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CC2500_04_SYNC1 = 0x04, // Sync word, high byte
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CC2500_05_SYNC0 = 0x05, // Sync word, low byte
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CC2500_06_PKTLEN = 0x06, // Packet length
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CC2500_07_PKTCTRL1 = 0x07, // Packet automation control
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CC2500_08_PKTCTRL0 = 0x08, // Packet automation control
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CC2500_09_ADDR = 0x09, // Device address
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CC2500_0A_CHANNR = 0x0A, // Channel number
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CC2500_0B_FSCTRL1 = 0x0B, // Frequency synthesizer control
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CC2500_0C_FSCTRL0 = 0x0C, // Frequency synthesizer control
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CC2500_0D_FREQ2 = 0x0D, // Frequency control word, high byte
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CC2500_0E_FREQ1 = 0x0E, // Frequency control word, middle byte
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CC2500_0F_FREQ0 = 0x0F, // Frequency control word, low byte
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CC2500_10_MDMCFG4 = 0x10, // Modem configuration
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CC2500_11_MDMCFG3 = 0x11, // Modem configuration
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CC2500_12_MDMCFG2 = 0x12, // Modem configuration
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CC2500_13_MDMCFG1 = 0x13, // Modem configuration
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CC2500_14_MDMCFG0 = 0x14, // Modem configuration
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CC2500_15_DEVIATN = 0x15, // Modem deviation setting
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CC2500_16_MCSM2 = 0x16, // Main Radio Cntrl State Machine config
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CC2500_17_MCSM1 = 0x17, // Main Radio Cntrl State Machine config
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CC2500_18_MCSM0 = 0x18, // Main Radio Cntrl State Machine config
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CC2500_19_FOCCFG = 0x19, // Frequency Offset Compensation config
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CC2500_1A_BSCFG = 0x1A, // Bit Synchronization configuration
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CC2500_1B_AGCCTRL2 = 0x1B, // AGC control
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CC2500_1C_AGCCTRL1 = 0x1C, // AGC control
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CC2500_1D_AGCCTRL0 = 0x1D, // AGC control
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CC2500_1E_WOREVT1 = 0x1E, // High byte Event 0 timeout
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CC2500_1F_WOREVT0 = 0x1F, // Low byte Event 0 timeout
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CC2500_20_WORCTRL = 0x20, // Wake On Radio control
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CC2500_21_FREND1 = 0x21, // Front end RX configuration
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CC2500_22_FREND0 = 0x22, // Front end TX configuration
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CC2500_23_FSCAL3 = 0x23, // Frequency synthesizer calibration
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CC2500_24_FSCAL2 = 0x24, // Frequency synthesizer calibration
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CC2500_25_FSCAL1 = 0x25, // Frequency synthesizer calibration
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CC2500_26_FSCAL0 = 0x26, // Frequency synthesizer calibration
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CC2500_27_RCCTRL1 = 0x27, // RC oscillator configuration
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CC2500_28_RCCTRL0 = 0x28, // RC oscillator configuration
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CC2500_29_FSTEST = 0x29, // Frequency synthesizer cal control
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CC2500_2A_PTEST = 0x2A, // Production test
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CC2500_2B_AGCTEST = 0x2B, // AGC test
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CC2500_2C_TEST2 = 0x2C, // Various test settings
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CC2500_2D_TEST1 = 0x2D, // Various test settings
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CC2500_2E_TEST0 = 0x2E, // Various test settings
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// Status registers
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CC2500_30_PARTNUM = 0x30, // Part number
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CC2500_31_VERSION = 0x31, // Current version number
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CC2500_32_FREQEST = 0x32, // Frequency offset estimate
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CC2500_33_LQI = 0x33, // Demodulator estimate for link quality
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CC2500_34_RSSI = 0x34, // Received signal strength indication
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CC2500_35_MARCSTATE = 0x35, // Control state machine state
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CC2500_36_WORTIME1 = 0x36, // High byte of WOR timer
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CC2500_37_WORTIME0 = 0x37, // Low byte of WOR timer
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CC2500_38_PKTSTATUS = 0x38, // Current GDOx status and packet status
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CC2500_39_VCO_VC_DAC = 0x39, // Current setting from PLL cal module
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CC2500_3A_TXBYTES = 0x3A, // Underflow and # of bytes in TXFIFO
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CC2500_3B_RXBYTES = 0x3B, // Overflow and # of bytes in RXFIFO
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// Multi byte memory locations
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CC2500_3E_PATABLE = 0x3E,
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CC2500_3F_TXFIFO = 0x3F,
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CC2500_3F_RXFIFO = 0x3F,
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};
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// Definitions for burst/single access to registers
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#define CC2500_WRITE_SINGLE 0x00
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#define CC2500_WRITE_BURST 0x40
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#define CC2500_READ_SINGLE 0x80
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#define CC2500_READ_BURST 0xC0
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// Strobe commands
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#define CC2500_SRES 0x30 // Reset chip.
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#define CC2500_SFSTXON 0x31 // Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1).
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// If in RX/TX: Go to a wait state where only the synthesizer is
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// running (for quick RX / TX turnaround).
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#define CC2500_SXOFF 0x32 // Turn off crystal oscillator.
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#define CC2500_SCAL 0x33 // Calibrate frequency synthesizer and turn it off
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// (enables quick start).
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#define CC2500_SRX 0x34 // Enable RX. Perform calibration first if coming from IDLE and
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// MCSM0.FS_AUTOCAL=1.
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#define CC2500_STX 0x35 // In IDLE state: Enable TX. Perform calibration first if
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// MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled:
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// Only go to TX if channel is clear.
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#define CC2500_SIDLE 0x36 // Exit RX / TX, turn off frequency synthesizer and exit
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// Wake-On-Radio mode if applicable.
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#define CC2500_SAFC 0x37 // Perform AFC adjustment of the frequency synthesizer
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#define CC2500_SWOR 0x38 // Start automatic RX polling sequence (Wake-on-Radio)
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#define CC2500_SPWD 0x39 // Enter power down mode when CSn goes high.
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#define CC2500_SFRX 0x3A // Flush the RX FIFO buffer.
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#define CC2500_SFTX 0x3B // Flush the TX FIFO buffer.
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#define CC2500_SWORRST 0x3C // Reset real time clock.
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#define CC2500_SNOP 0x3D // No operation. May be used to pad strobe commands to two
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// bytes for simpler software.
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//----------------------------------------------------------------------------------
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// Chip Status Byte
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//----------------------------------------------------------------------------------
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// Bit fields in the chip status byte
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#define CC2500_STATUS_CHIP_RDYn_BM 0x80
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#define CC2500_STATUS_STATE_BM 0x70
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#define CC2500_STATUS_FIFO_BYTES_AVAILABLE_BM 0x0F
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// Chip states
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#define CC2500_STATE_IDLE 0x00
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#define CC2500_STATE_RX 0x10
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#define CC2500_STATE_TX 0x20
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#define CC2500_STATE_FSTXON 0x30
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#define CC2500_STATE_CALIBRATE 0x40
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#define CC2500_STATE_SETTLING 0x50
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#define CC2500_STATE_RX_OVERFLOW 0x60
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#define CC2500_STATE_TX_UNDERFLOW 0x70
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//----------------------------------------------------------------------------------
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// Other register bit fields
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//----------------------------------------------------------------------------------
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#define CC2500_LQI_CRC_OK_BM 0x80
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#define CC2500_LQI_EST_BM 0x7F
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//void CC2500_WriteReg(u8 addr, u8 data);
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//u8 CC2500_ReadReg(u8 addr);
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//void CC2500_Reset();
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//void CC2500_Strobe(u8 cmd);
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//void CC2500_WriteData(u8 *packet, u8 length);
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//void CC2500_ReadData(u8 *dpbuffer, int len);
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//void CC2500_SetTxRxMode(enum TXRX_State);
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#endif
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