mirror of
https://github.com/pascallanger/DIY-Multiprotocol-TX-Module.git
synced 2025-02-04 18:38:13 +00:00
STM32 board & DSM fixes
Loads of changes: STM32 board introduction: NOT TESTED XMEGA renamed to ORANGE_TX to be more explicit DSM: added reset if cyrf freezed Validate: added a validate file to verify the different compilation options
This commit is contained in:
pascallanger
parent
cde8deaf4b
commit
f557609e9e
@ -15,6 +15,7 @@
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/********************/
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/** A7105 routines **/
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/********************/
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#ifdef A7105_INSTALLED
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#include "iface_a7105.h"
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void A7105_WriteData(uint8_t len, uint8_t channel)
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@ -30,13 +31,14 @@ void A7105_WriteData(uint8_t len, uint8_t channel)
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A7105_Strobe(A7105_TX);
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}
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void A7105_ReadData() {
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void A7105_ReadData()
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{
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uint8_t i;
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A7105_Strobe(0xF0); //A7105_RST_RDPTR
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A7105_CSN_off;
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SPI_Write(0x45);
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for (i=0;i<16;i++)
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packet[i]=SPI_SDIO_Read();
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packet[i]=SPI_SDI_Read();
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A7105_CSN_on;
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}
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@ -48,11 +50,12 @@ void A7105_WriteReg(uint8_t address, uint8_t data) {
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A7105_CSN_on;
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}
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uint8_t A7105_ReadReg(uint8_t address) {
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uint8_t A7105_ReadReg(uint8_t address)
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{
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uint8_t result;
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A7105_CSN_off;
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SPI_Write(address |=0x40); //bit 6 =1 for reading
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result = SPI_SDIO_Read();
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result = SPI_SDI_Read();
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A7105_CSN_on;
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return(result);
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}
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@ -163,21 +166,21 @@ const uint8_t PROGMEM FLYSKY_A7105_regs[] = {
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#define ID_PLUS 0xAA201041
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void A7105_Init(uint8_t protocol)
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{
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void *A7105_Regs;
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uint8_t *A7105_Regs;
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if(protocol==INIT_FLYSKY)
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{
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A7105_WriteID(0x5475c52A);//0x2Ac57554
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A7105_Regs=(void *)FLYSKY_A7105_regs;
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A7105_Regs=(uint8_t*)FLYSKY_A7105_regs;
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}
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else
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{
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A7105_WriteID(ID_NORMAL);
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A7105_Regs=(void *)HUBSAN_A7105_regs;
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A7105_Regs=(uint8_t*)HUBSAN_A7105_regs;
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}
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for (uint8_t i = 0; i < 0x33; i++){
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if( pgm_read_byte_near((uint16_t)(A7105_Regs)+i) != 0xFF)
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A7105_WriteReg(i, pgm_read_byte_near((uint16_t)(A7105_Regs)+i));
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if( pgm_read_byte_near(&A7105_Regs[i]) != 0xFF)
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A7105_WriteReg(i, pgm_read_byte_near(&A7105_Regs[i]));
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}
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A7105_Strobe(A7105_STANDBY);
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@ -216,3 +219,4 @@ void A7105_Init(uint8_t protocol)
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A7105_Strobe(A7105_STANDBY);
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}
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#endif
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@ -12,6 +12,8 @@
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You should have received a copy of the GNU General Public License
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along with Multiprotocol. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef STM32_BOARD
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/************************************/
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/************************************/
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/** Arduino replacement routines **/
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/************************************/
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@ -106,7 +108,7 @@ void delayMicroseconds(unsigned int us)
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return;
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us <<= 2; // * 4
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us -= 2; // - 2
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#ifdef XMEGA
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#ifdef ORANGE_TX
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__asm__ __volatile__ (
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"1: sbiw %0,1" "\n\t" // 2 cycles
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"nop \n"
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@ -123,11 +125,12 @@ void delayMicroseconds(unsigned int us)
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#endif
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}
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#ifndef XMEGA
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#ifndef ORANGE_TX
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void init()
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{
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// this needs to be called before setup() or some functions won't work there
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sei();
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}
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#endif //XMEGA
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#endif //ORANGE_TX
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#endif //STM32_BOARD
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@ -1,3 +1,4 @@
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/*
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This project is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@ -17,6 +18,7 @@
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//CC2500 SPI routines
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//-------------------------------
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//-------------------------------
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#ifdef CC2500_INSTALLED
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#include "iface_cc2500.h"
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//----------------------------
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@ -152,4 +154,4 @@ void CC2500_SetPower()
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prev_power=power;
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}
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}
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#endif
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@ -12,9 +12,9 @@
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You should have received a copy of the GNU General Public License
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along with Multiprotocol. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifdef CYRF6936_INSTALLED
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#include "iface_cyrf6936.h"
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void CYRF_WriteRegister(uint8_t address, uint8_t data)
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{
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CYRF_CSN_off;
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@ -182,11 +182,6 @@ void CYRF_WritePreamble(uint32_t preamble)
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/*
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*
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*/
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static void CYRF_StartReceive()
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{
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CYRF_WriteRegister(CYRF_05_RX_CTRL,0x87);
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}
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/*static void CYRF_ReadDataPacket(uint8_t dpbuffer[])
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{
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CYRF_ReadRegisterMulti(CYRF_21_RX_BUFFER, dpbuffer, 0x10);
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@ -243,10 +238,14 @@ void CYRF_FindBestChannels(uint8_t *channels, uint8_t len, uint8_t minspace, uin
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for(i = 0; i < NUM_FREQ; i++)
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{
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CYRF_ConfigRFChannel(i);
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CYRF_ReadRegister(CYRF_13_RSSI);
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CYRF_StartReceive();
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delayMicroseconds(10);
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rssi[i] = CYRF_ReadRegister(CYRF_13_RSSI);
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delayMicroseconds(270); //slow channel require 270usec for synthesizer to settle
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if( !(CYRF_ReadRegister(CYRF_05_RX_CTRL) & 0x80)) {
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CYRF_WriteRegister(CYRF_05_RX_CTRL, 0x80); //Prepare to receive
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delayMicroseconds(15);
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CYRF_ReadRegister(CYRF_13_RSSI); //dummy read
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delayMicroseconds(15); //The conversion can occur as often as once every 12us
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}
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rssi[i] = CYRF_ReadRegister(CYRF_13_RSSI)&0x1F;
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}
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for (i = 0; i < len; i++)
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@ -262,7 +261,9 @@ void CYRF_FindBestChannels(uint8_t *channels, uint8_t len, uint8_t minspace, uin
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rssi[j] = 0xff;
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}
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}
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CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x20); // Abort RX operation
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CYRF_SetTxRxMode(TX_EN);
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CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x20); // Clear abort RX
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}
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#if defined(DEVO_CYRF6936_INO) || defined(J6PRO_CYRF6936_INO)
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@ -297,4 +298,5 @@ static void __attribute__((unused)) CYRF_PROGMEM_ConfigSOPCode(const uint8_t *da
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for(uint8_t i=0;i<8;i++)
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code[i]=pgm_read_byte_near(&data[i]);
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CYRF_ConfigSOPCode(code);
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}
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}
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#endif
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@ -15,6 +15,7 @@
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/************************/
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/** Convert routines **/
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/************************/
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#ifndef STM32_BOARD
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int16_t map( int16_t x, int16_t in_min, int16_t in_max, int16_t out_min, int16_t out_max)
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{
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// return (x - in_min) * (out_max - out_min) / (in_max - in_min) + out_min;
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@ -25,6 +26,7 @@ int16_t map( int16_t x, int16_t in_min, int16_t in_max, int16_t out_min, int16_t
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x = y / (in_max - in_min) ;
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return x + out_min ;
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}
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#endif
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// Channel value is converted to 8bit values full scale
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uint8_t convert_channel_8b(uint8_t num)
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@ -135,8 +135,7 @@ static uint8_t __attribute__((unused)) get_pn_row(uint8_t channel)
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}
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const uint8_t PROGMEM init_vals[][2] = {
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{CYRF_02_TX_CTRL, 0x03}, // TX interrupt complete and error enabled
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//0x00 in deviation but needed to know when transmit is over
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{CYRF_02_TX_CTRL, 0x00}, // All TX interrupt disabled
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{CYRF_05_RX_CTRL, 0x00}, // All RX interrupt disabled
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{CYRF_28_CLK_EN, 0x02}, // Force receive clock enable
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{CYRF_32_AUTO_CAL_TIME, 0x3c}, // Default init value
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@ -369,13 +368,13 @@ static uint8_t __attribute__((unused)) DSM_Check_RX_packet()
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uint16_t ReadDsm()
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{
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#define DSM_CH1_CH2_DELAY 4010 // Time between write of channel 1 and channel 2
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#define DSM_WRITE_DELAY 1550 // Time after write to verify write complete
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#define DSM_WRITE_DELAY 1950 // Time after write to verify write complete
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#define DSM_READ_DELAY 600 // Time before write to check read phase, and switch channels. Was 400 but 600 seems what the 328p needs to read a packet
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uint16_t start;
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#if defined DSM_TELEMETRY
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uint8_t rx_phase;
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uint8_t len;
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#endif
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uint8_t start;
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switch(phase)
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{
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@ -451,19 +450,28 @@ uint16_t ReadDsm()
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return DSM_WRITE_DELAY;
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case DSM_CH1_CHECK_A:
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case DSM_CH1_CHECK_B:
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start=micros();
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while ((uint16_t)micros()-start < 500) // Wait max 500µs
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if(CYRF_ReadRegister(CYRF_04_TX_IRQ_STATUS) & 0x02)
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break;
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set_sop_data_crc();
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phase++; // change from CH1_CHECK to CH2_WRITE
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return DSM_CH1_CH2_DELAY - DSM_WRITE_DELAY;
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case DSM_CH2_CHECK_A:
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case DSM_CH2_CHECK_B:
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start=micros();
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while ((uint16_t)micros()-start < 500) // Wait max 500µs
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while ((uint8_t)micros()-start < 100) // Wait max 100µs, max I've seen is 50µs
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if(CYRF_ReadRegister(CYRF_04_TX_IRQ_STATUS) & 0x02)
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break;
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if(phase==DSM_CH1_CHECK_A || phase==DSM_CH1_CHECK_B)
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{
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#if defined DSM_TELEMETRY
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// reset cyrf6936 if freezed after switching from TX to RX
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if (((CYRF_ReadRegister(CYRF_04_TX_IRQ_STATUS) & 0x22) == 0x20) || (CYRF_ReadRegister(CYRF_02_TX_CTRL) & 0x80))
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{
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CYRF_Reset();
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cyrf_config();
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cyrf_configdata();
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CYRF_SetTxRxMode(TX_EN);
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}
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#endif
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set_sop_data_crc();
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phase++; // change from CH1_CHECK to CH2_WRITE
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return DSM_CH1_CH2_DELAY - DSM_WRITE_DELAY;
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}
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if (phase == DSM_CH2_CHECK_A)
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CYRF_SetPower(0x28); //Keep transmit power in sync
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#if defined DSM_TELEMETRY
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@ -63,7 +63,7 @@ static void __attribute__((unused)) DEVO_add_pkt_suffix()
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BIND_SET_PULLUP; // set pullup
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if(IS_BIND_BUTTON_on)
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{
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eeprom_write_byte((uint8_t*)(30+mode_select),0x01); // Set fixed id mode for the current model
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eeprom_write_byte((EE_ADDR)(30+mode_select),0x01); // Set fixed id mode for the current model
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option=1;
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}
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BIND_SET_OUTPUT;
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@ -274,13 +274,14 @@ uint16_t ReadFrSkyX()
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return 3000;
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case FRSKY_DATA4:
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len = CC2500_ReadReg(CC2500_3B_RXBYTES | CC2500_READ_BURST) & 0x7F;
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if (len && (len<MAX_PKT))
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if (len && (len<=(0x0E + 3))) //Telemetry frame is 17
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{
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counter=0;
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CC2500_ReadData(pkt, len);
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#if defined TELEMETRY
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frsky_check_telemetry(pkt,len); //check if valid telemetry packets
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//parse telemetry packets here
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//The same telemetry function used by FrSky(D8).
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frsky_check_telemetry(pkt,len); //check if valid telemetry packets
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//parse telemetry packets here
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//The same telemetry function used by FrSky(D8).
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#endif
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}
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else
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@ -292,7 +293,9 @@ uint16_t ReadFrSkyX()
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seq_last_sent = 0;
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seq_last_rcvd = 8;
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counter=0;
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telemetry_lost=1;
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}
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CC2500_Strobe(CC2500_SFRX); //flush the RXFIFO
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}
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state = FRSKY_DATA1;
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return 300;
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@ -58,7 +58,7 @@ const uint8_t h7_mys_byte[] = {
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0x05, 0x15, 0x06, 0x16, 0x07, 0x17, 0x00, 0x10
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};
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static const u8 ls_mys_byte[] = {
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static const uint8_t ls_mys_byte[] = {
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0x05, 0x15, 0x25, 0x06, 0x16, 0x26,
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0x07, 0x17, 0x27, 0x00, 0x10, 0x20,
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0x01, 0x11, 0x21, 0x02, 0x12, 0x22,
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@ -1,7 +1,7 @@
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#define ARDUINO_AVR_PRO 1
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//#define __AVR_ATmega328P__ 1
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#define XMEGA 1
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#define ORANGE_TX 1
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// For BLUE module use:
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//#define DSM_BLUE
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@ -13,16 +13,6 @@
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along with Multiprotocol. If not, see <http://www.gnu.org/licenses/>.
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*/
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// Check selected board type
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#ifndef XMEGA
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#if not defined(ARDUINO_AVR_PRO) && not defined(ARDUINO_AVR_MINI) && not defined(ARDUINO_AVR_NANO)
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#error You must select the board type "Arduino Pro or Pro Mini" or "Arduino Mini"
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#endif
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#if F_CPU != 16000000L || not defined(__AVR_ATmega328P__)
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#error You must select the processor type "ATmega328(5V, 16MHz)"
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#endif
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#endif
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//******************
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// Protocols
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//******************
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@ -159,27 +149,6 @@ struct PPM_Parameters
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// Macros
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#define NOP() __asm__ __volatile__("nop")
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//*******************
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//*** Timer ***
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//*******************
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#ifdef XMEGA
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#define TIFR1 TCC1.INTFLAGS
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#define OCF1A_bm TC1_CCAIF_bm
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#define OCR1A TCC1.CCA
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#define TCNT1 TCC1.CNT
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#define UDR0 USARTC0.DATA
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#define OCF1B_bm TC1_CCBIF_bm
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#define OCR1B TCC1.CCB
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#define TIMSK1 TCC1.INTCTRLB
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#define SET_TIMSK1_OCIE1B TIMSK1 = (TIMSK1 & 0xF3) | 0x04
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#define CLR_TIMSK1_OCIE1B TIMSK1 &= 0xF3
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#else
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#define OCF1A_bm _BV(OCF1A)
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#define OCF1B_bm _BV(OCF1B)
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#define SET_TIMSK1_OCIE1B TIMSK1 |= _BV(OCIE1B)
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#define CLR_TIMSK1_OCIE1B TIMSK1 &=~_BV(OCIE1B)
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#endif
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//***************
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//*** Flags ***
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//***************
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@ -20,24 +20,25 @@
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You should have received a copy of the GNU General Public License
|
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along with Multiprotocol. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <avr/eeprom.h>
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#include <avr/pgmspace.h>
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//#define DEBUG_TX
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#include "Pins.h"
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#include "Multiprotocol.h"
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//Multiprotocol module configuration file
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#include "_Config.h"
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#include "Pins.h"
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#include "TX_Def.h"
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#include "Validate.h"
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#ifdef XMEGA
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#undef ENABLE_PPM // Disable PPM for OrangeTX module
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#undef A7105_INSTALLED // Disable A7105 for OrangeTX module
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#undef CC2500_INSTALLED // Disable CC2500 for OrangeTX module
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#undef NRF24L01_INSTALLED // Disable NRF for OrangeTX module
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#define TELEMETRY // Enable telemetry
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#define INVERT_TELEMETRY // Enable invert telemetry
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#define DSM_TELEMETRY // Enable DSM telemetry
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#ifndef STM32_BOARD
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#include <avr/eeprom.h>
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#else
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#undef __cplusplus
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#include <libmaple/usart.h>
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#include <libmaple/timer.h>
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#include <SPI.h>
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#include <EEPROM.h>
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HardwareTimer timer(2);
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#endif
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//Global constants/variables
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@ -97,7 +98,7 @@ uint8_t protocol_flags=0,protocol_flags2=0;
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// PPM variable
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volatile uint16_t PPM_data[NUM_CHN];
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#ifndef XMEGA
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#ifndef ORANGE_TX
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//Random variable
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volatile uint32_t gWDT_entropy=0;
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#endif
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@ -117,35 +118,17 @@ volatile uint8_t rx_buff[RXBUFFER_SIZE];
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volatile uint8_t rx_ok_buff[RXBUFFER_SIZE];
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volatile uint8_t discard_frame = 0;
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|
||||
//Make sure telemetry is selected correctly
|
||||
#ifndef TELEMETRY
|
||||
#undef INVERT_TELEMETRY
|
||||
#undef DSM_TELEMETRY
|
||||
#undef SPORT_TELEMETRY
|
||||
#undef HUB_TELEMETRY
|
||||
#else
|
||||
#if not defined(CYRF6936_INSTALLED) || not defined(DSM_CYRF6936_INO)
|
||||
#undef DSM_TELEMETRY
|
||||
#endif
|
||||
#if (not defined(CC2500_INSTALLED) || not defined(FRSKYD_CC2500_INO)) && (not defined(A7105_INSTALLED) || not defined(HUBSAN_A7105_INO))
|
||||
#undef HUB_TELEMETRY
|
||||
#endif
|
||||
#if not defined(CC2500_INSTALLED) || not defined(FRSKYX_CC2500_INO)
|
||||
#undef SPORT_TELEMETRY
|
||||
#endif
|
||||
#ifdef STM32_BOARD
|
||||
void PPM_decode();
|
||||
void ISR_COMPB();
|
||||
#endif
|
||||
#if not defined(DSM_TELEMETRY) && not defined(HUB_TELEMETRY) && not defined(SPORT_TELEMETRY)
|
||||
#undef TELEMETRY
|
||||
#undef INVERT_TELEMETRY
|
||||
#endif
|
||||
|
||||
// Telemetry
|
||||
#define MAX_PKT 27
|
||||
uint8_t pkt[MAX_PKT];//telemetry receiving packets
|
||||
#if defined(TELEMETRY)
|
||||
#ifdef INVERT_TELEMETRY
|
||||
// enable bit bash for serial
|
||||
#ifndef XMEGA
|
||||
#if not defined(ORANGE_TX) && not defined(STM32_BOARD)
|
||||
// enable bit bash for serial
|
||||
#define BASH_SERIAL 1
|
||||
#endif
|
||||
#define INVERT_SERIAL 1
|
||||
@ -160,9 +143,9 @@ uint8_t pkt[MAX_PKT];//telemetry receiving packets
|
||||
#endif // BASH_SERIAL
|
||||
uint8_t v_lipo;
|
||||
int16_t RSSI_dBm;
|
||||
//const uint8_t RSSI_offset=72;//69 71.72 values db
|
||||
uint8_t telemetry_link=0;
|
||||
uint8_t telemetry_counter=0;
|
||||
uint8_t telemetry_lost;
|
||||
#endif
|
||||
|
||||
// Callback
|
||||
@ -172,8 +155,9 @@ void_function_t remote_callback = 0;
|
||||
// Init
|
||||
void setup()
|
||||
{
|
||||
#ifdef XMEGA
|
||||
// General pinout
|
||||
// General pinout
|
||||
#ifdef ORANGE_TX
|
||||
//XMEGA
|
||||
PORTD.OUTSET = 0x17 ;
|
||||
PORTD.DIRSET = 0xB2 ;
|
||||
PORTD.DIRCLR = 0x4D ;
|
||||
@ -189,8 +173,40 @@ void setup()
|
||||
TCC1.PER = 0xFFFF ;
|
||||
TCNT1 = 0 ;
|
||||
TCC1.CTRLA = 0x0B ; // Event3 (prescale of 16)
|
||||
#else
|
||||
// General pinout
|
||||
#elif defined STM32_BOARD
|
||||
//STM32
|
||||
pinMode(A7105_CSN_pin,OUTPUT);
|
||||
pinMode(CC25_CSN_pin,OUTPUT);
|
||||
pinMode(NRF_CSN_pin,OUTPUT);
|
||||
pinMode(CYRF_CSN_pin,OUTPUT);
|
||||
pinMode(CYRF_RST_pin,OUTPUT);
|
||||
pinMode(PE1_pin,OUTPUT);
|
||||
pinMode(PE2_pin,OUTPUT);
|
||||
#if defined TELEMETRY
|
||||
pinMode(TX_INV_pin,OUTPUT);
|
||||
pinMode(RX_INV_pin,OUTPUT);
|
||||
#if defined INVERT_SERIAL
|
||||
TX_INV_on;//activated inverter for both serial TX and RX signals
|
||||
RX_INV_on;
|
||||
#else
|
||||
TX_INV_off;
|
||||
RX_INV_off;
|
||||
#endif
|
||||
#endif
|
||||
pinMode(BIND_pin,INPUT_PULLUP);
|
||||
pinMode(PPM_pin,INPUT);
|
||||
pinMode(S1_pin,INPUT_PULLUP);//dial switch
|
||||
pinMode(S2_pin,INPUT_PULLUP);
|
||||
pinMode(S3_pin,INPUT_PULLUP);
|
||||
pinMode(S4_pin,INPUT_PULLUP);
|
||||
//Random pins
|
||||
pinMode(PB0, INPUT_ANALOG); // set up pin for analog input
|
||||
pinMode(PB1, INPUT_ANALOG); // set up pin for analog input
|
||||
|
||||
//select the counter clock.
|
||||
start_timer2();//0.5us
|
||||
#else
|
||||
//ATMEGA328p
|
||||
// all inputs
|
||||
DDRB=0x00;DDRC=0x00;DDRD=0x00;
|
||||
// outputs
|
||||
@ -242,8 +258,12 @@ void setup()
|
||||
NRF_CSN_on;
|
||||
#endif
|
||||
// Set SPI lines
|
||||
SDI_on;
|
||||
SCLK_off;
|
||||
#ifdef STM32_BOARD
|
||||
initSPI2();
|
||||
#else
|
||||
SDI_on;
|
||||
SCLK_off;
|
||||
#endif
|
||||
|
||||
// Set servos positions
|
||||
for(uint8_t i=0;i<NUM_CHN;i++)
|
||||
@ -264,6 +284,8 @@ void setup()
|
||||
// after this mode_select will be one of {0000, 0001, ..., 1111}
|
||||
#ifndef ENABLE_PPM
|
||||
mode_select = MODE_SERIAL ; // force serial mode
|
||||
#elif defined STM32_BOARD
|
||||
mode_select= 0x0F -(uint8_t)(((GPIOA->regs->IDR)>>4)&0x0F);
|
||||
#else
|
||||
mode_select =
|
||||
((MODE_DIAL1_ipr & _BV(MODE_DIAL1_pin)) ? 0 : 1) +
|
||||
@ -279,9 +301,13 @@ void setup()
|
||||
//Init RF modules
|
||||
modules_reset();
|
||||
|
||||
#ifndef XMEGA
|
||||
#ifndef ORANGE_TX
|
||||
//Init the seed with a random value created from watchdog timer for all protocols requiring random values
|
||||
randomSeed(random_value());
|
||||
#ifdef STM32_BOARD
|
||||
randomSeed((uint32_t)analogRead(PB0) << 10 | analogRead(PB1));
|
||||
#else
|
||||
randomSeed(random_value());
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// Read or create protocol id
|
||||
@ -306,15 +332,19 @@ void setup()
|
||||
|
||||
protocol_init();
|
||||
|
||||
//Configure PPM interrupt
|
||||
#if PPM_pin == 2
|
||||
EICRA |= _BV(ISC01); // The rising edge of INT0 pin D2 generates an interrupt request
|
||||
EIMSK |= _BV(INT0); // INT0 interrupt enable
|
||||
#elif PPM_pin == 3
|
||||
EICRA |= _BV(ISC11); // The rising edge of INT1 pin D3 generates an interrupt request
|
||||
EIMSK |= _BV(INT1); // INT1 interrupt enable
|
||||
#ifndef STM32_BOARD
|
||||
//Configure PPM interrupt
|
||||
#if PPM_pin == 2
|
||||
EICRA |= _BV(ISC01); // The rising edge of INT0 pin D2 generates an interrupt request
|
||||
EIMSK |= _BV(INT0); // INT0 interrupt enable
|
||||
#elif PPM_pin == 3
|
||||
EICRA |= _BV(ISC11); // The rising edge of INT1 pin D3 generates an interrupt request
|
||||
EIMSK |= _BV(INT1); // INT1 interrupt enable
|
||||
#else
|
||||
#error PPM pin can only be 2 or 3
|
||||
#endif
|
||||
#else
|
||||
#error PPM pin can only be 2 or 3
|
||||
attachInterrupt(PPM_pin,PPM_decode,FALLING);
|
||||
#endif
|
||||
|
||||
#if defined(TELEMETRY)
|
||||
@ -351,14 +381,25 @@ void loop()
|
||||
}
|
||||
while(remote_callback==0);
|
||||
}
|
||||
if( (TIFR1 & OCF1A_bm) != 0)
|
||||
{
|
||||
cli(); // Disable global int due to RW of 16 bits registers
|
||||
OCR1A=TCNT1; // Callback should already have been called... Use "now" as new sync point.
|
||||
sei(); // Enable global int
|
||||
}
|
||||
else
|
||||
while((TIFR1 & OCF1A_bm) == 0); // Wait before callback
|
||||
#ifndef STM32_BOARD
|
||||
if( (TIFR1 & OCF1A_bm) != 0)
|
||||
{
|
||||
cli(); // Disable global int due to RW of 16 bits registers
|
||||
OCR1A=TCNT1; // Callback should already have been called... Use "now" as new sync point.
|
||||
sei(); // Enable global int
|
||||
}
|
||||
else
|
||||
while((TIFR1 & OCF1A_bm) == 0); // Wait before callback
|
||||
#else
|
||||
if((TIMER2_BASE->SR & TIMER_SR_CC1IF)!=0)
|
||||
{
|
||||
cli();
|
||||
OCR1A = TCNT1;
|
||||
sei();
|
||||
}
|
||||
else
|
||||
while((TIMER2_BASE->SR & TIMER_SR_CC1IF )==0); // Wait before callback
|
||||
#endif
|
||||
do
|
||||
{
|
||||
TX_MAIN_PAUSE_on;
|
||||
@ -371,18 +412,30 @@ void loop()
|
||||
next_callback-=2000; // We will wait below for 2ms
|
||||
cli(); // Disable global int due to RW of 16 bits registers
|
||||
OCR1A += 2000*2 ; // set compare A for callback
|
||||
TIFR1=OCF1A_bm; // clear compare A=callback flag
|
||||
#ifndef STM32_BOARD
|
||||
TIFR1=OCF1A_bm; // clear compare A=callback flag
|
||||
#else
|
||||
TIMER2_BASE->SR &= ~TIMER_SR_CC1IF; //clear compare Flag
|
||||
#endif
|
||||
sei(); // enable global int
|
||||
Update_All();
|
||||
if(IS_CHANGE_PROTOCOL_FLAG_on)
|
||||
break; // Protocol has been changed
|
||||
while((TIFR1 & OCF1A_bm) == 0); // wait 2ms...
|
||||
#ifndef STM32_BOARD
|
||||
while((TIFR1 & OCF1A_bm) == 0); // wait 2ms...
|
||||
#else
|
||||
while((TIMER2_BASE->SR & TIMER_SR_CC1IF)==0);//2ms wait
|
||||
#endif
|
||||
}
|
||||
// at this point we have a maximum of 4ms in next_callback
|
||||
next_callback *= 2 ;
|
||||
cli(); // Disable global int due to RW of 16 bits registers
|
||||
OCR1A+= next_callback ; // set compare A for callback
|
||||
TIFR1=OCF1A_bm; // clear compare A=callback flag
|
||||
#ifndef STM32_BOARD
|
||||
TIFR1=OCF1A_bm; // clear compare A=callback flag
|
||||
#else
|
||||
TIMER2_BASE->SR &= ~TIMER_SR_CC1IF; //clear compare Flag write zero
|
||||
#endif
|
||||
diff=OCR1A-TCNT1; // compare timer and comparator
|
||||
sei(); // enable global int
|
||||
}
|
||||
@ -465,12 +518,14 @@ static void update_led_status(void)
|
||||
|
||||
inline void tx_pause()
|
||||
{
|
||||
#ifdef TELEMETRY
|
||||
#ifdef XMEGA
|
||||
USARTC0.CTRLA &= ~0x03 ; // Pause telemetry by disabling transmitter interrupt
|
||||
#else
|
||||
#ifndef BASH_SERIAL
|
||||
UCSR0B &= ~_BV(UDRIE0); // Pause telemetry by disabling transmitter interrupt
|
||||
#ifndef STM32_BOARD
|
||||
#ifdef TELEMETRY
|
||||
#ifdef ORANGE_TX
|
||||
USARTC0.CTRLA &= ~0x03 ; // Pause telemetry by disabling transmitter interrupt
|
||||
#else
|
||||
#ifndef BASH_SERIAL
|
||||
UCSR0B &= ~_BV(UDRIE0); // Pause telemetry by disabling transmitter interrupt
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
@ -478,24 +533,41 @@ inline void tx_pause()
|
||||
|
||||
inline void tx_resume()
|
||||
{
|
||||
#ifdef TELEMETRY
|
||||
if(!IS_TX_PAUSE_on)
|
||||
{
|
||||
#ifdef XMEGA
|
||||
cli() ;
|
||||
USARTC0.CTRLA = (USARTC0.CTRLA & 0xFC) | 0x01 ; // Resume telemetry by enabling transmitter interrupt
|
||||
sei() ;
|
||||
#else
|
||||
#ifndef BASH_SERIAL
|
||||
UCSR0B |= _BV(UDRIE0); // Resume telemetry by enabling transmitter interrupt
|
||||
#ifndef STM32_BOARD
|
||||
#ifdef TELEMETRY
|
||||
if(!IS_TX_PAUSE_on)
|
||||
{
|
||||
#ifdef ORANGE_TX
|
||||
cli() ;
|
||||
USARTC0.CTRLA = (USARTC0.CTRLA & 0xFC) | 0x01 ; // Resume telemetry by enabling transmitter interrupt
|
||||
sei() ;
|
||||
#else
|
||||
resumeBashSerial() ;
|
||||
#ifndef BASH_SERIAL
|
||||
UCSR0B |= _BV(UDRIE0); // Resume telemetry by enabling transmitter interrupt
|
||||
#else
|
||||
resumeBashSerial() ;
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef STM32_BOARD
|
||||
void start_timer2()
|
||||
{
|
||||
// Pause the timer while we're configuring it
|
||||
timer.pause();
|
||||
TIMER2_BASE->PSC = 35; //36-1;for 72 MHZ /0.5sec/(35+1)
|
||||
TIMER2_BASE->ARR = 0xFFFF; //count till max
|
||||
timer.setMode(TIMER_CH1, TIMER_OUTPUT_COMPARE);
|
||||
timer.setMode(TIMER_CH2, TIMER_OUTPUT_COMPARE);
|
||||
// Refresh the timer's count, prescale, and overflow
|
||||
timer.refresh();
|
||||
timer.resume();
|
||||
}
|
||||
#endif
|
||||
|
||||
// Protocol start
|
||||
static void protocol_init()
|
||||
{
|
||||
@ -507,6 +579,7 @@ static void protocol_init()
|
||||
tx_pause();
|
||||
pass=0;
|
||||
telemetry_link=0;
|
||||
telemetry_lost=1;
|
||||
#ifndef BASH_SERIAL
|
||||
tx_tail=0;
|
||||
tx_head=0;
|
||||
@ -521,7 +594,7 @@ static void protocol_init()
|
||||
else
|
||||
BIND_DONE;
|
||||
|
||||
PE1_on; //NRF24L01 antenna RF3 by default
|
||||
PE1_on; //NRF24L01 antenna RF3 by default
|
||||
PE2_off; //NRF24L01 antenna RF3 by default
|
||||
|
||||
switch(protocol) // Init the requested protocol
|
||||
@ -593,13 +666,13 @@ static void protocol_init()
|
||||
{
|
||||
if(IS_BIND_BUTTON_FLAG_on)
|
||||
{
|
||||
eeprom_write_byte((uint8_t*)(30+mode_select),0x00); // reset to autobind mode for the current model
|
||||
eeprom_write_byte((EE_ADDR)(30+mode_select),0x00); // reset to autobind mode for the current model
|
||||
option=0;
|
||||
}
|
||||
else
|
||||
{
|
||||
option=eeprom_read_byte((uint8_t*)(30+mode_select)); // load previous mode: autobind or fixed id
|
||||
if(option!=1) option=0; // if not fixed id mode then it should be autobind
|
||||
option=eeprom_read_byte((EE_ADDR)(30+mode_select)); // load previous mode: autobind or fixed id
|
||||
if(option!=1) option=0; // if not fixed id mode then it should be autobind
|
||||
}
|
||||
}
|
||||
#endif //ENABLE_PPM
|
||||
@ -731,7 +804,11 @@ static void protocol_init()
|
||||
cli(); // disable global int
|
||||
OCR1A = TCNT1 + next_callback*2; // set compare A for callback
|
||||
sei(); // enable global int
|
||||
TIFR1 = OCF1A_bm ; // clear compare A flag
|
||||
#ifndef STM32_BOARD
|
||||
TIFR1 = OCF1A_bm ; // clear compare A flag
|
||||
#else
|
||||
TIMER2_BASE->SR &= ~TIMER_SR_CC1IF; //clear compare Flag write zero
|
||||
#endif
|
||||
BIND_BUTTON_FLAG_off; // do not bind/reset id anymore even if protocol change
|
||||
}
|
||||
|
||||
@ -787,7 +864,7 @@ void update_serial_data()
|
||||
Servo_data[i]=((((*((uint32_t *)p))>>dec)&0x7FF)*5)/8+860; //value range 860<->2140 -125%<->+125%
|
||||
}
|
||||
RX_DONOTUPDTAE_off;
|
||||
#ifdef XMEGA
|
||||
#ifdef ORANGE_TX
|
||||
cli();
|
||||
#else
|
||||
UCSR0B &= ~_BV(RXCIE0); // RX interrupt disable
|
||||
@ -797,7 +874,7 @@ void update_serial_data()
|
||||
RX_FLAG_on; // data to be processed next time...
|
||||
RX_MISSED_BUFF_off;
|
||||
}
|
||||
#ifdef XMEGA
|
||||
#ifdef ORANGE_TX
|
||||
sei();
|
||||
#else
|
||||
UCSR0B |= _BV(RXCIE0) ; // RX interrupt enable
|
||||
@ -826,7 +903,7 @@ void modules_reset()
|
||||
|
||||
void Mprotocol_serial_init()
|
||||
{
|
||||
#ifdef XMEGA
|
||||
#ifdef ORANGE_TX
|
||||
PORTC.OUTSET = 0x08 ;
|
||||
PORTC.DIRSET = 0x08 ;
|
||||
|
||||
@ -837,10 +914,17 @@ void Mprotocol_serial_init()
|
||||
USARTC0.CTRLA = (USARTC0.CTRLA & 0xCF) | 0x10 ;
|
||||
USARTC0.CTRLC = 0x2B ;
|
||||
UDR0 ;
|
||||
#ifdef INVERT_TELEMETRY
|
||||
#ifdef INVERT_SERIAL
|
||||
PORTC.PIN3CTRL |= 0x40 ;
|
||||
#endif
|
||||
#elif defined STM32_BOARD
|
||||
Serial1.begin(100000,SERIAL_8E2);//USART2
|
||||
Serial2.begin(100000,SERIAL_8E2);//USART3
|
||||
USART2_BASE->CR1 |= USART_CR1_PCE_BIT;
|
||||
USART3_BASE->CR1 &= ~ USART_CR1_RE;//disable
|
||||
USART2_BASE->CR1 &= ~ USART_CR1_TE;//disable transmit
|
||||
#else
|
||||
//ATMEGA328p
|
||||
#include <util/setbaud.h>
|
||||
UBRR0H = UBRRH_VALUE;
|
||||
UBRR0L = UBRRL_VALUE;
|
||||
@ -856,7 +940,7 @@ void Mprotocol_serial_init()
|
||||
initTXSerial( SPEED_100K ) ;
|
||||
#endif //TELEMETRY
|
||||
#endif //DEBUG_TX
|
||||
#endif //XMEGA
|
||||
#endif //ORANGE_TX
|
||||
}
|
||||
|
||||
#if defined(TELEMETRY)
|
||||
@ -881,7 +965,7 @@ static void set_rx_tx_addr(uint32_t id)
|
||||
rx_tx_addr[4] = (rx_tx_addr[2]&0xF0)|(rx_tx_addr[3]&0x0F);
|
||||
}
|
||||
|
||||
#ifndef XMEGA
|
||||
#if not defined (ORANGE_TX) && not defined (STM32_BOARD)
|
||||
static void random_init(void)
|
||||
{
|
||||
cli(); // Temporarily turn off interrupts, until WDT configured
|
||||
@ -900,24 +984,26 @@ static uint32_t random_value(void)
|
||||
|
||||
static uint32_t random_id(uint16_t adress, uint8_t create_new)
|
||||
{
|
||||
uint32_t id;
|
||||
uint8_t txid[4];
|
||||
uint32_t id=0;
|
||||
|
||||
if(eeprom_read_byte((uint8_t*)(adress+10))==0xf0 && !create_new)
|
||||
if(eeprom_read_byte((EE_ADDR)(adress+10))==0xf0 && !create_new)
|
||||
{ // TXID exists in EEPROM
|
||||
eeprom_read_block((void*)txid,(const void*)adress,4);
|
||||
id=(txid[0] | ((uint32_t)txid[1]<<8) | ((uint32_t)txid[2]<<16) | ((uint32_t)txid[3]<<24));
|
||||
for(uint8_t i=4;i>0;i--)
|
||||
{
|
||||
id<<=8;
|
||||
id|=eeprom_read_byte((EE_ADDR)adress+i-1);
|
||||
}
|
||||
if(id!=0x2AD141A7) //ID with seed=0
|
||||
return id;
|
||||
}
|
||||
// Generate a random ID
|
||||
id = random(0xfefefefe) + ((uint32_t)random(0xfefefefe) << 16);
|
||||
txid[0]= (id &0xFF);
|
||||
txid[1] = ((id >> 8) & 0xFF);
|
||||
txid[2] = ((id >> 16) & 0xFF);
|
||||
txid[3] = ((id >> 24) & 0xFF);
|
||||
eeprom_write_block((const void*)txid,(void*)adress,4);
|
||||
eeprom_write_byte((uint8_t*)(adress+10),0xf0);//write bind flag in eeprom.
|
||||
for(uint8_t i=0;i<4;i++)
|
||||
{
|
||||
eeprom_write_byte((EE_ADDR)adress+i,id);
|
||||
id>>=8;
|
||||
}
|
||||
eeprom_write_byte((EE_ADDR)(adress+10),0xf0);//write bind flag in eeprom.
|
||||
return id;
|
||||
}
|
||||
|
||||
@ -929,12 +1015,14 @@ static uint32_t random_id(uint16_t adress, uint8_t create_new)
|
||||
|
||||
//PPM
|
||||
#ifdef ENABLE_PPM
|
||||
#ifdef XMEGA
|
||||
#ifdef ORANGE_TX
|
||||
#if PPM_pin == 2
|
||||
ISR(PORTD_INT0_vect)
|
||||
#else
|
||||
ISR(PORTD_INT1_vect)
|
||||
#endif
|
||||
#elif defined STM32_BOARD
|
||||
void PPM_decode()
|
||||
#else
|
||||
#if PPM_pin == 2
|
||||
ISR(INT0_vect, ISR_NOBLOCK)
|
||||
@ -969,15 +1057,22 @@ static uint32_t random_id(uint16_t adress, uint8_t create_new)
|
||||
|
||||
//Serial RX
|
||||
#ifdef ENABLE_SERIAL
|
||||
#ifdef XMEGA
|
||||
#ifdef ORANGE_TX
|
||||
ISR(USARTC0_RXC_vect)
|
||||
#elif defined STM32_BOARD
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void __irq_usart2()
|
||||
#else
|
||||
ISR(USART_RX_vect)
|
||||
#endif
|
||||
{ // RX interrupt
|
||||
static uint8_t idx=0;
|
||||
#ifdef XMEGA
|
||||
#ifdef ORANGE_TX
|
||||
if((USARTC0.STATUS & 0x1C)==0) // Check frame error, data overrun and parity error
|
||||
#elif defined STM32_BOARD
|
||||
if((USART2_BASE->SR & USART_SR_RXNE) && (USART2_BASE->SR &0x0F)==0)
|
||||
#else
|
||||
UCSR0B &= ~_BV(RXCIE0) ; // RX interrupt disable
|
||||
sei() ;
|
||||
@ -991,11 +1086,18 @@ static uint32_t random_id(uint16_t adress, uint8_t create_new)
|
||||
rx_buff[0]=UDR0;
|
||||
if((rx_buff[0]&0xFE)==0x54) // If 1st byte is 0x54 or 0x55 it looks ok
|
||||
{
|
||||
TX_RX_PAUSE_on;
|
||||
tx_pause();
|
||||
OCR1B = TCNT1+(6500L) ; // Full message should be received within timer of 3250us
|
||||
TIFR1 = OCF1B_bm ; // clear OCR1B match flag
|
||||
SET_TIMSK1_OCIE1B ; // enable interrupt on compare B match
|
||||
#if defined STM32_BOARD
|
||||
uint16_t OCR1B;
|
||||
OCR1B =TCNT1+(6500L);
|
||||
timer.setCompare(TIMER_CH2,OCR1B);
|
||||
timer.attachCompare2Interrupt(ISR_COMPB);
|
||||
#else
|
||||
TX_RX_PAUSE_on;
|
||||
tx_pause();
|
||||
OCR1B = TCNT1+(6500L) ; // Full message should be received within timer of 3250us
|
||||
TIFR1 = OCF1B_bm ; // clear OCR1B match flag
|
||||
SET_TIMSK1_OCIE1B ; // enable interrupt on compare B match
|
||||
#endif
|
||||
idx++;
|
||||
}
|
||||
}
|
||||
@ -1022,30 +1124,43 @@ static uint32_t random_id(uint16_t adress, uint8_t create_new)
|
||||
}
|
||||
if(discard_frame==1)
|
||||
{
|
||||
CLR_TIMSK1_OCIE1B; // Disable interrupt on compare B match
|
||||
TX_RX_PAUSE_off;
|
||||
tx_resume();
|
||||
#ifdef STM32_BOARD
|
||||
detachInterrupt(2); // Disable interrupt on ch2
|
||||
#else
|
||||
CLR_TIMSK1_OCIE1B; // Disable interrupt on compare B match
|
||||
TX_RX_PAUSE_off;
|
||||
tx_resume();
|
||||
#endif
|
||||
}
|
||||
#ifndef XMEGA
|
||||
#if not defined (ORANGE_TX) && not defined (STM32_BOARD)
|
||||
cli() ;
|
||||
UCSR0B |= _BV(RXCIE0) ; // RX interrupt enable
|
||||
#endif
|
||||
}
|
||||
#if defined (STM32_BOARD) && defined (__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
//Serial timer
|
||||
#ifdef XMEGA
|
||||
#ifdef ORANGE_TX
|
||||
ISR(TCC1_CCB_vect)
|
||||
#elif defined STM32_BOARD
|
||||
void ISR_COMPB()
|
||||
#else
|
||||
ISR(TIMER1_COMPB_vect, ISR_NOBLOCK )
|
||||
#endif
|
||||
{ // Timer1 compare B interrupt
|
||||
discard_frame=1;
|
||||
CLR_TIMSK1_OCIE1B; // Disable interrupt on compare B match
|
||||
tx_resume();
|
||||
#ifdef STM32_BOARD
|
||||
detachInterrupt(2); // Disable interrupt on ch2
|
||||
#else
|
||||
CLR_TIMSK1_OCIE1B; // Disable interrupt on compare B match
|
||||
tx_resume();
|
||||
#endif
|
||||
}
|
||||
#endif //ENABLE_SERIAL
|
||||
|
||||
#ifndef XMEGA
|
||||
#if not defined (ORANGE_TX) && not defined (STM32_BOARD)
|
||||
// Random interrupt service routine called every time the WDT interrupt is triggered.
|
||||
// It is only enabled at startup to generate a seed.
|
||||
ISR(WDT_vect)
|
||||
|
||||
@ -14,9 +14,7 @@
|
||||
*/
|
||||
|
||||
|
||||
//---------------------------
|
||||
// AVR nrf chip bitbang SPI functions
|
||||
//---------------------------
|
||||
#ifdef NRF24L01_INSTALLED
|
||||
#include "iface_nrf24l01.h"
|
||||
|
||||
|
||||
@ -181,7 +179,8 @@ void NRF24L01_SetTxRxMode(enum TXRX_State mode)
|
||||
NRF_CE_on;
|
||||
}
|
||||
else
|
||||
if (mode == RX_EN) {
|
||||
if (mode == RX_EN)
|
||||
{
|
||||
NRF_CE_off;
|
||||
NRF24L01_WriteReg(NRF24L01_07_STATUS, 0x70); // reset the flag(s)
|
||||
NRF24L01_WriteReg(NRF24L01_00_CONFIG, 0x0F); // switch to RX mode
|
||||
@ -327,7 +326,7 @@ void XN297_Configure(uint8_t flags)
|
||||
NRF24L01_WriteReg(NRF24L01_00_CONFIG, flags & 0xFF);
|
||||
}
|
||||
|
||||
void XN297_SetScrambledMode(const u8 mode)
|
||||
void XN297_SetScrambledMode(const uint8_t mode)
|
||||
{
|
||||
xn297_scramble_enabled = mode;
|
||||
}
|
||||
@ -583,3 +582,4 @@ void LT8900_WritePayload(uint8_t* msg, uint8_t len)
|
||||
NRF24L01_WritePayload(LT8900_buffer+LT8900_buffer_start,pos_final+pos-LT8900_buffer_start);
|
||||
}
|
||||
// End of LT8900 emulation
|
||||
#endif
|
||||
@ -15,195 +15,338 @@
|
||||
//*******************
|
||||
//*** Pinouts ***
|
||||
//*******************
|
||||
#ifndef STM32_BOARD
|
||||
// TX
|
||||
#define SERIAL_TX_pin 1 //PD1
|
||||
#define SERIAL_TX_port PORTD
|
||||
#define SERIAL_TX_ddr DDRD
|
||||
#define SERIAL_TX_output SERIAL_TX_ddr |= _BV(SERIAL_TX_pin)
|
||||
#define SERIAL_TX_on SERIAL_TX_port |= _BV(SERIAL_TX_pin)
|
||||
#define SERIAL_TX_off SERIAL_TX_port &= ~_BV(SERIAL_TX_pin)
|
||||
#ifdef DEBUG_TX
|
||||
#define DEBUG_TX_on SERIAL_TX_on
|
||||
#define DEBUG_TX_off SERIAL_TX_off
|
||||
#define DEBUG_TX_toggle SERIAL_TX_port ^= _BV(SERIAL_TX_pin)
|
||||
#else
|
||||
#define DEBUG_TX_on
|
||||
#define DEBUG_TX_off
|
||||
#define DEBUG_TX_toggle
|
||||
#endif
|
||||
|
||||
// TX
|
||||
#define SERIAL_TX_pin 1 //PD1
|
||||
#define SERIAL_TX_port PORTD
|
||||
#define SERIAL_TX_ddr DDRD
|
||||
#define SERIAL_TX_output SERIAL_TX_ddr |= _BV(SERIAL_TX_pin)
|
||||
#define SERIAL_TX_on SERIAL_TX_port |= _BV(SERIAL_TX_pin)
|
||||
#define SERIAL_TX_off SERIAL_TX_port &= ~_BV(SERIAL_TX_pin)
|
||||
#ifdef DEBUG_TX
|
||||
#define DEBUG_TX_on SERIAL_TX_ON
|
||||
#define DEBUG_TX_off SERIAL_TX_OFF
|
||||
#define DEBUG_TX_toggle SERIAL_TX_port ^= _BV(SERIAL_TX_pin)
|
||||
#else
|
||||
#define DEBUG_TX_on
|
||||
#define DEBUG_TX_off
|
||||
#define DEBUG_TX_toggle
|
||||
// Dial
|
||||
#define MODE_DIAL1_pin 2
|
||||
#define MODE_DIAL1_port PORTB
|
||||
#define MODE_DIAL1_ipr PINB
|
||||
#define MODE_DIAL2_pin 3
|
||||
#define MODE_DIAL2_port PORTB
|
||||
#define MODE_DIAL2_ipr PINB
|
||||
#define MODE_DIAL3_pin 4
|
||||
#define MODE_DIAL3_port PORTB
|
||||
#define MODE_DIAL3_ipr PINB
|
||||
#define MODE_DIAL4_pin 0
|
||||
#define MODE_DIAL4_port PORTC
|
||||
#define MODE_DIAL4_ipr PINC
|
||||
|
||||
// PPM
|
||||
#define PPM_pin 3 //D3 = PD3
|
||||
#define PPM_port PORTD
|
||||
|
||||
// SDIO
|
||||
#define SDI_pin 5 //D5 = PD5
|
||||
#define SDI_port PORTD
|
||||
#define SDI_ipr PIND
|
||||
#define SDI_ddr DDRD
|
||||
#ifdef ORANGE_TX
|
||||
#define SDI_on SDI_port.OUTSET = _BV(SDI_pin)
|
||||
#define SDI_off SDI_port.OUTCLR = _BV(SDI_pin)
|
||||
#else
|
||||
#define SDI_on SDI_port |= _BV(SDI_pin)
|
||||
#define SDI_off SDI_port &= ~_BV(SDI_pin)
|
||||
#define SDI_1 (SDI_ipr & _BV(SDI_pin))
|
||||
#define SDI_0 (SDI_ipr & _BV(SDI_pin)) == 0x00
|
||||
#endif
|
||||
#define SDI_input SDI_ddr &= ~_BV(SDI_pin)
|
||||
#define SDI_output SDI_ddr |= _BV(SDI_pin)
|
||||
|
||||
//SDO
|
||||
#define SDO_pin 6 //D6 = PD6
|
||||
#define SDO_port PORTD
|
||||
#define SDO_ipr PIND
|
||||
#ifdef ORANGE_TX
|
||||
#define SDO_1 (SDO_port.IN & _BV(SDO_pin))
|
||||
#define SDO_0 (SDO_port.IN & _BV(SDO_pin)) == 0x00
|
||||
#else
|
||||
#define SDO_1 (SDO_ipr & _BV(SDO_pin))
|
||||
#define SDO_0 (SDO_ipr & _BV(SDO_pin)) == 0x00
|
||||
#endif
|
||||
|
||||
// SCLK
|
||||
#define SCLK_port PORTD
|
||||
#define SCLK_ddr DDRD
|
||||
#ifdef ORANGE_TX
|
||||
#define SCLK_pin 7 //PD7
|
||||
#define SCLK_on SCLK_port.OUTSET = _BV(SCLK_pin)
|
||||
#define SCLK_off SCLK_port.OUTCLR = _BV(SCLK_pin)
|
||||
#else
|
||||
#define SCLK_pin 4 //D4 = PD4
|
||||
#define SCLK_output SCLK_ddr |= _BV(SCLK_pin)
|
||||
#define SCLK_on SCLK_port |= _BV(SCLK_pin)
|
||||
#define SCLK_off SCLK_port &= ~_BV(SCLK_pin)
|
||||
#endif
|
||||
|
||||
// A7105
|
||||
#define A7105_CSN_pin 2 //D2 = PD2
|
||||
#define A7105_CSN_port PORTD
|
||||
#define A7105_CSN_ddr DDRD
|
||||
#define A7105_CSN_output A7105_CSN_ddr |= _BV(A7105_CSN_pin)
|
||||
#define A7105_CSN_on A7105_CSN_port |= _BV(A7105_CSN_pin)
|
||||
#define A7105_CSN_off A7105_CSN_port &= ~_BV(A7105_CSN_pin)
|
||||
|
||||
// CC2500
|
||||
#define CC25_CSN_pin 7 //D7 = PD7
|
||||
#define CC25_CSN_port PORTD
|
||||
#define CC25_CSN_ddr DDRD
|
||||
#define CC25_CSN_output CC25_CSN_ddr |= _BV(CC25_CSN_pin)
|
||||
#define CC25_CSN_on CC25_CSN_port |= _BV(CC25_CSN_pin)
|
||||
#define CC25_CSN_off CC25_CSN_port &= ~_BV(CC25_CSN_pin)
|
||||
|
||||
// NRF24L01
|
||||
#define NRF_CSN_pin 0 //D8 = PB0
|
||||
#define NRF_CSN_port PORTB
|
||||
#define NRF_CSN_ddr DDRB
|
||||
#define NRF_CSN_output NRF_CSN_ddr |= _BV(NRF_CSN_pin)
|
||||
#define NRF_CSN_on NRF_CSN_port |= _BV(NRF_CSN_pin)
|
||||
#define NRF_CSN_off NRF_CSN_port &= ~_BV(NRF_CSN_pin)
|
||||
#define NRF_CE_on
|
||||
#define NRF_CE_off
|
||||
|
||||
// CYRF6936
|
||||
#ifdef ORANGE_TX
|
||||
#define CYRF_CSN_pin 4 //PD4
|
||||
#define CYRF_CSN_port PORTD
|
||||
#define CYRF_CSN_ddr DDRD
|
||||
#define CYRF_CSN_on CYRF_CSN_port.OUTSET = _BV(CYRF_CSN_pin)
|
||||
#define CYRF_CSN_off CYRF_CSN_port.OUTCLR = _BV(CYRF_CSN_pin)
|
||||
|
||||
#define CYRF_RST_pin 0 //PE0
|
||||
#define CYRF_RST_port PORTE
|
||||
#define CYRF_RST_ddr DDRE
|
||||
#define CYRF_RST_HI CYRF_RST_port.OUTSET = _BV(CYRF_RST_pin)
|
||||
#define CYRF_RST_LO CYRF_RST_port.OUTCLR = _BV(CYRF_RST_pin)
|
||||
#else
|
||||
#define CYRF_CSN_pin 1 //D9 = PB1
|
||||
#define CYRF_CSN_port PORTB
|
||||
#define CYRF_CSN_ddr DDRB
|
||||
#define CYRF_CSN_output CYRF_CSN_ddr |= _BV(CYRF_CSN_pin)
|
||||
#define CYRF_CSN_on CYRF_CSN_port |= _BV(CYRF_CSN_pin)
|
||||
#define CYRF_CSN_off CYRF_CSN_port &= ~_BV(CYRF_CSN_pin)
|
||||
|
||||
#define CYRF_RST_pin 5 //A5 = PC5
|
||||
#define CYRF_RST_port PORTC
|
||||
#define CYRF_RST_ddr DDRC
|
||||
#define CYRF_RST_output CYRF_RST_ddr |= _BV(CYRF_RST_pin)
|
||||
#define CYRF_RST_HI CYRF_RST_port |= _BV(CYRF_RST_pin)
|
||||
#define CYRF_RST_LO CYRF_RST_port &= ~_BV(CYRF_RST_pin)
|
||||
#endif
|
||||
|
||||
//RF Switch
|
||||
#ifdef ORANGE_TX
|
||||
#define PE1_on
|
||||
#define PE1_off
|
||||
#define PE2_on
|
||||
#define PE2_off
|
||||
#else
|
||||
#define PE1_pin 1 //A1 = PC1
|
||||
#define PE1_port PORTC
|
||||
#define PE1_ddr DDRC
|
||||
#define PE1_output PE1_ddr |= _BV(PE1_pin)
|
||||
#define PE1_on PE1_port |= _BV(PE1_pin)
|
||||
#define PE1_off PE1_port &= ~_BV(PE1_pin)
|
||||
|
||||
#define PE2_pin 2 //A2 = PC2
|
||||
#define PE2_port PORTC
|
||||
#define PE2_ddr DDRC
|
||||
#define PE2_output PE2_ddr |= _BV(PE2_pin)
|
||||
#define PE2_on PE2_port |= _BV(PE2_pin)
|
||||
#define PE2_off PE2_port &= ~_BV(PE2_pin)
|
||||
#endif
|
||||
|
||||
// LED
|
||||
#ifdef ORANGE_TX
|
||||
#define LED_pin 1 //PD1
|
||||
#define LED_port PORTD
|
||||
#define LED_ddr DDRD
|
||||
#define LED_on LED_port.OUTCLR = _BV(LED_pin)
|
||||
#define LED_off LED_port.OUTSET = _BV(LED_pin)
|
||||
#define LED_toggle LED_port.OUTTGL = _BV(LED_pin)
|
||||
#define LED_output LED_port.DIRSET = _BV(LED_pin)
|
||||
#define IS_LED_on (LED_port.OUT & _BV(LED_pin))
|
||||
#else
|
||||
#define LED_pin 5 //D13 = PB5
|
||||
#define LED_port PORTB
|
||||
#define LED_ddr DDRB
|
||||
#define LED_on LED_port |= _BV(LED_pin)
|
||||
#define LED_off LED_port &= ~_BV(LED_pin)
|
||||
#define LED_toggle LED_port ^= _BV(LED_pin)
|
||||
#define LED_output LED_ddr |= _BV(LED_pin)
|
||||
#define IS_LED_on (LED_port & _BV(LED_pin))
|
||||
#endif
|
||||
|
||||
//BIND
|
||||
#ifdef ORANGE_TX
|
||||
#define BIND_pin 2 //PD2
|
||||
#define BIND_port PORTD
|
||||
#define IS_BIND_BUTTON_on ( (BIND_port.IN & _BV(BIND_pin)) == 0x00 )
|
||||
#else
|
||||
#define BIND_pin 5 //D13 = PB5
|
||||
#define BIND_port PORTB
|
||||
#define BIND_ipr PINB
|
||||
#define BIND_ddr DDRB
|
||||
#define BIND_SET_INPUT BIND_ddr &= ~_BV(BIND_pin)
|
||||
#define BIND_SET_OUTPUT BIND_ddr |= _BV(BIND_pin)
|
||||
#define BIND_SET_PULLUP BIND_port |= _BV(BIND_pin)
|
||||
#define IS_BIND_BUTTON_on ( (BIND_ipr & _BV(BIND_pin)) == 0x00 )
|
||||
#endif
|
||||
#else //STM32_BOARD
|
||||
#define BIND_pin PA0
|
||||
#define LED_pin PA1
|
||||
//
|
||||
#define PPM_pin PA8 //PPM 5V tolerant
|
||||
//
|
||||
#define S1_pin PA4 //Dial switch pins
|
||||
#define S2_pin PA5
|
||||
#define S3_pin PA6
|
||||
#define S4_pin PA7
|
||||
//
|
||||
#define PE1_pin PB4 //PE1
|
||||
#define PE2_pin PB5 //PE2
|
||||
//CS pins
|
||||
#define CC25_CSN_pin PB6 //CC2500
|
||||
#define NRF_CSN_pin PB7 //NRF24L01
|
||||
#define CYRF_RST_pin PB8 //CYRF RESET
|
||||
#define A7105_CSN_pin PB9 //A7105
|
||||
#define CYRF_CSN_pin PB12 //CYRF CSN
|
||||
//SPI pins
|
||||
#define SCK_pin PB13 //SCK
|
||||
#define SDO_pin PB14 //MISO
|
||||
#define SDI_pin PB15 //MOSI
|
||||
//
|
||||
#define TX_INV_pin PB3
|
||||
#define RX_INV_pin PB1
|
||||
//
|
||||
#define PE1_on digitalWrite(PE1_pin,HIGH)
|
||||
#define PE1_off digitalWrite(PE1_pin,LOW)
|
||||
//
|
||||
#define PE2_on digitalWrite(PE2_pin,HIGH)
|
||||
#define PE2_off digitalWrite(PE2_pin,LOW)
|
||||
|
||||
#define A7105_CSN_on digitalWrite(A7105_CSN_pin,HIGH)
|
||||
#define A7105_CSN_off digitalWrite(A7105_CSN_pin,LOW)
|
||||
|
||||
#define NRF_CE_on
|
||||
#define NRF_CE_off
|
||||
|
||||
#define SCK_on digitalWrite(SCK_pin,HIGH)
|
||||
#define SCK_off digitalWrite(SCK_pin,LOW)
|
||||
|
||||
#define SDI_on digitalWrite(SDI_pin,HIGH)
|
||||
#define SDI_off digitalWrite(SDI_pin,LOW)
|
||||
|
||||
#define SDI_1 (digitalRead(SDI_pin)==HIGH)
|
||||
#define SDI_0 (digitalRead(SDI_pin)==LOW)
|
||||
|
||||
#define CC25_CSN_on digitalWrite(CC25_CSN_pin,HIGH)
|
||||
#define CC25_CSN_off digitalWrite(CC25_CSN_pin,LOW)
|
||||
|
||||
#define NRF_CSN_on digitalWrite(NRF_CSN_pin,HIGH)
|
||||
#define NRF_CSN_off digitalWrite(NRF_CSN_pin,LOW)
|
||||
|
||||
#define CYRF_CSN_on digitalWrite(CYRF_CSN_pin,HIGH)
|
||||
#define CYRF_CSN_off digitalWrite(CYRF_CSN_pin,LOW)
|
||||
|
||||
#define CYRF_RST_HI digitalWrite(CYRF_RST_pin,HIGH) //reset cyrf
|
||||
#define CYRF_RST_LO digitalWrite(CYRF_RST_pin,LOW) //
|
||||
|
||||
#define SDO_1 (digitalRead(SDO_pin)==HIGH)
|
||||
#define SDO_0 (digitalRead(SDO_pin)==LOW)
|
||||
|
||||
#define TX_INV_on digitalWrite(TX_INV_pin,HIGH)
|
||||
#define TX_INV_off digitalWrite(TX_INV_pin,LOW)
|
||||
|
||||
#define RX_INV_on digitalWrite(RX_INV_pin,HIGH)
|
||||
#define RX_INV_off digitalWrite(RX_INV_pin,LOW)
|
||||
|
||||
#define LED_on digitalWrite(LED_pin,HIGH)
|
||||
#define LED_off digitalWrite(LED_pin,LOW)
|
||||
#define LED_toggle digitalWrite(LED_pin ,!digitalRead(LED_pin))
|
||||
#define LED_output pinMode(LED_pin,OUTPUT)
|
||||
#define IS_LED_on ( digitalRead(LED_pin)==HIGH)
|
||||
|
||||
#define BIND_SET_INPUT pinMode(BIND_pin,INPUT)
|
||||
#define BIND_SET_PULLUP digitalWrite(BIND_pin,HIGH)
|
||||
#define BIND_SET_OUTPUT pinMode(BIND_pin,OUTPUT)
|
||||
#define IS_BIND_BUTTON_on (digitalRead(BIND_pin)==LOW)
|
||||
|
||||
#define cli() noInterrupts()
|
||||
#define sei() interrupts()
|
||||
#define delayMilliseconds(x) delay(x)
|
||||
//TX Pause
|
||||
#undef TX_MAIN_PAUSE_off
|
||||
#undef TX_MAIN_PAUSE_on
|
||||
#undef IS_TX_MAIN_PAUSE_on
|
||||
#undef TX_RX_PAUSE_off
|
||||
#undef TX_RX_PAUSE_on
|
||||
#undef IS_TX_RX_PAUSE_on
|
||||
#undef IS_TX_PAUSE_on
|
||||
#define TX_MAIN_PAUSE_off
|
||||
#define TX_MAIN_PAUSE_on
|
||||
#define IS_TX_MAIN_PAUSE_on
|
||||
#define TX_RX_PAUSE_off
|
||||
#define TX_RX_PAUSE_on
|
||||
#define IS_TX_RX_PAUSE_on
|
||||
#define IS_TX_PAUSE_on
|
||||
#endif
|
||||
|
||||
// Dial
|
||||
#define MODE_DIAL1_pin 2
|
||||
#define MODE_DIAL1_port PORTB
|
||||
#define MODE_DIAL1_ipr PINB
|
||||
#define MODE_DIAL2_pin 3
|
||||
#define MODE_DIAL2_port PORTB
|
||||
#define MODE_DIAL2_ipr PINB
|
||||
#define MODE_DIAL3_pin 4
|
||||
#define MODE_DIAL3_port PORTB
|
||||
#define MODE_DIAL3_ipr PINB
|
||||
#define MODE_DIAL4_pin 0
|
||||
#define MODE_DIAL4_port PORTC
|
||||
#define MODE_DIAL4_ipr PINC
|
||||
|
||||
// PPM
|
||||
#define PPM_pin 3 //D3 = PD3
|
||||
#define PPM_port PORTD
|
||||
|
||||
// SDIO
|
||||
#define SDI_pin 5 //D5 = PD5
|
||||
#define SDI_port PORTD
|
||||
#define SDI_ipr PIND
|
||||
#define SDI_ddr DDRD
|
||||
#ifdef XMEGA
|
||||
#define SDI_on SDI_port.OUTSET = _BV(SDI_pin)
|
||||
#define SDI_off SDI_port.OUTCLR = _BV(SDI_pin)
|
||||
//*******************
|
||||
//*** Timer ***
|
||||
//*******************
|
||||
#ifdef ORANGE_TX
|
||||
#define TIFR1 TCC1.INTFLAGS
|
||||
#define OCF1A_bm TC1_CCAIF_bm
|
||||
#define OCR1A TCC1.CCA
|
||||
#define TCNT1 TCC1.CNT
|
||||
#define UDR0 USARTC0.DATA
|
||||
#define OCF1B_bm TC1_CCBIF_bm
|
||||
#define OCR1B TCC1.CCB
|
||||
#define TIMSK1 TCC1.INTCTRLB
|
||||
#define SET_TIMSK1_OCIE1B TIMSK1 = (TIMSK1 & 0xF3) | 0x04
|
||||
#define CLR_TIMSK1_OCIE1B TIMSK1 &= 0xF3
|
||||
#else
|
||||
#define SDI_on SDI_port |= _BV(SDI_pin)
|
||||
#define SDI_off SDI_port &= ~_BV(SDI_pin)
|
||||
#define SDI_1 (SDI_ipr & _BV(SDI_pin))
|
||||
#define SDI_0 (SDI_ipr & _BV(SDI_pin)) == 0x00
|
||||
#endif
|
||||
#define SDI_input SDI_ddr &= ~_BV(SDI_pin)
|
||||
#define SDI_output SDI_ddr |= _BV(SDI_pin)
|
||||
|
||||
//SDO
|
||||
#define SDO_pin 6 //D6 = PD6
|
||||
#define SDO_port PORTD
|
||||
#define SDO_ipr PIND
|
||||
#ifdef XMEGA
|
||||
#define SDO_1 (SDO_port.IN & _BV(SDO_pin))
|
||||
#define SDO_0 (SDO_port.IN & _BV(SDO_pin)) == 0x00
|
||||
#else
|
||||
#define SDO_1 (SDO_ipr & _BV(SDO_pin))
|
||||
#define SDO_0 (SDO_ipr & _BV(SDO_pin)) == 0x00
|
||||
#ifdef STM32_BOARD
|
||||
#define OCR1A TIMER2_BASE->CCR1
|
||||
#define TCNT1 TIMER2_BASE->CNT
|
||||
#define UDR0 USART2_BASE->DR
|
||||
#define TIFR1 TIMER2_BASE->SR
|
||||
#define OCF1A_bm TIMER_SR_CC1IF
|
||||
#define UCSR0B USART2_BASE->CR1
|
||||
#define RXCIE0 USART_CR1_RXNEIE_BIT
|
||||
#define TXCIE0 USART_CR1_TXEIE_BIT
|
||||
//#define TIFR1 TIMER2_BASE->SR
|
||||
#else
|
||||
#define OCF1A_bm _BV(OCF1A)
|
||||
#define OCF1B_bm _BV(OCF1B)
|
||||
#define SET_TIMSK1_OCIE1B TIMSK1 |= _BV(OCIE1B)
|
||||
#define CLR_TIMSK1_OCIE1B TIMSK1 &=~_BV(OCIE1B)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// SCLK
|
||||
#define SCLK_port PORTD
|
||||
#define SCLK_ddr DDRD
|
||||
#ifdef XMEGA
|
||||
#define SCLK_pin 7 //PD7
|
||||
#define SCLK_on SCLK_port.OUTSET = _BV(SCLK_pin)
|
||||
#define SCLK_off SCLK_port.OUTCLR = _BV(SCLK_pin)
|
||||
//*******************
|
||||
//*** EEPROM ***
|
||||
//*******************
|
||||
#ifdef STM32_BOARD
|
||||
#define EE_ADDR uint16
|
||||
#define eeprom_write_byte EEPROM.write
|
||||
#define eeprom_read_byte EEPROM.read
|
||||
#else
|
||||
#define SCLK_pin 4 //D4 = PD4
|
||||
#define SCLK_output SCLK_ddr |= _BV(SCLK_pin)
|
||||
#define SCLK_on SCLK_port |= _BV(SCLK_pin)
|
||||
#define SCLK_off SCLK_port &= ~_BV(SCLK_pin)
|
||||
#endif
|
||||
|
||||
// A7105
|
||||
#define A7105_CSN_pin 2 //D2 = PD2
|
||||
#define A7105_CSN_port PORTD
|
||||
#define A7105_CSN_ddr DDRD
|
||||
#define A7105_CSN_output A7105_CSN_ddr |= _BV(A7105_CSN_pin)
|
||||
#define A7105_CSN_on A7105_CSN_port |= _BV(A7105_CSN_pin)
|
||||
#define A7105_CSN_off A7105_CSN_port &= ~_BV(A7105_CSN_pin)
|
||||
|
||||
// CC2500
|
||||
#define CC25_CSN_pin 7 //D7 = PD7
|
||||
#define CC25_CSN_port PORTD
|
||||
#define CC25_CSN_ddr DDRD
|
||||
#define CC25_CSN_output CC25_CSN_ddr |= _BV(CC25_CSN_pin)
|
||||
#define CC25_CSN_on CC25_CSN_port |= _BV(CC25_CSN_pin)
|
||||
#define CC25_CSN_off CC25_CSN_port &= ~_BV(CC25_CSN_pin)
|
||||
|
||||
// NRF24L01
|
||||
#define NRF_CSN_pin 0 //D8 = PB0
|
||||
#define NRF_CSN_port PORTB
|
||||
#define NRF_CSN_ddr DDRB
|
||||
#define NRF_CSN_output NRF_CSN_ddr |= _BV(NRF_CSN_pin)
|
||||
#define NRF_CSN_on NRF_CSN_port |= _BV(NRF_CSN_pin)
|
||||
#define NRF_CSN_off NRF_CSN_port &= ~_BV(NRF_CSN_pin)
|
||||
#define NRF_CE_on
|
||||
#define NRF_CE_off
|
||||
|
||||
// CYRF6936
|
||||
#ifdef XMEGA
|
||||
#define CYRF_CSN_pin 4 //PD4
|
||||
#define CYRF_CSN_port PORTD
|
||||
#define CYRF_CSN_ddr DDRD
|
||||
#define CYRF_CSN_on CYRF_CSN_port.OUTSET = _BV(CYRF_CSN_pin)
|
||||
#define CYRF_CSN_off CYRF_CSN_port.OUTCLR = _BV(CYRF_CSN_pin)
|
||||
|
||||
#define CYRF_RST_pin 0 //PE0
|
||||
#define CYRF_RST_port PORTE
|
||||
#define CYRF_RST_ddr DDRE
|
||||
#define CYRF_RST_HI CYRF_RST_port.OUTSET = _BV(CYRF_RST_pin)
|
||||
#define CYRF_RST_LO CYRF_RST_port.OUTCLR = _BV(CYRF_RST_pin)
|
||||
#else
|
||||
#define CYRF_CSN_pin 1 //D9 = PB1
|
||||
#define CYRF_CSN_port PORTB
|
||||
#define CYRF_CSN_ddr DDRB
|
||||
#define CYRF_CSN_output CYRF_CSN_ddr |= _BV(CYRF_CSN_pin)
|
||||
#define CYRF_CSN_on CYRF_CSN_port |= _BV(CYRF_CSN_pin)
|
||||
#define CYRF_CSN_off CYRF_CSN_port &= ~_BV(CYRF_CSN_pin)
|
||||
|
||||
#define CYRF_RST_pin 5 //A5 = PC5
|
||||
#define CYRF_RST_port PORTC
|
||||
#define CYRF_RST_ddr DDRC
|
||||
#define CYRF_RST_output CYRF_RST_ddr |= _BV(CYRF_RST_pin)
|
||||
#define CYRF_RST_HI CYRF_RST_port |= _BV(CYRF_RST_pin)
|
||||
#define CYRF_RST_LO CYRF_RST_port &= ~_BV(CYRF_RST_pin)
|
||||
#endif
|
||||
|
||||
//RF Switch
|
||||
#ifdef XMEGA
|
||||
#define PE1_on
|
||||
#define PE1_off
|
||||
#define PE2_on
|
||||
#define PE2_off
|
||||
#else
|
||||
#define PE1_pin 1 //A1 = PC1
|
||||
#define PE1_port PORTC
|
||||
#define PE1_ddr DDRC
|
||||
#define PE1_output PE1_ddr |= _BV(PE1_pin)
|
||||
#define PE1_on PE1_port |= _BV(PE1_pin)
|
||||
#define PE1_off PE1_port &= ~_BV(PE1_pin)
|
||||
|
||||
#define PE2_pin 2 //A2 = PC2
|
||||
#define PE2_port PORTC
|
||||
#define PE2_ddr DDRC
|
||||
#define PE2_output PE2_ddr |= _BV(PE2_pin)
|
||||
#define PE2_on PE2_port |= _BV(PE2_pin)
|
||||
#define PE2_off PE2_port &= ~_BV(PE2_pin)
|
||||
#endif
|
||||
|
||||
// LED
|
||||
#ifdef XMEGA
|
||||
#define LED_pin 1 //PD1
|
||||
#define LED_port PORTD
|
||||
#define LED_ddr DDRD
|
||||
#define LED_on LED_port.OUTCLR = _BV(LED_pin)
|
||||
#define LED_off LED_port.OUTSET = _BV(LED_pin)
|
||||
#define LED_toggle LED_port.OUTTGL = _BV(LED_pin)
|
||||
#define LED_output LED_port.DIRSET = _BV(LED_pin)
|
||||
#define IS_LED_on (LED_port.OUT & _BV(LED_pin))
|
||||
#else
|
||||
#define LED_pin 5 //D13 = PB5
|
||||
#define LED_port PORTB
|
||||
#define LED_ddr DDRB
|
||||
#define LED_on LED_port |= _BV(LED_pin)
|
||||
#define LED_off LED_port &= ~_BV(LED_pin)
|
||||
#define LED_toggle LED_port ^= _BV(LED_pin)
|
||||
#define LED_output LED_ddr |= _BV(LED_pin)
|
||||
#define IS_LED_on (LED_port & _BV(LED_pin))
|
||||
#endif
|
||||
|
||||
//BIND
|
||||
#ifdef XMEGA
|
||||
#define BIND_pin 2 //PD2
|
||||
#define BIND_port PORTD
|
||||
#define IS_BIND_BUTTON_on ( (BIND_port.IN & _BV(BIND_pin)) == 0x00 )
|
||||
#else
|
||||
#define BIND_pin 5 //D13 = PB5
|
||||
#define BIND_port PORTB
|
||||
#define BIND_ipr PINB
|
||||
#define BIND_ddr DDRB
|
||||
#define BIND_SET_INPUT BIND_ddr &= ~_BV(BIND_pin)
|
||||
#define BIND_SET_OUTPUT BIND_ddr |= _BV(BIND_pin)
|
||||
#define BIND_SET_PULLUP BIND_port |= _BV(BIND_pin)
|
||||
#define IS_BIND_BUTTON_on ( (BIND_ipr & _BV(BIND_pin)) == 0x00 )
|
||||
#define EE_ADDR uint8_t*
|
||||
#endif
|
||||
|
||||
@ -15,7 +15,81 @@
|
||||
/********************/
|
||||
/** SPI routines **/
|
||||
/********************/
|
||||
#ifdef XMEGA
|
||||
#ifdef STM32_BOARD
|
||||
|
||||
SPIClass SPI_2(2); //Create an instance of the SPI Class called SPI_2 that uses the 2nd SPI Port
|
||||
|
||||
void initSPI2()
|
||||
{
|
||||
//SPI_DISABLE();
|
||||
SPI_2.end();
|
||||
SPI2_BASE->CR1 &= ~SPI_CR1_DFF_8_BIT; //8 bits format This bit should be written only when SPI is disabled (SPE = ?0?) for correct operation.
|
||||
SPI_2.begin(); //Initialize the SPI_2 port.
|
||||
|
||||
SPI_2.setBitOrder(MSBFIRST); // Set the SPI_2 bit order
|
||||
SPI_2.setDataMode(SPI_MODE0); // Set the SPI_2 data mode 0
|
||||
SPI_2.setClockDivider(SPI_CLOCK_DIV8); // Set the speed (36 / 8 = 4.5 MHz SPI_2 speed)
|
||||
}
|
||||
|
||||
void SPI_Write(uint8_t command)
|
||||
{//working OK
|
||||
SPI2_BASE->DR = command; //Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag).
|
||||
while (!(SPI2_BASE->SR & SPI_SR_RXNE));
|
||||
command = SPI2_BASE->DR; // ... and read the last received data.
|
||||
}
|
||||
|
||||
uint8_t SPI_Read(void)
|
||||
{
|
||||
SPI_Write(0x00);
|
||||
return SPI2_BASE->DR;
|
||||
}
|
||||
|
||||
uint8_t SPI_SDI_Read()
|
||||
{
|
||||
uint8_t rx=0;
|
||||
cli(); //Fix Hubsan droputs??
|
||||
while(!(SPI2_BASE->SR & SPI_SR_TXE));
|
||||
while((SPI2_BASE->SR & SPI_SR_BSY));
|
||||
//
|
||||
SPI_DISABLE();
|
||||
SPI_SET_BIDIRECTIONAL();
|
||||
volatile uint8_t x = SPI2_BASE->DR;
|
||||
(void)x;
|
||||
SPI_ENABLE();
|
||||
//
|
||||
SPI_DISABLE();
|
||||
while(!(SPI2_BASE->SR& SPI_SR_RXNE));
|
||||
rx=SPI2_BASE->DR;
|
||||
SPI_SET_UNIDIRECTIONAL();
|
||||
SPI_ENABLE();
|
||||
sei();//fix Hubsan dropouts??
|
||||
return rx;
|
||||
}
|
||||
|
||||
void SPI_ENABLE()
|
||||
{
|
||||
SPI2_BASE->CR1 |= SPI_CR1_SPE;
|
||||
}
|
||||
|
||||
void SPI_DISABLE()
|
||||
{
|
||||
SPI2_BASE->CR1 &= ~SPI_CR1_SPE;
|
||||
}
|
||||
|
||||
void SPI_SET_BIDIRECTIONAL()
|
||||
{
|
||||
SPI2_BASE->CR1 |= SPI_CR1_BIDIMODE;
|
||||
SPI2_BASE->CR1 &= ~ SPI_CR1_BIDIOE;//receive only
|
||||
}
|
||||
|
||||
void SPI_SET_UNIDIRECTIONAL()
|
||||
{
|
||||
SPI2_BASE->CR1 &= ~SPI_CR1_BIDIMODE;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#ifdef ORANGE_TX
|
||||
#define XNOP() NOP()
|
||||
#else
|
||||
#define XNOP()
|
||||
@ -67,7 +141,7 @@ uint8_t SPI_Read(void)
|
||||
}
|
||||
|
||||
#ifdef A7105_INSTALLED
|
||||
uint8_t SPI_SDIO_Read(void)
|
||||
uint8_t SPI_SDI_Read(void)
|
||||
{
|
||||
uint8_t result=0;
|
||||
SDI_input;
|
||||
@ -84,3 +158,5 @@ uint8_t SPI_SDIO_Read(void)
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif//STM32_BOARD
|
||||
@ -51,199 +51,151 @@
|
||||
|
||||
//Channel definitions
|
||||
#ifdef AETR
|
||||
enum {
|
||||
AILERON =0,
|
||||
ELEVATOR,
|
||||
THROTTLE,
|
||||
RUDDER,
|
||||
};
|
||||
#define AILERON 0
|
||||
#define ELEVATOR 1
|
||||
#define THROTTLE 2
|
||||
#define RUDDER 3
|
||||
#endif
|
||||
#ifdef AERT
|
||||
enum {
|
||||
AILERON =0,
|
||||
ELEVATOR,
|
||||
RUDDER,
|
||||
THROTTLE,
|
||||
};
|
||||
#define AILERON 0
|
||||
#define ELEVATOR 1
|
||||
#define THROTTLE 3
|
||||
#define RUDDER 2
|
||||
#endif
|
||||
#ifdef ARET
|
||||
enum {
|
||||
AILERON =0,
|
||||
RUDDER,
|
||||
ELEVATOR,
|
||||
THROTTLE,
|
||||
};
|
||||
#define AILERON 0
|
||||
#define ELEVATOR 2
|
||||
#define THROTTLE 3
|
||||
#define RUDDER 1
|
||||
#endif
|
||||
#ifdef ARTE
|
||||
enum {
|
||||
AILERON =0,
|
||||
RUDDER,
|
||||
THROTTLE,
|
||||
ELEVATOR,
|
||||
};
|
||||
#define AILERON 0
|
||||
#define ELEVATOR 3
|
||||
#define THROTTLE 2
|
||||
#define RUDDER 1
|
||||
#endif
|
||||
#ifdef ATRE
|
||||
enum {
|
||||
AILERON =0,
|
||||
THROTTLE,
|
||||
RUDDER,
|
||||
ELEVATOR,
|
||||
};
|
||||
#define AILERON 0
|
||||
#define ELEVATOR 3
|
||||
#define THROTTLE 1
|
||||
#define RUDDER 2
|
||||
#endif
|
||||
#ifdef ATER
|
||||
enum {
|
||||
AILERON =0,
|
||||
THROTTLE,
|
||||
ELEVATOR,
|
||||
RUDDER,
|
||||
};
|
||||
#define AILERON 0
|
||||
#define ELEVATOR 2
|
||||
#define THROTTLE 1
|
||||
#define RUDDER 3
|
||||
#endif
|
||||
|
||||
#ifdef EATR
|
||||
enum {
|
||||
ELEVATOR =0,
|
||||
AILERON,
|
||||
THROTTLE,
|
||||
RUDDER,
|
||||
};
|
||||
#define AILERON 1
|
||||
#define ELEVATOR 0
|
||||
#define THROTTLE 2
|
||||
#define RUDDER 3
|
||||
#endif
|
||||
#ifdef EART
|
||||
enum {
|
||||
ELEVATOR =0,
|
||||
AILERON,
|
||||
RUDDER,
|
||||
THROTTLE,
|
||||
};
|
||||
#define AILERON 1
|
||||
#define ELEVATOR 0
|
||||
#define THROTTLE 3
|
||||
#define RUDDER 2
|
||||
#endif
|
||||
#ifdef ERAT
|
||||
enum {
|
||||
ELEVATOR =0,
|
||||
RUDDER,
|
||||
AILERON,
|
||||
THROTTLE,
|
||||
};
|
||||
#define AILERON 2
|
||||
#define ELEVATOR 0
|
||||
#define THROTTLE 3
|
||||
#define RUDDER 1
|
||||
#endif
|
||||
#ifdef ERTA
|
||||
enum {
|
||||
ELEVATOR =0,
|
||||
RUDDER,
|
||||
THROTTLE,
|
||||
AILERON,
|
||||
};
|
||||
#define AILERON 3
|
||||
#define ELEVATOR 0
|
||||
#define THROTTLE 2
|
||||
#define RUDDER 1
|
||||
#endif
|
||||
#ifdef ETRA
|
||||
enum {
|
||||
ELEVATOR =0,
|
||||
THROTTLE,
|
||||
RUDDER,
|
||||
AILERON,
|
||||
};
|
||||
#define AILERON 3
|
||||
#define ELEVATOR 0
|
||||
#define THROTTLE 1
|
||||
#define RUDDER 2
|
||||
#endif
|
||||
#ifdef ETAR
|
||||
enum {
|
||||
ELEVATOR =0,
|
||||
THROTTLE,
|
||||
AILERON,
|
||||
RUDDER,
|
||||
};
|
||||
#define AILERON 2
|
||||
#define ELEVATOR 0
|
||||
#define THROTTLE 1
|
||||
#define RUDDER 3
|
||||
#endif
|
||||
|
||||
#ifdef TEAR
|
||||
enum {
|
||||
THROTTLE =0,
|
||||
ELEVATOR,
|
||||
AILERON,
|
||||
RUDDER,
|
||||
};
|
||||
#define AILERON 2
|
||||
#define ELEVATOR 1
|
||||
#define THROTTLE 0
|
||||
#define RUDDER 3
|
||||
#endif
|
||||
#ifdef TERA
|
||||
enum {
|
||||
THROTTLE =0,
|
||||
ELEVATOR,
|
||||
RUDDER,
|
||||
AILERON,
|
||||
};
|
||||
#define AILERON 3
|
||||
#define ELEVATOR 1
|
||||
#define THROTTLE 0
|
||||
#define RUDDER 2
|
||||
#endif
|
||||
#ifdef TREA
|
||||
enum {
|
||||
THROTTLE =0,
|
||||
RUDDER,
|
||||
ELEVATOR,
|
||||
AILERON,
|
||||
};
|
||||
#define AILERON 3
|
||||
#define ELEVATOR 2
|
||||
#define THROTTLE 0
|
||||
#define RUDDER 1
|
||||
#endif
|
||||
#ifdef TRAE
|
||||
enum {
|
||||
THROTTLE =0,
|
||||
RUDDER,
|
||||
AILERON,
|
||||
ELEVATOR,
|
||||
};
|
||||
#define AILERON 2
|
||||
#define ELEVATOR 3
|
||||
#define THROTTLE 0
|
||||
#define RUDDER 1
|
||||
#endif
|
||||
#ifdef TARE
|
||||
enum {
|
||||
THROTTLE =0,
|
||||
AILERON,
|
||||
RUDDER,
|
||||
ELEVATOR,
|
||||
};
|
||||
#define AILERON 1
|
||||
#define ELEVATOR 3
|
||||
#define THROTTLE 0
|
||||
#define RUDDER 2
|
||||
#endif
|
||||
#ifdef TAER
|
||||
enum {
|
||||
THROTTLE =0,
|
||||
AILERON,
|
||||
ELEVATOR,
|
||||
RUDDER,
|
||||
};
|
||||
#define AILERON 1
|
||||
#define ELEVATOR 2
|
||||
#define THROTTLE 0
|
||||
#define RUDDER 3
|
||||
#endif
|
||||
|
||||
#ifdef RETA
|
||||
enum {
|
||||
RUDDER =0,
|
||||
ELEVATOR,
|
||||
THROTTLE,
|
||||
AILERON,
|
||||
};
|
||||
#define AILERON 3
|
||||
#define ELEVATOR 1
|
||||
#define THROTTLE 2
|
||||
#define RUDDER 0
|
||||
#endif
|
||||
#ifdef REAT
|
||||
enum {
|
||||
RUDDER =0,
|
||||
ELEVATOR,
|
||||
AILERON,
|
||||
THROTTLE,
|
||||
};
|
||||
#define AILERON 2
|
||||
#define ELEVATOR 1
|
||||
#define THROTTLE 3
|
||||
#define RUDDER 0
|
||||
#endif
|
||||
#ifdef RAET
|
||||
enum {
|
||||
RUDDER =0,
|
||||
AILERON,
|
||||
ELEVATOR,
|
||||
THROTTLE,
|
||||
};
|
||||
#define AILERON 1
|
||||
#define ELEVATOR 2
|
||||
#define THROTTLE 3
|
||||
#define RUDDER 0
|
||||
#endif
|
||||
#ifdef RATE
|
||||
enum {
|
||||
RUDDER =0,
|
||||
AILERON,
|
||||
THROTTLE,
|
||||
ELEVATOR,
|
||||
};
|
||||
#define AILERON 1
|
||||
#define ELEVATOR 3
|
||||
#define THROTTLE 2
|
||||
#define RUDDER 0
|
||||
#endif
|
||||
#ifdef RTAE
|
||||
enum {
|
||||
RUDDER =0,
|
||||
THROTTLE,
|
||||
AILERON,
|
||||
ELEVATOR,
|
||||
};
|
||||
#define AILERON 2
|
||||
#define ELEVATOR 3
|
||||
#define THROTTLE 1
|
||||
#define RUDDER 0
|
||||
#endif
|
||||
#ifdef RTEA
|
||||
enum {
|
||||
RUDDER =0,
|
||||
THROTTLE,
|
||||
ELEVATOR,
|
||||
AILERON,
|
||||
};
|
||||
#define AILERON 3
|
||||
#define ELEVATOR 2
|
||||
#define THROTTLE 1
|
||||
#define RUDDER 0
|
||||
#endif
|
||||
|
||||
#define AUX1 4
|
||||
|
||||
@ -37,7 +37,7 @@
|
||||
#define MAX_PKTX 10
|
||||
uint8_t pktx[MAX_PKTX];
|
||||
uint8_t pktx1[MAX_PKTX];
|
||||
uint8_t index;
|
||||
uint8_t indx;
|
||||
uint8_t frame[18];
|
||||
|
||||
#ifdef BASH_SERIAL
|
||||
@ -93,6 +93,7 @@ void frsky_check_telemetry(uint8_t *pkt,uint8_t len)
|
||||
for (uint8_t i=3;i<len;i++)
|
||||
pktt[i]=pkt[i];
|
||||
telemetry_link=1;
|
||||
telemetry_lost=0;
|
||||
if(pktt[6])
|
||||
telemetry_counter=(telemetry_counter+1)%32;
|
||||
//
|
||||
@ -171,28 +172,28 @@ void frsky_user_frame()
|
||||
pass=1;
|
||||
|
||||
case 1:
|
||||
index=indexx;
|
||||
indx=indexx;
|
||||
prev_index = indexx;
|
||||
if(index<USER_MAX_BYTES)
|
||||
if(indx<USER_MAX_BYTES)
|
||||
{
|
||||
for(i=0;i<index;i++)
|
||||
for(i=0;i<indx;i++)
|
||||
frame[i+3]=pktx[i];
|
||||
pktt[6]=0;
|
||||
pass=0;
|
||||
}
|
||||
else
|
||||
{
|
||||
index = USER_MAX_BYTES;
|
||||
for(i=0;i<index;i++)
|
||||
indx = USER_MAX_BYTES;
|
||||
for(i=0;i<indx;i++)
|
||||
frame[i+3]=pktx[i];
|
||||
pass=2;
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
index = prev_index - index;
|
||||
indx = prev_index - indx;
|
||||
prev_index=0;
|
||||
if(index<=(MAX_PKTX-USER_MAX_BYTES)) //10-6=4
|
||||
for(i=0;i<index;i++)
|
||||
if(indx<=(MAX_PKTX-USER_MAX_BYTES)) //10-6=4
|
||||
for(i=0;i<indx;i++)
|
||||
frame[i+3]=pktx[USER_MAX_BYTES+i];
|
||||
pass=0;
|
||||
pktt[6]=0;
|
||||
@ -200,9 +201,9 @@ void frsky_user_frame()
|
||||
default:
|
||||
break;
|
||||
}
|
||||
if(!index)
|
||||
if(!indx)
|
||||
return;
|
||||
frame[1] = index;
|
||||
frame[1] = indx;
|
||||
frskySendStuffed();
|
||||
}
|
||||
else
|
||||
@ -310,7 +311,11 @@ void sportSendFrame()
|
||||
{
|
||||
uint8_t i;
|
||||
sport_counter = (sport_counter + 1) %36;
|
||||
|
||||
if(telemetry_lost)
|
||||
{
|
||||
sportIdle();
|
||||
return;
|
||||
}
|
||||
if(sport_counter<6)
|
||||
{
|
||||
frame[0] = 0x98;
|
||||
@ -361,30 +366,30 @@ void proces_sport_data(uint8_t data)
|
||||
case 0:
|
||||
if (data == START_STOP)
|
||||
{//waiting for 0x7e
|
||||
index = 0;
|
||||
indx = 0;
|
||||
pass = 1;
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
if (data == START_STOP) // Happens if missed packet
|
||||
{//waiting for 0x7e
|
||||
index = 0;
|
||||
indx = 0;
|
||||
pass = 1;
|
||||
break;
|
||||
}
|
||||
if(data == BYTESTUFF)//if they are stuffed
|
||||
pass=2;
|
||||
else
|
||||
if (index < MAX_PKTX)
|
||||
pktx[index++] = data;
|
||||
if (indx < MAX_PKTX)
|
||||
pktx[indx++] = data;
|
||||
break;
|
||||
case 2:
|
||||
if (index < MAX_PKTX)
|
||||
pktx[index++] = data ^ STUFF_MASK; //unstuff bytes
|
||||
if (indx < MAX_PKTX)
|
||||
pktx[indx++] = data ^ STUFF_MASK; //unstuff bytes
|
||||
pass=1;
|
||||
break;
|
||||
} // end switch
|
||||
if (index >= FRSKY_SPORT_PACKET_SIZE)
|
||||
if (indx >= FRSKY_SPORT_PACKET_SIZE)
|
||||
{//8 bytes no crc
|
||||
if ( sport )
|
||||
{
|
||||
@ -407,93 +412,92 @@ void proces_sport_data(uint8_t data)
|
||||
|
||||
void TelemetryUpdate()
|
||||
{
|
||||
#if defined SPORT_TELEMETRY
|
||||
if (protocol==MODE_FRSKYX)
|
||||
{ // FrSkyX
|
||||
if(telemetry_link)
|
||||
{
|
||||
if(pktt[4] & 0x80)
|
||||
rssi=pktt[4] & 0x7F ;
|
||||
else
|
||||
RxBt = (pktt[4]<<1) + 1 ;
|
||||
for (uint8_t i=0; i < pktt[6]; i++)
|
||||
proces_sport_data(pktt[7+i]);
|
||||
telemetry_link=0;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
// check for space in tx buffer
|
||||
|
||||
#ifdef BASH_SERIAL
|
||||
uint8_t h ;
|
||||
uint8_t t ;
|
||||
h = SerialControl.head ;
|
||||
t = SerialControl.tail ;
|
||||
if ( h >= t )
|
||||
{
|
||||
t += 64 - h ;
|
||||
}
|
||||
else
|
||||
{
|
||||
t -= h ;
|
||||
}
|
||||
if ( t < 32 )
|
||||
{
|
||||
return ;
|
||||
}
|
||||
|
||||
#else
|
||||
uint8_t h ;
|
||||
uint8_t t ;
|
||||
h = tx_head ;
|
||||
t = tx_tail ;
|
||||
if ( h >= t )
|
||||
{
|
||||
t += TXBUFFER_SIZE - h ;
|
||||
}
|
||||
else
|
||||
{
|
||||
t -= h ;
|
||||
}
|
||||
if ( t < 16 )
|
||||
{
|
||||
return ;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined DSM_TELEMETRY
|
||||
if(telemetry_link && protocol == MODE_DSM )
|
||||
{ // DSM
|
||||
DSM_frame();
|
||||
telemetry_link=0;
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
if(telemetry_link && protocol != MODE_FRSKYX )
|
||||
{ // FrSky + Hubsan
|
||||
frsky_link_frame();
|
||||
telemetry_link=0;
|
||||
return;
|
||||
}
|
||||
#if defined HUB_TELEMETRY
|
||||
if(!telemetry_link && protocol == MODE_FRSKYD)
|
||||
{ // FrSky
|
||||
frsky_user_frame();
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
#if defined SPORT_TELEMETRY
|
||||
if (protocol==MODE_FRSKYX)
|
||||
{ // FrSkyX
|
||||
uint32_t now = micros();
|
||||
if ((now - last) > SPORT_TIME)
|
||||
#ifdef BASH_SERIAL
|
||||
uint8_t h ;
|
||||
uint8_t t ;
|
||||
h = SerialControl.head ;
|
||||
t = SerialControl.tail ;
|
||||
if ( h >= t )
|
||||
{
|
||||
sportSendFrame();
|
||||
last += SPORT_TIME ;
|
||||
t += 64 - h ;
|
||||
}
|
||||
else
|
||||
{
|
||||
t -= h ;
|
||||
}
|
||||
if ( t < 32 )
|
||||
{
|
||||
return ;
|
||||
}
|
||||
|
||||
#else
|
||||
uint8_t h ;
|
||||
uint8_t t ;
|
||||
h = tx_head ;
|
||||
t = tx_tail ;
|
||||
if ( h >= t )
|
||||
{
|
||||
t += TXBUFFER_SIZE - h ;
|
||||
}
|
||||
else
|
||||
{
|
||||
t -= h ;
|
||||
}
|
||||
if ( t < 16 )
|
||||
{
|
||||
return ;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined SPORT_TELEMETRY
|
||||
if (protocol==MODE_FRSKYX)
|
||||
{ // FrSkyX
|
||||
if(telemetry_link)
|
||||
{
|
||||
if(pktt[4] & 0x80)
|
||||
rssi=pktt[4] & 0x7F ;
|
||||
else
|
||||
RxBt = (pktt[4]<<1) + 1 ;
|
||||
if(pktt[6]<=6)
|
||||
for (uint8_t i=0; i < pktt[6]; i++)
|
||||
proces_sport_data(pktt[7+i]);
|
||||
telemetry_link=0;
|
||||
}
|
||||
uint32_t now = micros();
|
||||
if ((now - last) > SPORT_TIME)
|
||||
{
|
||||
sportSendFrame();
|
||||
#ifdef STM32_BOARD
|
||||
last=now;
|
||||
#else
|
||||
last += SPORT_TIME ;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined DSM_TELEMETRY
|
||||
if(telemetry_link && protocol == MODE_DSM )
|
||||
{ // DSM
|
||||
DSM_frame();
|
||||
telemetry_link=0;
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
if(telemetry_link && protocol != MODE_FRSKYX )
|
||||
{ // FrSky + Hubsan
|
||||
frsky_link_frame();
|
||||
telemetry_link=0;
|
||||
return;
|
||||
}
|
||||
#if defined HUB_TELEMETRY
|
||||
if(!telemetry_link && protocol == MODE_FRSKYD)
|
||||
{ // FrSky
|
||||
frsky_user_frame();
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
@ -504,93 +508,133 @@ void TelemetryUpdate()
|
||||
/**************************/
|
||||
|
||||
#ifndef BASH_SERIAL
|
||||
// Routines for normal serial output
|
||||
void Serial_write(uint8_t data)
|
||||
{
|
||||
uint8_t nextHead ;
|
||||
nextHead = tx_head + 1 ;
|
||||
if ( nextHead >= TXBUFFER_SIZE )
|
||||
nextHead = 0 ;
|
||||
tx_buff[nextHead]=data;
|
||||
tx_head = nextHead ;
|
||||
tx_resume();
|
||||
}
|
||||
|
||||
void initTXSerial( uint8_t speed)
|
||||
{
|
||||
#ifdef ENABLE_PPM
|
||||
if(speed==SPEED_9600)
|
||||
{ // 9600
|
||||
#ifdef XMEGA
|
||||
USARTC0.BAUDCTRLA = 207 ;
|
||||
USARTC0.BAUDCTRLB = 0 ;
|
||||
USARTC0.CTRLB = 0x18 ;
|
||||
USARTC0.CTRLA = (USARTC0.CTRLA & 0xCF) | 0x10 ;
|
||||
USARTC0.CTRLC = 0x03 ;
|
||||
#else
|
||||
//9600 bauds
|
||||
UBRR0H = 0x00;
|
||||
UBRR0L = 0x67;
|
||||
UCSR0A = 0 ; // Clear X2 bit
|
||||
//Set frame format to 8 data bits, none, 1 stop bit
|
||||
UCSR0C = (1<<UCSZ01)|(1<<UCSZ00);
|
||||
#endif
|
||||
}
|
||||
else if(speed==SPEED_57600)
|
||||
{ // 57600
|
||||
#ifdef XMEGA
|
||||
/*USARTC0.BAUDCTRLA = 207 ;
|
||||
USARTC0.BAUDCTRLB = 0 ;
|
||||
USARTC0.CTRLB = 0x18 ;
|
||||
USARTC0.CTRLA = (USARTC0.CTRLA & 0xCF) | 0x10 ;
|
||||
USARTC0.CTRLC = 0x03 ;*/
|
||||
#else
|
||||
//57600 bauds
|
||||
UBRR0H = 0x00;
|
||||
UBRR0L = 0x22;
|
||||
UCSR0A = 0x02 ; // Set X2 bit
|
||||
//Set frame format to 8 data bits, none, 1 stop bit
|
||||
UCSR0C = (1<<UCSZ01)|(1<<UCSZ00);
|
||||
#endif
|
||||
}
|
||||
else if(speed==SPEED_125K)
|
||||
{ // 125000
|
||||
#ifdef XMEGA
|
||||
/*USARTC0.BAUDCTRLA = 207 ;
|
||||
USARTC0.BAUDCTRLB = 0 ;
|
||||
USARTC0.CTRLB = 0x18 ;
|
||||
USARTC0.CTRLA = (USARTC0.CTRLA & 0xCF) | 0x10 ;
|
||||
USARTC0.CTRLC = 0x03 ;*/
|
||||
#else
|
||||
//125000 bauds
|
||||
UBRR0H = 0x00;
|
||||
UBRR0L = 0x07;
|
||||
UCSR0A = 0x00 ; // Clear X2 bit
|
||||
//Set frame format to 8 data bits, none, 1 stop bit
|
||||
UCSR0C = (1<<UCSZ01)|(1<<UCSZ00);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
#ifndef XMEGA
|
||||
UCSR0B |= (1<<TXEN0);//tx enable
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef XMEGA
|
||||
ISR(USARTC0_DRE_vect)
|
||||
#else
|
||||
ISR(USART_UDRE_vect)
|
||||
#endif
|
||||
{ // Transmit interrupt
|
||||
if(tx_head!=tx_tail)
|
||||
// Routines for normal serial output
|
||||
void Serial_write(uint8_t data)
|
||||
{
|
||||
if(++tx_tail>=TXBUFFER_SIZE)//head
|
||||
tx_tail=0;
|
||||
UDR0=tx_buff[tx_tail];
|
||||
uint8_t nextHead ;
|
||||
nextHead = tx_head + 1 ;
|
||||
if ( nextHead >= TXBUFFER_SIZE )
|
||||
nextHead = 0 ;
|
||||
tx_buff[nextHead]=data;
|
||||
tx_head = nextHead ;
|
||||
tx_resume();
|
||||
}
|
||||
if (tx_tail == tx_head)
|
||||
tx_pause(); // Check if all data is transmitted . if yes disable transmitter UDRE interrupt
|
||||
}
|
||||
|
||||
void initTXSerial( uint8_t speed)
|
||||
{
|
||||
#ifdef ENABLE_PPM
|
||||
if(speed==SPEED_9600)
|
||||
{ // 9600
|
||||
#ifdef ORANGE_TX
|
||||
USARTC0.BAUDCTRLA = 207 ;
|
||||
USARTC0.BAUDCTRLB = 0 ;
|
||||
USARTC0.CTRLB = 0x18 ;
|
||||
USARTC0.CTRLA = (USARTC0.CTRLA & 0xCF) | 0x10 ;
|
||||
USARTC0.CTRLC = 0x03 ;
|
||||
#else
|
||||
#ifdef STM32_BOARD
|
||||
Serial2.begin(9600); //USART3
|
||||
USART3_BASE->CR1 &= ~ USART_CR1_RE; //disable RX leave TX enabled
|
||||
#else
|
||||
UBRR0H = 0x00;
|
||||
UBRR0L = 0x67;
|
||||
UCSR0A = 0 ; // Clear X2 bit
|
||||
//Set frame format to 8 data bits, none, 1 stop bit
|
||||
UCSR0C = (1<<UCSZ01)|(1<<UCSZ00);
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
else if(speed==SPEED_57600)
|
||||
{ // 57600
|
||||
#ifdef ORANGE_TX
|
||||
/*USARTC0.BAUDCTRLA = 207 ;
|
||||
USARTC0.BAUDCTRLB = 0 ;
|
||||
USARTC0.CTRLB = 0x18 ;
|
||||
USARTC0.CTRLA = (USARTC0.CTRLA & 0xCF) | 0x10 ;
|
||||
USARTC0.CTRLC = 0x03 ;*/
|
||||
#else
|
||||
#ifdef STM32_BOARD
|
||||
Serial2.begin(57600); //USART3
|
||||
USART3_BASE->CR1 &= ~ USART_CR1_RE; //disable RX leave TX enabled
|
||||
#else
|
||||
UBRR0H = 0x00;
|
||||
UBRR0L = 0x22;
|
||||
UCSR0A = 0x02 ; // Set X2 bit
|
||||
//Set frame format to 8 data bits, none, 1 stop bit
|
||||
UCSR0C = (1<<UCSZ01)|(1<<UCSZ00);
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
else if(speed==SPEED_125K)
|
||||
{ // 125000
|
||||
#ifdef ORANGE_TX
|
||||
/*USARTC0.BAUDCTRLA = 207 ;
|
||||
USARTC0.BAUDCTRLB = 0 ;
|
||||
USARTC0.CTRLB = 0x18 ;
|
||||
USARTC0.CTRLA = (USARTC0.CTRLA & 0xCF) | 0x10 ;
|
||||
USARTC0.CTRLC = 0x03 ;*/
|
||||
#else
|
||||
#ifdef STM32_BOARD
|
||||
Serial2.begin(125000); //USART3
|
||||
USART3_BASE->CR1 &= ~ USART_CR1_RE; //disable RX leave TX enabled
|
||||
#else
|
||||
UBRR0H = 0x00;
|
||||
UBRR0L = 0x07;
|
||||
UCSR0A = 0x00 ; // Clear X2 bit
|
||||
//Set frame format to 8 data bits, none, 1 stop bit
|
||||
UCSR0C = (1<<UCSZ01)|(1<<UCSZ00);
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
#ifndef ORANGE_TX
|
||||
#ifndef STM32_BOARD
|
||||
UCSR0B |= (1<<TXEN0);//tx enable
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
//Serial TX
|
||||
#ifdef ORANGE_TX
|
||||
ISR(USARTC0_DRE_vect)
|
||||
#else
|
||||
#ifdef STM32_BOARD
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void __irq_usart3()
|
||||
#else
|
||||
ISR(USART_UDRE_vect)
|
||||
#endif
|
||||
#endif
|
||||
{ // Transmit interrupt
|
||||
#ifdef STM32_BOARD
|
||||
if(USART3_BASE->SR & USART_SR_TXE)
|
||||
{
|
||||
#endif
|
||||
if(tx_head!=tx_tail)
|
||||
{
|
||||
if(++tx_tail>=TXBUFFER_SIZE)//head
|
||||
tx_tail=0;
|
||||
#ifdef STM32_BOARD
|
||||
USART3_BASE->DR=tx_buff[tx_tail];//clears TXE bit
|
||||
#else
|
||||
UDR0=tx_buff[tx_tail];
|
||||
#endif
|
||||
}
|
||||
if (tx_tail == tx_head)
|
||||
#ifdef STM32_BOARD
|
||||
USART3_BASE->CR1 &= ~USART_CR1_TXEIE;//disable interrupt
|
||||
}
|
||||
#else
|
||||
tx_pause(); // Check if all data is transmitted . if yes disable transmitter UDRE interrupt
|
||||
#endif
|
||||
}
|
||||
#if defined STM32_BOARD
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif //STM32_BOARD
|
||||
|
||||
#else //BASH_SERIAL
|
||||
// Routines for bit-bashed serial output
|
||||
|
||||
96
Multiprotocol/Validate.h
Normal file
96
Multiprotocol/Validate.h
Normal file
@ -0,0 +1,96 @@
|
||||
// Check selected board type
|
||||
#if defined (STM32_BOARD) && defined (ORANGE_TX)
|
||||
#error You must comment the board type STM32_BOARD in _Config.h to compile ORANGE_TX
|
||||
#endif
|
||||
#if not defined (ORANGE_TX) && not defined (STM32_BOARD)
|
||||
//Atmega328p
|
||||
#if not defined(ARDUINO_AVR_PRO) && not defined(ARDUINO_AVR_MINI) && not defined(ARDUINO_AVR_NANO)
|
||||
#error You must select the board type "Arduino Pro or Pro Mini" or "Arduino Mini"
|
||||
#endif
|
||||
#if F_CPU != 16000000L || not defined(__AVR_ATmega328P__)
|
||||
#error You must select the processor type "ATmega328(5V, 16MHz)"
|
||||
#endif
|
||||
#endif
|
||||
#if defined (STM32_BOARD) && not defined (ORANGE_TX)
|
||||
//STM32
|
||||
#ifndef ARDUINO_GENERIC_STM32F103C
|
||||
#error You must select the board type "Generic STM32F103C series"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
//Change/Force configuration if OrangeTX
|
||||
#ifdef ORANGE_TX
|
||||
#undef ENABLE_PPM // Disable PPM for OrangeTX module
|
||||
#undef A7105_INSTALLED // Disable A7105 for OrangeTX module
|
||||
#undef CC2500_INSTALLED // Disable CC2500 for OrangeTX module
|
||||
#undef NRF24L01_INSTALLED // Disable NRF for OrangeTX module
|
||||
#define TELEMETRY // Enable telemetry
|
||||
#define INVERT_TELEMETRY // Enable invert telemetry
|
||||
#define DSM_TELEMETRY // Enable DSM telemetry
|
||||
#endif
|
||||
|
||||
//Make sure protocols are selected correctly
|
||||
#ifndef A7105_INSTALLED
|
||||
#undef FLYSKY_A7105_INO
|
||||
#undef HUBSAN_A7105_INO
|
||||
#endif
|
||||
#ifndef CYRF6936_INSTALLED
|
||||
#undef DEVO_CYRF6936_INO
|
||||
#undef DSM_CYRF6936_INO
|
||||
#undef J6PRO_CYRF6936_INO
|
||||
#endif
|
||||
#ifndef CC2500_INSTALLED
|
||||
#undef FRSKYD_CC2500_INO
|
||||
#undef FRSKYV_CC2500_INO
|
||||
#undef FRSKYX_CC2500_INO
|
||||
#undef SFHSS_CC2500_INO
|
||||
#endif
|
||||
#ifndef NRF24L01_INSTALLED
|
||||
#undef BAYANG_NRF24L01_INO
|
||||
#undef CG023_NRF24L01_INO
|
||||
#undef CX10_NRF24L01_INO
|
||||
#undef ESKY_NRF24L01_INO
|
||||
#undef HISKY_NRF24L01_INO
|
||||
#undef KN_NRF24L01_INO
|
||||
#undef SLT_NRF24L01_INO
|
||||
#undef SYMAX_NRF24L01_INO
|
||||
#undef V2X2_NRF24L01_INO
|
||||
#undef YD717_NRF24L01_INO
|
||||
#undef MT99XX_NRF24L01_INO
|
||||
#undef MJXQ_NRF24L01_INO
|
||||
#undef SHENQI_NRF24L01_INO
|
||||
#undef FY326_NRF24L01_INO
|
||||
#undef FQ777_NRF24L01_INO
|
||||
#undef ASSAN_NRF24L01_INO
|
||||
#undef HONTAI_NRF24L01_INO
|
||||
#endif
|
||||
|
||||
//Make sure telemetry is selected correctly
|
||||
#ifndef TELEMETRY
|
||||
#undef INVERT_TELEMETRY
|
||||
#undef DSM_TELEMETRY
|
||||
#undef SPORT_TELEMETRY
|
||||
#undef HUB_TELEMETRY
|
||||
#else
|
||||
#if not defined(CYRF6936_INSTALLED) || not defined(DSM_CYRF6936_INO)
|
||||
#undef DSM_TELEMETRY
|
||||
#endif
|
||||
#if (not defined(CC2500_INSTALLED) || not defined(FRSKYD_CC2500_INO)) && (not defined(A7105_INSTALLED) || not defined(HUBSAN_A7105_INO))
|
||||
#undef HUB_TELEMETRY
|
||||
#endif
|
||||
#if not defined(CC2500_INSTALLED) || not defined(FRSKYX_CC2500_INO)
|
||||
#undef SPORT_TELEMETRY
|
||||
#endif
|
||||
#if not defined(DSM_TELEMETRY) && not defined(HUB_TELEMETRY) && not defined(SPORT_TELEMETRY)
|
||||
#undef TELEMETRY
|
||||
#undef INVERT_TELEMETRY
|
||||
#endif
|
||||
#endif
|
||||
|
||||
//Make sure TX is defined correctly
|
||||
#ifndef AILERON
|
||||
#error You must select a correct channel order.
|
||||
#endif
|
||||
#if not defined(PPM_MAX_100) || not defined(PPM_MIN_100) || not defined(PPM_MAX_125) || not defined(PPM_MIN_125)
|
||||
#error You must set correct TX end points.
|
||||
#endif
|
||||
@ -17,6 +17,14 @@
|
||||
/** Multiprotocol module configuration file ***/
|
||||
/**********************************************/
|
||||
|
||||
/********************/
|
||||
/*** BOARD TYPE ***/
|
||||
/********************/
|
||||
//Uncomment one of the line below if you have a different module not based on the original Multi Atmega328p design which includes the 4-in-1.
|
||||
//If you don't know then leave them commented.
|
||||
//#define STM32_BOARD
|
||||
|
||||
|
||||
/*******************/
|
||||
/*** TX SETTINGS ***/
|
||||
/*******************/
|
||||
@ -53,13 +61,13 @@
|
||||
//The protocols below need a CYRF6936 to be installed
|
||||
#define DEVO_CYRF6936_INO
|
||||
#define DSM_CYRF6936_INO
|
||||
#define J6PRO_CYRF6936_INO
|
||||
#define J6PRO_CYRF6936_INO
|
||||
|
||||
//The protocols below need a CC2500 to be installed
|
||||
#define FRSKYD_CC2500_INO
|
||||
#define FRSKYV_CC2500_INO
|
||||
#define FRSKYX_CC2500_INO
|
||||
#define SFHSS_CC2500_INO
|
||||
#define SFHSS_CC2500_INO
|
||||
|
||||
//The protocols below need a NRF24L01 to be installed
|
||||
#define BAYANG_NRF24L01_INO
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user