mirror of
https://github.com/pascallanger/DIY-Multiprotocol-TX-Module.git
synced 2025-02-09 22:38:10 +00:00
Protocol FrskyX D16 RX frequency auto-tune (#270)
* Add autotune during bind * Fix data phase
This commit is contained in:
goebish
pascallanger
parent
bed02c9384
commit
e038c49ae9
@ -17,10 +17,13 @@
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#include "iface_cc2500.h"
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#define FRSKYX_FCC_LENGTH 30+2
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#define FRSKYX_LBT_LENGTH 33+2
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#define FRSKYX_FCC_LENGTH (30+2)
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#define FRSKYX_LBT_LENGTH (33+2)
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enum {
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FRSKYX_RX_TUNE_START,
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FRSKYX_RX_TUNE_LOW,
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FRSKYX_RX_TUNE_HIGH,
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FRSKYX_RX_BIND,
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FRSKYX_RX_DATA,
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};
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@ -28,6 +31,14 @@
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static uint8_t frskyx_rx_chanskip;
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static uint8_t frskyx_rx_disable_lna;
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static uint8_t frskyx_rx_data_started;
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static int8_t frskyx_rx_finetune;
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static void __attribute__((unused)) frskyx_rx_strobe_rx()
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{
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CC2500_Strobe(CC2500_SIDLE);
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CC2500_Strobe(CC2500_SFRX);
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CC2500_Strobe(CC2500_SRX);
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}
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static void __attribute__((unused)) FrSkyX_Rx_initialise() {
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CC2500_Reset();
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@ -36,7 +47,7 @@ static void __attribute__((unused)) FrSkyX_Rx_initialise() {
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CC2500_WriteReg(CC2500_18_MCSM0, 0x18);
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CC2500_WriteReg(CC2500_07_PKTCTRL1, 0x04);
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CC2500_WriteReg(CC2500_3E_PATABLE, 0xFF);
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CC2500_WriteReg(CC2500_0C_FSCTRL0, option); // Frequency offset hack
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CC2500_WriteReg(CC2500_0C_FSCTRL0, 0);
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CC2500_WriteReg(CC2500_0D_FREQ2, 0x5C);
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CC2500_WriteReg(CC2500_13_MDMCFG1, 0x23);
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CC2500_WriteReg(CC2500_14_MDMCFG0, 0x7A);
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@ -88,9 +99,7 @@ static void __attribute__((unused)) FrSkyX_Rx_initialise() {
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frskyx_rx_disable_lna = IS_POWER_FLAG_on;
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CC2500_SetTxRxMode(frskyx_rx_disable_lna ? TXRX_OFF : RX_EN); // lna disable / enable
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CC2500_Strobe(CC2500_SIDLE);
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CC2500_Strobe(CC2500_SFRX);
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CC2500_Strobe(CC2500_SRX);
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frskyx_rx_strobe_rx();
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CC2500_WriteReg(CC2500_0A_CHANNR, 0); // bind channel
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delayMicroseconds(1000); // wait for RX to activate
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}
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@ -99,16 +108,12 @@ static void __attribute__((unused)) frskyx_rx_set_channel(uint8_t channel)
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{
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CC2500_WriteReg(CC2500_0A_CHANNR, hopping_frequency[channel]);
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CC2500_WriteReg(CC2500_25_FSCAL1, calData[channel]);
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CC2500_Strobe(CC2500_SIDLE);
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CC2500_Strobe(CC2500_SFRX);
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CC2500_Strobe(CC2500_SRX);
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frskyx_rx_strobe_rx();
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}
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static void __attribute__((unused)) frskyx_rx_calibrate()
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{
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CC2500_Strobe(CC2500_SIDLE);
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CC2500_Strobe(CC2500_SFRX);
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CC2500_Strobe(CC2500_SRX);
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frskyx_rx_strobe_rx();
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for (unsigned c = 0; c < 47; c++)
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{
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CC2500_Strobe(CC2500_SIDLE);
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@ -178,21 +183,27 @@ uint16_t initFrSkyX_Rx()
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frskyx_rx_chanskip = 1;
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hopping_frequency_no = 0;
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frskyx_rx_data_started = 0;
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frskyx_rx_finetune = 0;
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telemetry_link = 0;
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if (IS_BIND_IN_PROGRESS) {
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phase = FRSKYX_RX_BIND;
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phase = FRSKYX_RX_TUNE_START;
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}
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else {
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uint16_t temp = FRSKYX_RX_EEPROM_OFFSET;
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rx_tx_addr[0] = eeprom_read_byte(temp++);
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rx_tx_addr[1] = eeprom_read_byte(temp++);
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rx_tx_addr[2] = eeprom_read_byte(temp++);
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frskyx_rx_finetune = eeprom_read_byte(temp++);
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for(uint8_t ch = 0; ch < 47; ch++)
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hopping_frequency[ch] = eeprom_read_byte(temp++);
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frskyx_rx_calibrate();
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CC2500_WriteReg(CC2500_18_MCSM0, 0x08); // FS_AUTOCAL = manual
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CC2500_WriteReg(CC2500_09_ADDR, rx_tx_addr[0]); // set address
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CC2500_WriteReg(CC2500_07_PKTCTRL1, 0x05); // check address
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if (option == 0)
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CC2500_WriteReg(CC2500_0C_FSCTRL0, frskyx_rx_finetune);
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else
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CC2500_WriteReg(CC2500_0C_FSCTRL0, option);
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frskyx_rx_set_channel(hopping_frequency_no);
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phase = FRSKYX_RX_DATA;
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}
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@ -205,19 +216,81 @@ uint16_t FrSkyX_Rx_callback()
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static uint32_t pps_timer=0;
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static uint8_t pps_counter=0;
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static int8_t read_retry = 0;
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static int8_t tune_low, tune_high;
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uint8_t len, ch;
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if (prev_option != option)
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{
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CC2500_WriteReg(CC2500_0C_FSCTRL0, option); // Frequency offset hack
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if ((prev_option != option) && (phase >= FRSKYX_RX_DATA)) {
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if (option == 0)
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CC2500_WriteReg(CC2500_0C_FSCTRL0, frskyx_rx_finetune);
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else
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CC2500_WriteReg(CC2500_0C_FSCTRL0, option);
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prev_option = option;
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}
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if (frskyx_rx_disable_lna != IS_POWER_FLAG_on) {
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frskyx_rx_disable_lna = IS_POWER_FLAG_on;
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CC2500_SetTxRxMode(frskyx_rx_disable_lna ? TXRX_OFF : RX_EN);
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}
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len = CC2500_ReadReg(CC2500_3B_RXBYTES | CC2500_READ_BURST) & 0x7F;
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switch(phase) {
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case FRSKYX_RX_TUNE_START:
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if (len >= packet_length) {
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CC2500_ReadData(packet, packet_length);
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if(packet[1] == 0x03 && packet[2] == 0x01) {
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if(frskyx_rx_check_crc()) {
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frskyx_rx_finetune = -127;
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CC2500_WriteReg(CC2500_0C_FSCTRL0, frskyx_rx_finetune);
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phase = FRSKYX_RX_TUNE_LOW;
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frskyx_rx_strobe_rx();
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return 1000;
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}
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}
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}
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frskyx_rx_finetune += 10;
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CC2500_WriteReg(CC2500_0C_FSCTRL0, frskyx_rx_finetune);
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frskyx_rx_strobe_rx();
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return 18000;
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case FRSKYX_RX_TUNE_LOW:
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if (len >= packet_length) {
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CC2500_ReadData(packet, packet_length);
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if (frskyx_rx_check_crc()) {
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tune_low = frskyx_rx_finetune;
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frskyx_rx_finetune = 127;
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CC2500_WriteReg(CC2500_0C_FSCTRL0, frskyx_rx_finetune);
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phase = FRSKYX_RX_TUNE_HIGH;
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frskyx_rx_strobe_rx();
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return 1000;
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}
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}
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frskyx_rx_finetune += 1;
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CC2500_WriteReg(CC2500_0C_FSCTRL0, frskyx_rx_finetune);
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frskyx_rx_strobe_rx();
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return 18000;
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case FRSKYX_RX_TUNE_HIGH:
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if (len >= packet_length) {
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CC2500_ReadData(packet, packet_length);
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if (frskyx_rx_check_crc()) {
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tune_high = frskyx_rx_finetune;
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frskyx_rx_finetune = (tune_low + tune_high) / 2;
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CC2500_WriteReg(CC2500_0C_FSCTRL0, (int8_t)frskyx_rx_finetune);
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if(tune_low < tune_high)
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phase = FRSKYX_RX_BIND;
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else
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phase = FRSKYX_RX_TUNE_START;
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frskyx_rx_strobe_rx();
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return 1000;
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}
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}
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frskyx_rx_finetune -= 1;
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CC2500_WriteReg(CC2500_0C_FSCTRL0, frskyx_rx_finetune);
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frskyx_rx_strobe_rx();
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return 18000;
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case FRSKYX_RX_BIND:
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len = CC2500_ReadReg(CC2500_3B_RXBYTES | CC2500_READ_BURST) & 0x7F;
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if(len >= packet_length) {
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CC2500_ReadData(packet, packet_length);
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if (frskyx_rx_check_crc()) {
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@ -243,17 +316,16 @@ uint16_t FrSkyX_Rx_callback()
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eeprom_write_byte((EE_ADDR)temp++, rx_tx_addr[0]);
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eeprom_write_byte((EE_ADDR)temp++, rx_tx_addr[1]);
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eeprom_write_byte((EE_ADDR)temp++, rx_tx_addr[2]);
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eeprom_write_byte((EE_ADDR)temp++, frskyx_rx_finetune);
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for (ch = 0; ch < 47; ch++)
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eeprom_write_byte((EE_ADDR)temp++, hopping_frequency[ch]);
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BIND_DONE;
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}
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CC2500_Strobe(CC2500_SIDLE);
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CC2500_Strobe(CC2500_SFRX);
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CC2500_Strobe(CC2500_SRX);
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frskyx_rx_strobe_rx();
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}
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return 1000;
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case FRSKYX_RX_DATA:
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len = CC2500_ReadReg(CC2500_3B_RXBYTES | CC2500_READ_BURST) & 0x7F;
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if (len >= packet_length) {
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CC2500_ReadData(packet, packet_length);
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if (packet[1] == rx_tx_addr[0] && packet[2] == rx_tx_addr[1] && packet[6] == rx_tx_addr[2] && frskyx_rx_check_crc()) {
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@ -574,7 +574,7 @@ enum {
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#define AFHDS2A_EEPROM_OFFSET 50 // RX ID, 4 bytes per model id, end is 50+64=114
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#define BUGS_EEPROM_OFFSET 114 // RX ID, 2 bytes per model id, end is 114+32=146
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#define BUGSMINI_EEPROM_OFFSET 146 // RX ID, 2 bytes per model id, end is 146+32=178
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#define FRSKYX_RX_EEPROM_OFFSET 178 // (3) TX ID + (47) channels + (1) freq_tune, 51 bytes per model, end is 178+51=229
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#define FRSKYX_RX_EEPROM_OFFSET 178 // (3) TX ID + (1) freq_tune + (47) channels, 51 bytes per model, end is 178+51=229
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//#define CONFIG_EEPROM_OFFSET 210 // Current configuration of the multimodule
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//****************************************
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