Fix for module boot issue?

This commit is contained in:
Pascal Langer 2021-03-13 18:18:07 +01:00
parent 732e66cab2
commit dbc33951a4
4 changed files with 10 additions and 2 deletions

View File

@ -350,7 +350,7 @@ uint16_t HOTT_callback()
CC2500_Strobe(CC2500_SFRX);
//RX
if(packet[29] & 0xF8)
{// binary telemetry
{// Sync telemetry
CC2500_WriteReg(CC2500_04_SYNC1, 0x2C);
CC2500_WriteReg(CC2500_05_SYNC0, 0x6E);
}

View File

@ -19,7 +19,7 @@
#define VERSION_MAJOR 1
#define VERSION_MINOR 3
#define VERSION_REVISION 2
#define VERSION_PATCH_LEVEL 59
#define VERSION_PATCH_LEVEL 60
#define MODE_SERIAL 0

View File

@ -1676,6 +1676,7 @@ void modules_reset()
usart_config_gpios_async(USART2,GPIOA,PIN_MAP[PA3].gpio_bit,GPIOA,PIN_MAP[PA2].gpio_bit,config);
LED2_output;
usart_set_baud_rate(USART2, STM32_PCLK1, baud);
USART2_BASE->CR1 &= ~ USART_CR1_TE; // Disable transmit
usart_enable(USART2);
}
void usart3_begin(uint32_t baud,uint32_t config )
@ -1683,6 +1684,7 @@ void modules_reset()
usart_init(USART3);
usart_config_gpios_async(USART3,GPIOB,PIN_MAP[PB11].gpio_bit,GPIOB,PIN_MAP[PB10].gpio_bit,config);
usart_set_baud_rate(USART3, STM32_PCLK1, baud);
USART3_BASE->CR1 &= ~ USART_CR1_RE; // Disable receive
usart_enable(USART3);
}
void init_HWTimer()

View File

@ -1159,6 +1159,12 @@ void TelemetryUpdate()
}
#ifdef STM32_BOARD
}
else if(USART3_BASE->SR & USART_SR_RXNE)
{ //Should not get here...
uint8_t dummy = USART3_BASE->DR;
dummy++;
USART3_BASE->CR1 &= ~ USART_CR1_RE; // Disable receive
}
#endif
}
#else //BASH_SERIAL