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https://github.com/pascallanger/DIY-Multiprotocol-TX-Module.git
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Use CC2500 if available instead of NRF24L01 for E010 and PHOENIX sub protocols
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Goebish
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@ -78,6 +78,119 @@ const uint8_t PROGMEM E010_map_rfchan[][2] = {
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#define MJXQ_PAN_UP 0x04
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#define MJXQ_TILT_DOWN 0x20
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#define MJXQ_TILT_UP 0x10
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// if CC2500 is installed, use it for E010 format
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#ifdef CC2500_INSTALLED
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#include "iface_cc2500.h"
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extern uint8_t xn297_addr_len;
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extern uint8_t xn297_tx_addr[];
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extern const uint8_t xn297_scramble[];
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extern const uint16_t PROGMEM xn297_crc_xorout_scrambled[];
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static void __attribute__((unused)) XN297L_init()
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{
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PE1_off; // antenna RF2
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PE2_on;
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CC2500_Reset();
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CC2500_Strobe(CC2500_SIDLE);
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// Address Config = No address check
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// Base Frequency = 2400
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// CRC Autoflush = false
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// CRC Enable = false
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// Channel Spacing = 333.251953
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// Data Format = Normal mode
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// Data Rate = 249.939
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// Deviation = 126.953125
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// Device Address = 0
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// Manchester Enable = false
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// Modulated = true
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// Modulation Format = GFSK
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// Packet Length Mode = Variable packet length mode. Packet length configured by the first byte after sync word
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// RX Filter BW = 203.125000
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// Sync Word Qualifier Mode = No preamble/sync
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// TX Power = 0
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// Whitening = false
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CC2500_WriteReg(CC2500_08_PKTCTRL0, 0x01); // Packet Automation Control
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CC2500_WriteReg(CC2500_0B_FSCTRL1, 0x0A); // Frequency Synthesizer Control
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CC2500_WriteReg(CC2500_0C_FSCTRL0, 0x00); // Frequency Synthesizer Control
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CC2500_WriteReg(CC2500_0D_FREQ2, 0x5C); // Frequency Control Word, High Byte
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CC2500_WriteReg(CC2500_0E_FREQ1, 0x4E); // Frequency Control Word, Middle Byte
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CC2500_WriteReg(CC2500_0F_FREQ0, 0xC3); // Frequency Control Word, Low Byte
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CC2500_WriteReg(CC2500_10_MDMCFG4, 0x8D); // Modem Configuration
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CC2500_WriteReg(CC2500_11_MDMCFG3, 0x3B); // Modem Configuration
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CC2500_WriteReg(CC2500_12_MDMCFG2, 0x10); // Modem Configuration
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CC2500_WriteReg(CC2500_13_MDMCFG1, 0x23); // Modem Configuration
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CC2500_WriteReg(CC2500_14_MDMCFG0, 0xA4); // Modem Configuration
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CC2500_WriteReg(CC2500_15_DEVIATN, 0x62); // Modem Deviation Setting
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CC2500_WriteReg(CC2500_18_MCSM0, 0x18); // Main Radio Control State Machine Configuration
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CC2500_WriteReg(CC2500_19_FOCCFG, 0x1D); // Frequency Offset Compensation Configuration
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CC2500_WriteReg(CC2500_1A_BSCFG, 0x1C); // Bit Synchronization Configuration
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CC2500_WriteReg(CC2500_1B_AGCCTRL2, 0xC7); // AGC Control
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CC2500_WriteReg(CC2500_1C_AGCCTRL1, 0x00); // AGC Control
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CC2500_WriteReg(CC2500_1D_AGCCTRL0, 0xB0); // AGC Control
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CC2500_WriteReg(CC2500_21_FREND1, 0xB6); // Front End RX Configuration
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CC2500_WriteReg(CC2500_23_FSCAL3, 0xEA); // Frequency Synthesizer Calibration
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CC2500_WriteReg(CC2500_25_FSCAL1, 0x00); // Frequency Synthesizer Calibration
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CC2500_WriteReg(CC2500_26_FSCAL0, 0x11); // Frequency Synthesizer Calibration
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CC2500_SetTxRxMode(TX_EN);
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}
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static void __attribute__((unused)) XN297L_SetTXAddr(const uint8_t* addr, uint8_t len)
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{
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if (len > 5) len = 5;
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if (len < 3) len = 3;
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xn297_addr_len = len;
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memcpy(xn297_tx_addr, addr, len);
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}
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static void __attribute__((unused)) XN297L_WritePayload(const uint8_t* msg, uint8_t len)
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{
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uint8_t buf[32];
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uint8_t last = 0;
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uint8_t i;
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static const uint16_t initial = 0xb5d2;
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// address
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for (i = 0; i < xn297_addr_len; ++i) {
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buf[last++] = xn297_tx_addr[xn297_addr_len - i - 1] ^ xn297_scramble[i];
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}
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// payload
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for (i = 0; i < len; ++i) {
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// bit-reverse bytes in packet
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uint8_t b_out = bit_reverse(msg[i]);
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buf[last++] = b_out ^ xn297_scramble[xn297_addr_len + i];
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}
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uint8_t offset = xn297_addr_len < 4 ? 1 : 0;
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// crc
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uint16_t crc = initial;
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for (uint8_t i = offset; i < last; ++i)
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crc = crc16_update(crc, buf[i], 8);
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crc ^= xn297_crc_xorout_scrambled[xn297_addr_len - 3 + len];
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buf[last++] = crc >> 8;
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buf[last++] = crc & 0xff;
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// stop TX/RX
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CC2500_Strobe(CC2500_SIDLE);
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// flush tx FIFO
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CC2500_Strobe(CC2500_SFTX);
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// packet length
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CC2500_WriteReg(CC2500_3F_TXFIFO, last + 3);
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// xn297L preamble
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CC2500_WriteRegisterMulti(CC2500_3F_TXFIFO, (uint8_t*)"\x71\x0f\x55", 3);
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// xn297 packet
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CC2500_WriteRegisterMulti(CC2500_3F_TXFIFO, buf, last);
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// transmit
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CC2500_Strobe(CC2500_STX);
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}
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#endif // CC2500_INSTALLED
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static uint8_t __attribute__((unused)) MJXQ_pan_tilt_value()
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{
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// CH12_SW PAN // H26D
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@ -190,9 +303,27 @@ static void __attribute__((unused)) MJXQ_send_packet(uint8_t bind)
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uint8_t sum = packet[0];
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for (uint8_t i=1; i < MJXQ_PACKET_SIZE-1; i++) sum += packet[i];
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packet[15] = sum;
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NRF24L01_WriteReg(NRF24L01_05_RF_CH, hopping_frequency[hopping_frequency_no++ / 2]);
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hopping_frequency_no %= 2 * MJXQ_RF_NUM_CHANNELS; // channels repeated
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hopping_frequency_no++;
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#ifdef CC2500_INSTALLED
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if (sub_protocol == E010 || sub_protocol == PHOENIX) {
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// spacing is 333.25 kHz, must multiply xn297 channel by 3
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CC2500_WriteReg(CC2500_0A_CHANNR, hopping_frequency[hopping_frequency_no / 2] * 3);
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// Make sure that the radio is in IDLE state before flushing the FIFO
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CC2500_Strobe(CC2500_SIDLE);
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// Flush TX FIFO
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CC2500_Strobe(CC2500_SFTX);
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// Frequency offset hack
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if (prev_option != option) {
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prev_option = option;
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CC2500_WriteReg(CC2500_0C_FSCTRL0, option);
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}
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XN297L_WritePayload(packet, MJXQ_PACKET_SIZE);
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CC2500_SetPower();
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}
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else
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#endif
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{
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NRF24L01_WriteReg(NRF24L01_05_RF_CH, hopping_frequency[hopping_frequency_no / 2]);
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NRF24L01_WriteReg(NRF24L01_07_STATUS, 0x70);
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NRF24L01_FlushTx();
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@ -209,6 +340,8 @@ static void __attribute__((unused)) MJXQ_send_packet(uint8_t bind)
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XN297_WritePayload(packet, MJXQ_PACKET_SIZE);
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}
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NRF24L01_SetPower();
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}
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hopping_frequency_no %= 2 * MJXQ_RF_NUM_CHANNELS; // channels repeated
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}
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static void __attribute__((unused)) MJXQ_init()
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@ -225,7 +358,16 @@ static void __attribute__((unused)) MJXQ_init()
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memcpy(hopping_frequency, "\x0a\x35\x42\x3d", MJXQ_RF_NUM_CHANNELS);
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memcpy(addr, "\x6d\x6a\x73\x73\x73", MJXQ_ADDRESS_LENGTH);
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}
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#ifdef CC2500_INSTALLED
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if (sub_protocol == E010 || sub_protocol == PHOENIX) {
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XN297L_init(); // setup cc2500 for xn297L@250kbps emulation
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CC2500_WriteReg(CC2500_0C_FSCTRL0, option); // Frequency offset hack
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XN297L_SetTXAddr(addr, sizeof(addr));
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CC2500_SetPower();
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}
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else
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#endif
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{
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NRF24L01_Initialize();
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NRF24L01_SetTxRxMode(TX_EN);
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@ -249,6 +391,7 @@ static void __attribute__((unused)) MJXQ_init()
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else
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NRF24L01_SetBitrate(NRF24L01_BR_1M); // 1Mbps
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NRF24L01_SetPower();
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}
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}
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static void __attribute__((unused)) MJXQ_init2()
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@ -251,7 +251,7 @@ uint8_t xn297_tx_addr[5];
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uint8_t xn297_rx_addr[5];
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uint8_t xn297_crc = 0;
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static const uint8_t xn297_scramble[] = {
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const uint8_t xn297_scramble[] = {
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0xe3, 0xb1, 0x4b, 0xea, 0x85, 0xbc, 0xe5, 0x66,
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0x0d, 0xae, 0x8c, 0x88, 0x12, 0x69, 0xee, 0x1f,
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0xc7, 0x62, 0x97, 0xd5, 0x0b, 0x79, 0xca, 0xcc,
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