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	New protocol GD00X
Protocol number: 47 No sub protocol !!!! ONLY 1 ID AT THIS TIME !!!! CH1 AILERON CH3 THROTTLE CH5 TRIM CH6 LIGHT
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							| @ -0,0 +1,108 @@ | |||||||
|  | /*
 | ||||||
|  |  This project is free software: you can redistribute it and/or modify | ||||||
|  |  it under the terms of the GNU General Public License as published by | ||||||
|  |  the Free Software Foundation, either version 3 of the License, or | ||||||
|  |  (at your option) any later version. | ||||||
|  | 
 | ||||||
|  | Multiprotocol is distributed in the hope that it will be useful, | ||||||
|  |  but WITHOUT ANY WARRANTY; without even the implied warranty of | ||||||
|  |  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the | ||||||
|  |  GNU General Public License for more details. | ||||||
|  | 
 | ||||||
|  |  You should have received a copy of the GNU General Public License | ||||||
|  |  along with Multiprotocol.  If not, see <http://www.gnu.org/licenses/>.
 | ||||||
|  |  */ | ||||||
|  | // Compatible with GD005 C-17 and GD006 DA62 planes.
 | ||||||
|  | 
 | ||||||
|  | #if defined(GD00X_NRF24L01_INO) | ||||||
|  | 
 | ||||||
|  | #include "iface_nrf24l01.h" | ||||||
|  | 
 | ||||||
|  | #define GD00X_ORIGINAL_ID | ||||||
|  | 
 | ||||||
|  | #define GD00X_INITIAL_WAIT    500 | ||||||
|  | #define GD00X_PACKET_PERIOD   3500 | ||||||
|  | #define GD00X_RF_BIND_CHANNEL 2 | ||||||
|  | #define GD00X_PAYLOAD_SIZE    15 | ||||||
|  | 
 | ||||||
|  | // flags going to packet[11]
 | ||||||
|  | #define	GD00X_FLAG_DR		0x08 | ||||||
|  | #define	GD00X_FLAG_LIGHT	0x04 | ||||||
|  | 
 | ||||||
|  | static void __attribute__((unused)) GD00X_send_packet() | ||||||
|  | { | ||||||
|  | 	packet[0] = IS_BIND_IN_PROGRESS?0xAA:0x55; | ||||||
|  | 	memcpy(void *(packet+1),rx_tx_addr,4); | ||||||
|  | 	uint16_t channel=convert_channel_ppm(AILERON); | ||||||
|  | 	packet[5 ] = channel; | ||||||
|  | 	packet[6 ] = channel>>8; | ||||||
|  | 	uint16_t channel=convert_channel_ppm(THROTTLE); | ||||||
|  | 	packet[7 ] = channel; | ||||||
|  | 	packet[8 ] = channel>>8; | ||||||
|  | 	uint16_t channel=convert_channel_ppm(CH5);		// TRIM
 | ||||||
|  | 	packet[9 ] = channel; | ||||||
|  | 	packet[10] = channel>>8; | ||||||
|  | 	packet[11] = GD00X_FLAG_DR						// Force high rate
 | ||||||
|  | 			   | GETFLAG(CH6_SW, GD00X_FLAG_LIGHT); | ||||||
|  | 	packet[12] = 0x00; | ||||||
|  | 	packet[13] = 0x00; | ||||||
|  | 	packet[14] = 0x00; | ||||||
|  | 
 | ||||||
|  | 	// Power on, TX mode, CRC enabled
 | ||||||
|  | 	XN297_Configure(_BV(NRF24L01_00_EN_CRC) | _BV(NRF24L01_00_CRCO) | _BV(NRF24L01_00_PWR_UP)); | ||||||
|  | 	if(IS_BIND_DONE) | ||||||
|  | 	{ | ||||||
|  | 		NRF24L01_WriteReg(NRF24L01_05_RF_CH, hopping_frequency[hopping_frequency_no++]); | ||||||
|  | 		hopping_frequency_no &= 3;	// 4 RF channels
 | ||||||
|  | 	} | ||||||
|  | 
 | ||||||
|  | 	NRF24L01_WriteReg(NRF24L01_07_STATUS, 0x70); | ||||||
|  | 	NRF24L01_FlushTx(); | ||||||
|  | 	XN297_WritePayload(packet, GD00X_PAYLOAD_SIZE); | ||||||
|  | 
 | ||||||
|  | 	NRF24L01_SetPower();	// Set tx_power
 | ||||||
|  | } | ||||||
|  | 
 | ||||||
|  | static void __attribute__((unused)) GD00X_init() | ||||||
|  | { | ||||||
|  | 	NRF24L01_Initialize(); | ||||||
|  | 	NRF24L01_SetTxRxMode(TX_EN); | ||||||
|  | 	XN297_SetTXAddr((uint8_t*)"\xcc\xcc\xcc\xcc\xcc", 5); | ||||||
|  | 	NRF24L01_WriteReg(NRF24L01_05_RF_CH, GD00X_RF_BIND_CHANNEL);	// Bind channel
 | ||||||
|  | 	NRF24L01_FlushTx(); | ||||||
|  | 	NRF24L01_FlushRx(); | ||||||
|  | 	NRF24L01_WriteReg(NRF24L01_07_STATUS, 0x70);	// Clear data ready, data sent, and retransmit
 | ||||||
|  | 	NRF24L01_WriteReg(NRF24L01_01_EN_AA, 0x00);		// No Auto Acknowldgement on all data pipes
 | ||||||
|  | 	NRF24L01_WriteReg(NRF24L01_02_EN_RXADDR, 0x01);	// Enable data pipe 0 only
 | ||||||
|  | 	NRF24L01_SetBitrate(NRF24L01_BR_250K);			// 250Kbps
 | ||||||
|  | 	NRF24L01_SetPower(); | ||||||
|  | } | ||||||
|  | 
 | ||||||
|  | static void __attribute__((unused)) GD00X_initialize_txid() | ||||||
|  | { | ||||||
|  | 	#ifdef GD00X_ORIGINAL_ID | ||||||
|  | 		rx_tx_addr[0]=0x1F; | ||||||
|  | 		rx_tx_addr[1]=0x39: | ||||||
|  | 		rx_tx_addr[2]=0x12; | ||||||
|  | 		rx_tx_addr[3]=0x13; | ||||||
|  | 		for(uint8_t i=0; i<4;i++) | ||||||
|  | 			hopping_frequency[0]=79-(i<<1); | ||||||
|  | 	#endif | ||||||
|  | } | ||||||
|  | 
 | ||||||
|  | uint16_t GD00X_callback() | ||||||
|  | { | ||||||
|  | 	GD00X_send_packet(); | ||||||
|  | 	return GD00X_PACKET_PERIOD; | ||||||
|  | } | ||||||
|  | 
 | ||||||
|  | uint16_t initGD00X() | ||||||
|  | { | ||||||
|  | 	BIND_IN_PROGRESS;	// autobind protocol
 | ||||||
|  | 	GD00X_initialize_txid(); | ||||||
|  | 	GD00X_init(); | ||||||
|  | 	hopping_frequency_no = 0; | ||||||
|  | 	return GD00X_INITIAL_WAIT; | ||||||
|  | } | ||||||
|  | 
 | ||||||
|  | #endif | ||||||
| @ -44,4 +44,5 @@ | |||||||
| 44,NCC1701 | 44,NCC1701 | ||||||
| 45,E01X,E012,E015 | 45,E01X,E012,E015 | ||||||
| 46,V911S | 46,V911S | ||||||
|  | 47,GD00X | ||||||
| 63,Test | 63,Test | ||||||
|  | |||||||
| @ -19,7 +19,7 @@ | |||||||
| #define VERSION_MAJOR		1 | #define VERSION_MAJOR		1 | ||||||
| #define VERSION_MINOR		2 | #define VERSION_MINOR		2 | ||||||
| #define VERSION_REVISION	1 | #define VERSION_REVISION	1 | ||||||
| #define VERSION_PATCH_LEVEL	12 | #define VERSION_PATCH_LEVEL	13 | ||||||
| 
 | 
 | ||||||
| //******************
 | //******************
 | ||||||
| // Protocols
 | // Protocols
 | ||||||
| @ -73,6 +73,7 @@ enum PROTOCOLS | |||||||
| 	PROTO_NCC1701	= 44,	// =>NRF24L01
 | 	PROTO_NCC1701	= 44,	// =>NRF24L01
 | ||||||
| 	PROTO_E01X		= 45,	// =>NRF24L01
 | 	PROTO_E01X		= 45,	// =>NRF24L01
 | ||||||
| 	PROTO_V911S		= 46,	// =>NRF24L01
 | 	PROTO_V911S		= 46,	// =>NRF24L01
 | ||||||
|  | 	PROTO_GD00X		= 47,	// =>NRF24L01
 | ||||||
| 	PROTO_TEST		= 63,	// =>NRF24L01
 | 	PROTO_TEST		= 63,	// =>NRF24L01
 | ||||||
| }; | }; | ||||||
| 
 | 
 | ||||||
| @ -595,6 +596,7 @@ Serial: 100000 Baud 8e2      _ xxxx xxxx p -- | |||||||
| 					NCC1701		44 | 					NCC1701		44 | ||||||
| 					E01X		45 | 					E01X		45 | ||||||
| 					V911S		46 | 					V911S		46 | ||||||
|  | 					GD00X		47 | ||||||
|    BindBit=>		0x80	1=Bind/0=No |    BindBit=>		0x80	1=Bind/0=No | ||||||
|    AutoBindBit=>	0x40	1=Yes /0=No |    AutoBindBit=>	0x40	1=Yes /0=No | ||||||
|    RangeCheck=>		0x20	1=Yes /0=No |    RangeCheck=>		0x20	1=Yes /0=No | ||||||
|  | |||||||
| @ -176,6 +176,7 @@ | |||||||
| 	#undef	HONTAI_NRF24L01_INO | 	#undef	HONTAI_NRF24L01_INO | ||||||
| 	#undef	Q303_NRF24L01_INO | 	#undef	Q303_NRF24L01_INO | ||||||
| 	#undef	GW008_NRF24L01_INO | 	#undef	GW008_NRF24L01_INO | ||||||
|  | 	#undef	GD00X_NRF24L01_INO | ||||||
| 	#undef	DM002_NRF24L01_INO | 	#undef	DM002_NRF24L01_INO | ||||||
| 	#undef	CABELL_NRF24L01_INO | 	#undef	CABELL_NRF24L01_INO | ||||||
| 	#undef	ESKY150_NRF24L01_INO | 	#undef	ESKY150_NRF24L01_INO | ||||||
|  | |||||||
| @ -183,6 +183,7 @@ | |||||||
| #define	ESKY150_NRF24L01_INO | #define	ESKY150_NRF24L01_INO | ||||||
| #define	FQ777_NRF24L01_INO | #define	FQ777_NRF24L01_INO | ||||||
| #define	FY326_NRF24L01_INO | #define	FY326_NRF24L01_INO | ||||||
|  | #define	GD00X_NRF24L01_INO | ||||||
| #define	GW008_NRF24L01_INO | #define	GW008_NRF24L01_INO | ||||||
| #define	HISKY_NRF24L01_INO | #define	HISKY_NRF24L01_INO | ||||||
| #define	HONTAI_NRF24L01_INO | #define	HONTAI_NRF24L01_INO | ||||||
| @ -584,6 +585,8 @@ const PPM_Parameters PPM_prot[14*NBR_BANKS]=	{ | |||||||
| 		E015 | 		E015 | ||||||
| 	PROTO_V911S | 	PROTO_V911S | ||||||
| 		NONE | 		NONE | ||||||
|  | 	PROTO_GD00X | ||||||
|  | 		NONE | ||||||
| */ | */ | ||||||
| 
 | 
 | ||||||
| // RX_Num is used for TX & RX match. Using different RX_Num values for each receiver will prevent starting a model with the false config loaded...
 | // RX_Num is used for TX & RX match. Using different RX_Num values for each receiver will prevent starting a model with the false config loaded...
 | ||||||
|  | |||||||
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