diff --git a/BootLoaders/package_multi_4in1_avr_board_v1.0.1.tar.gz b/BootLoaders/Archives/package_multi_4in1_avr_board_v1.0.1.tar.gz similarity index 100% rename from BootLoaders/package_multi_4in1_avr_board_v1.0.1.tar.gz rename to BootLoaders/Archives/package_multi_4in1_avr_board_v1.0.1.tar.gz diff --git a/BootLoaders/Archives/package_multi_4in1_avr_board_v1.0.2.tar.gz b/BootLoaders/Archives/package_multi_4in1_avr_board_v1.0.2.tar.gz new file mode 100644 index 0000000..1ab6265 Binary files /dev/null and b/BootLoaders/Archives/package_multi_4in1_avr_board_v1.0.2.tar.gz differ diff --git a/BootLoaders/package_multi_4in1_board_v1.0.0.zip b/BootLoaders/Archives/package_multi_4in1_board_v1.0.0.zip similarity index 100% rename from BootLoaders/package_multi_4in1_board_v1.0.0.zip rename to BootLoaders/Archives/package_multi_4in1_board_v1.0.0.zip diff --git a/BootLoaders/package_multi_4in1_orangerx_board_v1.0.1.tar.gz b/BootLoaders/Archives/package_multi_4in1_orangerx_board_v1.0.1.tar.gz similarity index 100% rename from BootLoaders/package_multi_4in1_orangerx_board_v1.0.1.tar.gz rename to BootLoaders/Archives/package_multi_4in1_orangerx_board_v1.0.1.tar.gz diff --git a/BootLoaders/package_multi_4in1_stm32_board_v1.0.0.zip b/BootLoaders/Archives/package_multi_4in1_stm32_board_v1.0.0.zip similarity index 100% rename from BootLoaders/package_multi_4in1_stm32_board_v1.0.0.zip rename to BootLoaders/Archives/package_multi_4in1_stm32_board_v1.0.0.zip diff --git a/BootLoaders/package_multi_4in1_stm32_board_v1.0.1.tar.gz b/BootLoaders/Archives/package_multi_4in1_stm32_board_v1.0.1.tar.gz similarity index 100% rename from BootLoaders/package_multi_4in1_stm32_board_v1.0.1.tar.gz rename to BootLoaders/Archives/package_multi_4in1_stm32_board_v1.0.1.tar.gz diff --git a/BootLoaders/package_multi_4in1_stm32_board_v1.0.2.tar.gz b/BootLoaders/Archives/package_multi_4in1_stm32_board_v1.0.2.tar.gz similarity index 100% rename from BootLoaders/package_multi_4in1_stm32_board_v1.0.2.tar.gz rename to BootLoaders/Archives/package_multi_4in1_stm32_board_v1.0.2.tar.gz diff --git a/BootLoaders/Archives/package_multi_4in1_stm32_board_v1.0.3.tar.gz b/BootLoaders/Archives/package_multi_4in1_stm32_board_v1.0.3.tar.gz new file mode 100644 index 0000000..400d33f Binary files /dev/null and b/BootLoaders/Archives/package_multi_4in1_stm32_board_v1.0.3.tar.gz differ diff --git a/BootLoaders/Boards/orangerx/avrdude.conf b/BootLoaders/Boards/avr/avrdude_xmega.conf similarity index 100% rename from BootLoaders/Boards/orangerx/avrdude.conf rename to BootLoaders/Boards/avr/avrdude_xmega.conf diff --git a/BootLoaders/Boards/avr/boards.txt b/BootLoaders/Boards/avr/boards.txt index 928fdbd..1cdde33 100644 --- a/BootLoaders/Boards/avr/boards.txt +++ b/BootLoaders/Boards/avr/boards.txt @@ -20,7 +20,15 @@ multiatmega328p.build.f_cpu=16000000L multiatmega328p.build.core=arduino:arduino multiatmega328p.build.variant=arduino:eightanaloginputs multiatmega328p.build.extra_flags=-Wl,--relax -multiatmega328p.build.board=MULTI_AVR +multiatmega328p.build.board=MULTI_AVR=102 + +multiatmega328p.board.compiler.c.flags=-c -g -Os {compiler.warning_flags} -std=gnu11 -ffunction-sections -fdata-sections -MMD -flto -fno-fat-lto-objects +multiatmega328p.board.compiler.c.elf.flags=-Os -g -flto -fuse-linker-plugin -Wl,--gc-sections +multiatmega328p.board.compiler.S.flags=-c -g -x assembler-with-cpp -flto -MMD +multiatmega328p.board.recipe.output.save_file=multi-avr.hex +multiatmega328p.board.tools.avrdude.config.path={path}/etc/avrdude.conf +multiatmega328p.board.tools.avrdude.erase.pattern="{cmd.path}" "-C{config.path}" {erase.verbose} -p{build.mcu} -c{protocol} {program.extra_params} -e -Ulock:w:{bootloader.unlock_bits}:m -Uefuse:w:{bootloader.extended_fuses}:m -Uhfuse:w:{bootloader.high_fuses}:m -Ulfuse:w:{bootloader.low_fuses}:m +multiatmega328p.board.tools.avrdude.bootloader.pattern="{cmd.path}" "-C{config.path}" {bootloader.verbose} -p{build.mcu} -c{protocol} {program.extra_params} "-Uflash:w:{runtime.platform.path}/bootloaders/{bootloader.file}:i" -Ulock:w:{bootloader.lock_bits}:m multiatmega328p.bootloader.tool=arduino:avrdude multiatmega328p.bootloader.low_fuses=0xFF @@ -29,17 +37,48 @@ multiatmega328p.bootloader.unlock_bits=0x3F multiatmega328p.bootloader.lock_bits=0x0F multiatmega328p.menu.bootloader.none=No bootloader -multiatmega328p.menu.bootloader.none.build.board=MULTI_NO_BOOT +multiatmega328p.menu.bootloader.none.build.board=MULTI_NO_BOOT=102 multiatmega328p.menu.bootloader.none.upload.maximum_size=32768 multiatmega328p.menu.bootloader.none.bootloader.file=Multi4in1/AtmegaMultiEmpty.hex multiatmega328p.menu.bootloader.none.bootloader.high_fuses=0xD7 multiatmega328p.menu.bootloader.optiboot=Flash from TX -multiatmega328p.menu.bootloader.optiboot.build.board=MULTI_FLASH_FROM_TX +multiatmega328p.menu.bootloader.optiboot.build.board=MULTI_FLASH_FROM_TX=102 multiatmega328p.menu.bootloader.optiboot.upload.maximum_size=32256 multiatmega328p.menu.bootloader.optiboot.bootloader.file=Multi4in1/AtmegaMultiBoot.hex multiatmega328p.menu.bootloader.optiboot.bootloader.high_fuses=0xD6 ############################################################## + +############################################################## +## Multi 4-in-1 (OrangeRX) +## -------------------------------------------------- +multixmega32d4.name=Multi 4-in-1 (OrangeRX) + +multixmega32d4.build.board=MULTI_ORANGERX=102 +multixmega32d4.build.mcu=atxmega32d4 +multixmega32d4.build.f_cpu=32000000L +multixmega32d4.build.core=xmega +multixmega32d4.build.variant=xmega32d4 + +multixmega32d4.upload.tool=arduino:avrdude +multixmega32d4.upload.protocol=avrispmkii +multixmega32d4.upload.maximum_size=32768 +multixmega32d4.upload.speed=57600 + +multixmega32d4.bootloader.tool=arduino:avrdude +multixmega32d4.bootloader.file=Multi4in1/OrangeMultiBoot.hex +multixmega32d4.bootloader.lock_bits=0xFF + +multixmega32d4.board.compiler.c.flags=-c -g -Os {compiler.warning_flags} -std=gnu11 -ffunction-sections -fdata-sections -MMD -flto +multixmega32d4.board.compiler.c.elf.flags=-Os -flto -Wl,--gc-sections +multixmega32d4.board.compiler.S.flags=-c -g -x assembler-with-cpp -flto +multixmega32d4.board.recipe.output.save_file=multi-orx.hex + +multixmega32d4.board.tools.avrdude.config.path={runtime.platform.path}/avrdude_xmega.conf +multixmega32d4.board.tools.avrdude.erase.pattern="{cmd.path}" "-C{config.path}" {erase.verbose} -p{build.mcu} -c{protocol} {program.extra_params} -e -Ulock:w:{bootloader.unlock_bits}:m -Ufuse1:w:{bootloader.fuse1}:m -Ufuse2:w:{bootloader.fuse2}:m -Ufuse4:w:{bootloader.fuse4}:m -Ufuse5:w:{bootloader.fuse5}:m +multixmega32d4.board.tools.avrdude.bootloader.pattern="{cmd.path}" "-C{config.path}" {bootloader.verbose} -p{build.mcu} -c{protocol} {program.extra_params} "-Uboot:w:{runtime.platform.path}/bootloaders/{bootloader.file}:i" -Ulock:w:{bootloader.lock_bits}:m + +############################################################## diff --git a/BootLoaders/Boards/avr/bootloaders/Multi4in1/OrangeMultiBoot.hex b/BootLoaders/Boards/avr/bootloaders/Multi4in1/OrangeMultiBoot.hex new file mode 100644 index 0000000..1d7eb24 --- /dev/null +++ b/BootLoaders/Boards/avr/bootloaders/Multi4in1/OrangeMultiBoot.hex @@ -0,0 +1,47 @@ +:108000001F92CDB7DEB7CFD01124809178009FEFBB +:1080100090937800837099F088EA91E680936808DD +:108020009093690880E180934C0880914C0884FF0C +:10803000FCCF109240088091680682FD8FD082E0CC +:1080400080936106C12CD12C97D0813479F494D0DF +:10805000898399D08981823811F485E005C08138FF +:1080600011F484E001C083E080D075C0823411F443 +:1080700084E103C0853419F485E08CD06CC085356B +:1080800059F47AD0C82E78D0D12CD82A8D2D881FBB +:108090008827881F8BBF5EC0863521F484E07AD0A4 +:1080A00080E0E2CF843641F567D066D0F82E64D008 +:1080B000C601DCD000E010E25FD0F80181938F01AF +:1080C000FE12FACF60D0D7FC46C0CBD0C601DAD0C2 +:1080D000760100E010E2F801619171918F01C70112 +:1080E000DBD0F2E0EF0EF11C011581E2180799F7E1 +:1080F000C601E0D0B6D02FC08437C1F43DD03CD00B +:10810000F82E3AD040D0F601EC2CEF0C8F010F5F27 +:108110001F4F84912AD0E01207C0EFEFCE1ADE0A7B +:10812000FA94CF0CD11C17C0F801F0CF853739F481 +:108130002AD08EE11AD085E918D082E495CF813516 +:1081400049F421D080E111D08091A10886FFFCCFB5 +:1081500005D001C018D080E108D076CFE0E0F0E093 +:1081600084918F3F09F0099408959091A10895FF9B +:10817000FCCF8093A00808958091A10887FFFCCFD1 +:108180008091A0080895F8DF803211F085E1EDDFDD +:1081900084E1EBCFCF93C82FEFDFC150E9F7CF9148 +:1081A000F2CFA895089583EC8093520080915000FF +:1081B0008860809350008091510083FFFCCF82EC57 +:1081C0008093550080915000806180935000809191 +:1081D000510084FFFCCF88ED84BF1092400084BF23 +:1081E00024E02093400087E08093A20087E88093FA +:1081F0008301109241081092420810924308109295 +:10820000440810924608109247088FEF9FEF809322 +:1082100066089093670810926008109261088BE0DE +:1082200080934008209365062093620688E180933E +:10823000720698E0909345069093410692E29093DF +:10824000A6081092A7088093A4088091A3088F7CA9 +:1082500080618093A30883E08093A5088091A008A3 +:1082600008958091CF0187FDFCCF08958F939F9350 +:1082700082E2E0ECF1E08287FF91EF918DE984BF2B +:10828000E8950895FC0186E28093CA0188ED84BFD9 +:1082900081E08093CB0108950F921F92FC01062E7E +:1082A000172E83E28093CA018DE984BFE8951F9061 +:1082B0000F900895FC018EE28093CA018DE984BF7E +:0482C000E8950895A0 +:040000030000800079 +:00000001FF diff --git a/BootLoaders/Boards/orangerx/cores/xmega/Arduino.h b/BootLoaders/Boards/avr/cores/xmega/Arduino.h similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/Arduino.h rename to BootLoaders/Boards/avr/cores/xmega/Arduino.h diff --git a/BootLoaders/Boards/orangerx/cores/xmega/CDC.cpp b/BootLoaders/Boards/avr/cores/xmega/CDC.cpp similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/CDC.cpp rename to BootLoaders/Boards/avr/cores/xmega/CDC.cpp diff --git a/BootLoaders/Boards/orangerx/cores/xmega/Client.h b/BootLoaders/Boards/avr/cores/xmega/Client.h similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/Client.h rename to BootLoaders/Boards/avr/cores/xmega/Client.h diff --git a/BootLoaders/Boards/orangerx/cores/xmega/HID.cpp b/BootLoaders/Boards/avr/cores/xmega/HID.cpp similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/HID.cpp rename to BootLoaders/Boards/avr/cores/xmega/HID.cpp diff --git a/BootLoaders/Boards/orangerx/cores/xmega/HardwareSerial.cpp b/BootLoaders/Boards/avr/cores/xmega/HardwareSerial.cpp similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/HardwareSerial.cpp rename to BootLoaders/Boards/avr/cores/xmega/HardwareSerial.cpp diff --git a/BootLoaders/Boards/orangerx/cores/xmega/HardwareSerial.h b/BootLoaders/Boards/avr/cores/xmega/HardwareSerial.h similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/HardwareSerial.h rename to BootLoaders/Boards/avr/cores/xmega/HardwareSerial.h diff --git a/BootLoaders/Boards/orangerx/cores/xmega/IPAddress.cpp b/BootLoaders/Boards/avr/cores/xmega/IPAddress.cpp similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/IPAddress.cpp rename to BootLoaders/Boards/avr/cores/xmega/IPAddress.cpp diff --git a/BootLoaders/Boards/orangerx/cores/xmega/IPAddress.h b/BootLoaders/Boards/avr/cores/xmega/IPAddress.h similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/IPAddress.h rename to BootLoaders/Boards/avr/cores/xmega/IPAddress.h diff --git a/BootLoaders/Boards/orangerx/cores/xmega/Platform.h b/BootLoaders/Boards/avr/cores/xmega/Platform.h similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/Platform.h rename to BootLoaders/Boards/avr/cores/xmega/Platform.h diff --git a/BootLoaders/Boards/orangerx/cores/xmega/Print.cpp b/BootLoaders/Boards/avr/cores/xmega/Print.cpp similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/Print.cpp rename to BootLoaders/Boards/avr/cores/xmega/Print.cpp diff --git a/BootLoaders/Boards/orangerx/cores/xmega/Print.h b/BootLoaders/Boards/avr/cores/xmega/Print.h similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/Print.h rename to BootLoaders/Boards/avr/cores/xmega/Print.h diff --git a/BootLoaders/Boards/orangerx/cores/xmega/Printable.h b/BootLoaders/Boards/avr/cores/xmega/Printable.h similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/Printable.h rename to BootLoaders/Boards/avr/cores/xmega/Printable.h diff --git a/BootLoaders/Boards/orangerx/cores/xmega/Server.h b/BootLoaders/Boards/avr/cores/xmega/Server.h similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/Server.h rename to BootLoaders/Boards/avr/cores/xmega/Server.h diff --git a/BootLoaders/Boards/orangerx/cores/xmega/Stream.cpp b/BootLoaders/Boards/avr/cores/xmega/Stream.cpp similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/Stream.cpp rename to BootLoaders/Boards/avr/cores/xmega/Stream.cpp diff --git a/BootLoaders/Boards/orangerx/cores/xmega/Stream.h b/BootLoaders/Boards/avr/cores/xmega/Stream.h similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/Stream.h rename to BootLoaders/Boards/avr/cores/xmega/Stream.h diff --git a/BootLoaders/Boards/orangerx/cores/xmega/Tone.cpp b/BootLoaders/Boards/avr/cores/xmega/Tone.cpp similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/Tone.cpp rename to BootLoaders/Boards/avr/cores/xmega/Tone.cpp diff --git a/BootLoaders/Boards/orangerx/cores/xmega/USBAPI.h b/BootLoaders/Boards/avr/cores/xmega/USBAPI.h similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/USBAPI.h rename to BootLoaders/Boards/avr/cores/xmega/USBAPI.h diff --git a/BootLoaders/Boards/orangerx/cores/xmega/USBCore.cpp b/BootLoaders/Boards/avr/cores/xmega/USBCore.cpp similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/USBCore.cpp rename to BootLoaders/Boards/avr/cores/xmega/USBCore.cpp diff --git a/BootLoaders/Boards/orangerx/cores/xmega/USBCore.h b/BootLoaders/Boards/avr/cores/xmega/USBCore.h similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/USBCore.h rename to BootLoaders/Boards/avr/cores/xmega/USBCore.h diff --git a/BootLoaders/Boards/orangerx/cores/xmega/USBDesc.h b/BootLoaders/Boards/avr/cores/xmega/USBDesc.h similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/USBDesc.h rename to BootLoaders/Boards/avr/cores/xmega/USBDesc.h diff --git a/BootLoaders/Boards/orangerx/cores/xmega/Udp.h b/BootLoaders/Boards/avr/cores/xmega/Udp.h similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/Udp.h rename to BootLoaders/Boards/avr/cores/xmega/Udp.h diff --git a/BootLoaders/Boards/orangerx/cores/xmega/WCharacter.h b/BootLoaders/Boards/avr/cores/xmega/WCharacter.h similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/WCharacter.h rename to BootLoaders/Boards/avr/cores/xmega/WCharacter.h diff --git a/BootLoaders/Boards/orangerx/cores/xmega/WInterrupts.c b/BootLoaders/Boards/avr/cores/xmega/WInterrupts.c similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/WInterrupts.c rename to BootLoaders/Boards/avr/cores/xmega/WInterrupts.c diff --git a/BootLoaders/Boards/orangerx/cores/xmega/WMath.cpp b/BootLoaders/Boards/avr/cores/xmega/WMath.cpp similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/WMath.cpp rename to BootLoaders/Boards/avr/cores/xmega/WMath.cpp diff --git a/BootLoaders/Boards/orangerx/cores/xmega/WString.cpp b/BootLoaders/Boards/avr/cores/xmega/WString.cpp similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/WString.cpp rename to BootLoaders/Boards/avr/cores/xmega/WString.cpp diff --git a/BootLoaders/Boards/orangerx/cores/xmega/WString.h b/BootLoaders/Boards/avr/cores/xmega/WString.h similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/WString.h rename to BootLoaders/Boards/avr/cores/xmega/WString.h diff --git a/BootLoaders/Boards/orangerx/cores/xmega/avr-libc/malloc.c b/BootLoaders/Boards/avr/cores/xmega/avr-libc/malloc.c similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/avr-libc/malloc.c rename to BootLoaders/Boards/avr/cores/xmega/avr-libc/malloc.c diff --git a/BootLoaders/Boards/orangerx/cores/xmega/avr-libc/realloc.c b/BootLoaders/Boards/avr/cores/xmega/avr-libc/realloc.c similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/avr-libc/realloc.c rename to BootLoaders/Boards/avr/cores/xmega/avr-libc/realloc.c diff --git a/BootLoaders/Boards/orangerx/cores/xmega/avr-libc/sectionname.h b/BootLoaders/Boards/avr/cores/xmega/avr-libc/sectionname.h similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/avr-libc/sectionname.h rename to BootLoaders/Boards/avr/cores/xmega/avr-libc/sectionname.h diff --git a/BootLoaders/Boards/orangerx/cores/xmega/avr-libc/stdlib_private.h b/BootLoaders/Boards/avr/cores/xmega/avr-libc/stdlib_private.h similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/avr-libc/stdlib_private.h rename to BootLoaders/Boards/avr/cores/xmega/avr-libc/stdlib_private.h diff --git a/BootLoaders/Boards/orangerx/cores/xmega/binary.h b/BootLoaders/Boards/avr/cores/xmega/binary.h similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/binary.h rename to BootLoaders/Boards/avr/cores/xmega/binary.h diff --git a/BootLoaders/Boards/orangerx/cores/xmega/main.cpp b/BootLoaders/Boards/avr/cores/xmega/main.cpp similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/main.cpp rename to BootLoaders/Boards/avr/cores/xmega/main.cpp diff --git a/BootLoaders/Boards/orangerx/cores/xmega/new.cpp b/BootLoaders/Boards/avr/cores/xmega/new.cpp similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/new.cpp rename to BootLoaders/Boards/avr/cores/xmega/new.cpp diff --git a/BootLoaders/Boards/orangerx/cores/xmega/new.h b/BootLoaders/Boards/avr/cores/xmega/new.h similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/new.h rename to BootLoaders/Boards/avr/cores/xmega/new.h diff --git a/BootLoaders/Boards/orangerx/cores/xmega/wiring.c b/BootLoaders/Boards/avr/cores/xmega/wiring.c similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/wiring.c rename to BootLoaders/Boards/avr/cores/xmega/wiring.c diff --git a/BootLoaders/Boards/orangerx/cores/xmega/wiring_analog.c b/BootLoaders/Boards/avr/cores/xmega/wiring_analog.c similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/wiring_analog.c rename to BootLoaders/Boards/avr/cores/xmega/wiring_analog.c diff --git a/BootLoaders/Boards/orangerx/cores/xmega/wiring_digital.c b/BootLoaders/Boards/avr/cores/xmega/wiring_digital.c similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/wiring_digital.c rename to BootLoaders/Boards/avr/cores/xmega/wiring_digital.c diff --git a/BootLoaders/Boards/orangerx/cores/xmega/wiring_private.h b/BootLoaders/Boards/avr/cores/xmega/wiring_private.h similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/wiring_private.h rename to BootLoaders/Boards/avr/cores/xmega/wiring_private.h diff --git a/BootLoaders/Boards/orangerx/cores/xmega/wiring_pulse.c b/BootLoaders/Boards/avr/cores/xmega/wiring_pulse.c similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/wiring_pulse.c rename to BootLoaders/Boards/avr/cores/xmega/wiring_pulse.c diff --git a/BootLoaders/Boards/orangerx/cores/xmega/wiring_shift.c b/BootLoaders/Boards/avr/cores/xmega/wiring_shift.c similarity index 100% rename from BootLoaders/Boards/orangerx/cores/xmega/wiring_shift.c rename to BootLoaders/Boards/avr/cores/xmega/wiring_shift.c diff --git a/BootLoaders/Boards/avr/platform.local.txt b/BootLoaders/Boards/avr/platform.local.txt index 65ae6a9..2b786ce 100644 --- a/BootLoaders/Boards/avr/platform.local.txt +++ b/BootLoaders/Boards/avr/platform.local.txt @@ -1,16 +1,8 @@ -## Save hex -recipe.output.tmp_file={build.project_name}.hex -recipe.output.save_file=multi-avr.hex +## Override some platform.txt settings to create a .bin instead of a .hex file +## The two lines below can be uncommented to have the compiler create a .bin file instead of a .hex file +#compiler.elf2hex.flags=-O binary -R .eeprom +#recipe.objcopy.hex.pattern="{compiler.path}{compiler.elf2hex.cmd}" {compiler.elf2hex.flags} {compiler.elf2hex.extra_flags} "{build.path}/{build.project_name}.elf" "{build.path}/{build.project_name}.bin" -## Copy hex -# Make a copy of the compiled binary with the version number in the file name -recipe.hooks.objcopy.postobjcopy.01.pattern.windows="{runtime.platform.path}/tools/win/do_version.bat" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} -recipe.hooks.objcopy.postobjcopy.01.pattern.linux="{runtime.platform.path}/tools/linux/do_version" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} -recipe.hooks.objcopy.postobjcopy.01.pattern.linux64="{runtime.platform.path}/tools/linux64/do_version" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} -recipe.hooks.objcopy.postobjcopy.01.pattern.macosx="{runtime.platform.path}/tools/macosx/do_version" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} - -# If we're exporting the hex file, rename it with the version number -recipe.hooks.savehex.postsavehex.01.pattern.windows="{runtime.platform.path}/tools/win/do_version.bat" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} EXPORT -recipe.hooks.savehex.postsavehex.01.pattern.linux="{runtime.platform.path}/tools/linux/do_version" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} EXPORT -recipe.hooks.savehex.postsavehex.01.pattern.linux64="{runtime.platform.path}/tools/linux64/do_version" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} EXPORT -recipe.hooks.savehex.postsavehex.01.pattern.macosx="{runtime.platform.path}/tools/macosx/do_version" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} EXPORT +## Make a .bin version of the .hex file +## The line below can be uncommented to have a .bin file made as well as the .hex file +#recipe.hooks.objcopy.postobjcopy.00.pattern.windows="{compiler.path}{compiler.objcopy.cmd}" -I ihex "{build.path}/{build.project_name}.hex" -O binary "{build.path}/{build.project_name}.bin" diff --git a/BootLoaders/Boards/avr/platform.txt b/BootLoaders/Boards/avr/platform.txt index 8dd0c1d..0f28cb3 100644 --- a/BootLoaders/Boards/avr/platform.txt +++ b/BootLoaders/Boards/avr/platform.txt @@ -1,7 +1,139 @@ # +# Customized for the Atmega328p and OrangeRX (XMEGA) multi 4-in-1 boards. +# Both are AVR boards but need different compiler and upload flags and parameters. # # For more info: # https://github.com/arduino/Arduino/wiki/Arduino-IDE-1.5---3rd-party-Hardware-specification name=Multi 4-in-1 AVR -version=1.0.0 +version=1.0.2 + +compiler.warning_flags=-w +compiler.warning_flags.none=-w +compiler.warning_flags.default= +compiler.warning_flags.more=-Wall +compiler.warning_flags.all=-Wall -Wextra + +# Default "compiler.path" is correct, change only if you want to override the initial value +compiler.path={runtime.tools.avr-gcc.path}/bin/ +compiler.c.cmd=avr-gcc +compiler.c.flags={board.compiler.c.flags} +compiler.c.elf.flags={compiler.warning_flags} {board.compiler.c.elf.flags} +compiler.c.elf.cmd=avr-gcc +compiler.S.flags={board.compiler.S.flags} +compiler.cpp.cmd=avr-g++ +compiler.cpp.flags=-c -g -Os {compiler.warning_flags} -std=gnu++11 -fpermissive -fno-exceptions -ffunction-sections -fdata-sections -fno-threadsafe-statics -MMD -flto +compiler.ar.cmd=avr-gcc-ar +compiler.ar.flags=rcs +compiler.objcopy.cmd=avr-objcopy +compiler.objcopy.eep.flags=-O ihex -j .eeprom --set-section-flags=.eeprom=alloc,load --no-change-warnings --change-section-lma .eeprom=0 +compiler.elf2hex.flags=-O ihex -R .eeprom +compiler.elf2hex.cmd=avr-objcopy +compiler.ldflags= +compiler.size.cmd=avr-size + +# This can be overridden in boards.txt +build.extra_flags= + +# These can be overridden in platform.local.txt +compiler.c.extra_flags= +compiler.c.elf.extra_flags= +compiler.S.extra_flags= +compiler.cpp.extra_flags= +compiler.ar.extra_flags= +compiler.objcopy.eep.extra_flags= +compiler.elf2hex.extra_flags= + +# AVR compile patterns +# -------------------- + +## Compile c files +recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.c.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{object_file}" + +## Compile c++ files +recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{object_file}" + +## Compile S files +recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.S.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.S.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{object_file}" + +## Create archives +# archive_file_path is needed for backwards compatibility with IDE 1.6.5 or older, IDE 1.6.6 or newer overrides this value +archive_file_path={build.path}/{archive_file} +recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{archive_file_path}" "{object_file}" + +## Combine gc-sections, archives, and objects +recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} -mmcu={build.mcu} {compiler.c.elf.extra_flags} -o "{build.path}/{build.project_name}.elf" {object_files} "{build.path}/{archive_file}" "-L{build.path}" -lm + +## Create output files (.eep and .hex) +recipe.objcopy.eep.pattern="{compiler.path}{compiler.objcopy.cmd}" {compiler.objcopy.eep.flags} {compiler.objcopy.eep.extra_flags} "{build.path}/{build.project_name}.elf" "{build.path}/{build.project_name}.eep" +recipe.objcopy.hex.pattern="{compiler.path}{compiler.elf2hex.cmd}" {compiler.elf2hex.flags} {compiler.elf2hex.extra_flags} "{build.path}/{build.project_name}.elf" "{build.path}/{build.project_name}.hex" + +## Save hex +recipe.output.tmp_file={build.project_name}.hex +recipe.output.save_file={board.recipe.output.save_file} + +## Compute size +recipe.size.pattern="{compiler.path}{compiler.size.cmd}" -A "{build.path}/{build.project_name}.elf" +recipe.size.regex=^(?:\.text|\.data|\.bootloader)\s+([0-9]+).* +recipe.size.regex.data=^(?:\.data|\.bss|\.noinit)\s+([0-9]+).* +recipe.size.regex.eeprom=^(?:\.eeprom)\s+([0-9]+).* + +## Preprocessor +preproc.includes.flags=-w -x c++ -M -MG -MP +recipe.preproc.includes="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} {preproc.includes.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} "{source_file}" + +preproc.macros.flags=-w -x c++ -E -CC +recipe.preproc.macros="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} {preproc.macros.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{preprocessed_file_path}" + +## Post objcopy recipes +# Make a copy of the compiled binary with the version number in the file name +recipe.hooks.objcopy.postobjcopy.01.pattern.windows="{runtime.platform.path}/tools/win/do_version.bat" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} +recipe.hooks.objcopy.postobjcopy.01.pattern.linux="{runtime.platform.path}/tools/linux/do_version" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} +recipe.hooks.objcopy.postobjcopy.01.pattern.linux64="{runtime.platform.path}/tools/linux64/do_version" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} +recipe.hooks.objcopy.postobjcopy.01.pattern.macosx="{runtime.platform.path}/tools/macosx/do_version" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} + +## Post savehex (export compiled binary) recipes +# If we're exporting the hex file, rename it with the version number +recipe.hooks.savehex.postsavehex.01.pattern.windows="{runtime.platform.path}/tools/win/do_version.bat" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} EXPORT +recipe.hooks.savehex.postsavehex.01.pattern.linux="{runtime.platform.path}/tools/linux/do_version" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} EXPORT +recipe.hooks.savehex.postsavehex.01.pattern.linux64="{runtime.platform.path}/tools/linux64/do_version" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} EXPORT +recipe.hooks.savehex.postsavehex.01.pattern.macosx="{runtime.platform.path}/tools/macosx/do_version" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} EXPORT + +# AVR Uploader/Programmers tools +# ------------------------------ + +tools.avrdude.path={runtime.tools.avrdude.path} +tools.avrdude.cmd.path={path}/bin/avrdude +tools.avrdude.config.path={board.tools.avrdude.config.path} + +tools.avrdude.upload.params.verbose=-v +tools.avrdude.upload.params.quiet=-q -q +# tools.avrdude.upload.verify is needed for backwards compatibility with IDE 1.6.8 or older, IDE 1.6.9 or newer overrides this value +tools.avrdude.upload.verify= +tools.avrdude.upload.params.noverify=-V +tools.avrdude.upload.pattern="{cmd.path}" "-C{config.path}" {upload.verbose} {upload.verify} -p{build.mcu} -c{upload.protocol} "-P{serial.port}" -b{upload.speed} -D "-Uflash:w:{build.path}/{build.project_name}.hex:i" + +tools.avrdude.program.params.verbose=-v +tools.avrdude.program.params.quiet=-q -q +# tools.avrdude.program.verify is needed for backwards compatibility with IDE 1.6.8 or older, IDE 1.6.9 or newer overrides this value +tools.avrdude.program.verify= +tools.avrdude.program.params.noverify=-V +tools.avrdude.program.pattern="{cmd.path}" "-C{config.path}" {program.verbose} {program.verify} -p{build.mcu} -c{protocol} {program.extra_params} "-Uflash:w:{build.path}/{build.project_name}.hex:i" + +tools.avrdude.erase.params.verbose=-v +tools.avrdude.erase.params.quiet=-q -q +tools.avrdude.erase.pattern={board.tools.avrdude.erase.pattern} + +tools.avrdude.bootloader.params.verbose=-v +tools.avrdude.bootloader.params.quiet=-q -q +tools.avrdude.bootloader.pattern={board.tools.avrdude.bootloader.pattern} + +tools.avrdude_remote.upload.pattern=/usr/bin/run-avrdude /tmp/sketch.hex {upload.verbose} -p{build.mcu} + +# USB Default Flags +# Default blank usb manufacturer will be filled in at compile time +# - from numeric vendor ID, set to Unknown otherwise +build.usb_manufacturer="Unknown" +build.usb_flags=-DUSB_VID={build.vid} -DUSB_PID={build.pid} '-DUSB_MANUFACTURER={build.usb_manufacturer}' '-DUSB_PRODUCT={build.usb_product}' + + diff --git a/BootLoaders/Boards/avr/tools/linux/do_version b/BootLoaders/Boards/avr/tools/linux/do_version index ba2a182..6b47f49 100755 --- a/BootLoaders/Boards/avr/tools/linux/do_version +++ b/BootLoaders/Boards/avr/tools/linux/do_version @@ -6,7 +6,31 @@ SKETCH_PATH=$3 MULTI_BOARD=$4 EXPORT_FLAG=$5 -MULTI_TYPE=avr +IFS== read MULTI_BOARD BOARD_VERSION <<< "$MULTI_BOARD" + +case "$MULTI_BOARD" in + MULTI_NO_BOOT) + MULTI_TYPE=avr + ;; + MULTI_FLASH_FROM_TX) + MULTI_TYPE=avr + ;; + MULTI_STM32_NO_BOOT) + MULTI_TYPE=stm + ;; + MULTI_STM32_FLASH_FROM_TX) + MULTI_TYPE=stm + ;; + MULTI_ORANGERX) + MULTI_TYPE=orx + ;; +esac + +#echo "Build Path: $BUILD_PATH" +#echo "Sketch Path: $SKETCH_PATH" +#echo "Project Name: $PROJECT_NAME" +#echo "Multi Board: $MULTI_BOARD" +#echo "Multi Board Type: $MULTI_TYPE" if [ -e "$BUILD_PATH/sketch/Multiprotocol.h" ]; then MAJOR_VERSION=$(grep "VERSION_MAJOR" "$BUILD_PATH/sketch/Multiprotocol.h" | awk -v N=3 '{print $N}') diff --git a/BootLoaders/Boards/avr/tools/linux64/do_version b/BootLoaders/Boards/avr/tools/linux64/do_version index ba2a182..6b47f49 100755 --- a/BootLoaders/Boards/avr/tools/linux64/do_version +++ b/BootLoaders/Boards/avr/tools/linux64/do_version @@ -6,7 +6,31 @@ SKETCH_PATH=$3 MULTI_BOARD=$4 EXPORT_FLAG=$5 -MULTI_TYPE=avr +IFS== read MULTI_BOARD BOARD_VERSION <<< "$MULTI_BOARD" + +case "$MULTI_BOARD" in + MULTI_NO_BOOT) + MULTI_TYPE=avr + ;; + MULTI_FLASH_FROM_TX) + MULTI_TYPE=avr + ;; + MULTI_STM32_NO_BOOT) + MULTI_TYPE=stm + ;; + MULTI_STM32_FLASH_FROM_TX) + MULTI_TYPE=stm + ;; + MULTI_ORANGERX) + MULTI_TYPE=orx + ;; +esac + +#echo "Build Path: $BUILD_PATH" +#echo "Sketch Path: $SKETCH_PATH" +#echo "Project Name: $PROJECT_NAME" +#echo "Multi Board: $MULTI_BOARD" +#echo "Multi Board Type: $MULTI_TYPE" if [ -e "$BUILD_PATH/sketch/Multiprotocol.h" ]; then MAJOR_VERSION=$(grep "VERSION_MAJOR" "$BUILD_PATH/sketch/Multiprotocol.h" | awk -v N=3 '{print $N}') diff --git a/BootLoaders/Boards/avr/tools/macosx/do_version b/BootLoaders/Boards/avr/tools/macosx/do_version index ba2a182..6b47f49 100755 --- a/BootLoaders/Boards/avr/tools/macosx/do_version +++ b/BootLoaders/Boards/avr/tools/macosx/do_version @@ -6,7 +6,31 @@ SKETCH_PATH=$3 MULTI_BOARD=$4 EXPORT_FLAG=$5 -MULTI_TYPE=avr +IFS== read MULTI_BOARD BOARD_VERSION <<< "$MULTI_BOARD" + +case "$MULTI_BOARD" in + MULTI_NO_BOOT) + MULTI_TYPE=avr + ;; + MULTI_FLASH_FROM_TX) + MULTI_TYPE=avr + ;; + MULTI_STM32_NO_BOOT) + MULTI_TYPE=stm + ;; + MULTI_STM32_FLASH_FROM_TX) + MULTI_TYPE=stm + ;; + MULTI_ORANGERX) + MULTI_TYPE=orx + ;; +esac + +#echo "Build Path: $BUILD_PATH" +#echo "Sketch Path: $SKETCH_PATH" +#echo "Project Name: $PROJECT_NAME" +#echo "Multi Board: $MULTI_BOARD" +#echo "Multi Board Type: $MULTI_TYPE" if [ -e "$BUILD_PATH/sketch/Multiprotocol.h" ]; then MAJOR_VERSION=$(grep "VERSION_MAJOR" "$BUILD_PATH/sketch/Multiprotocol.h" | awk -v N=3 '{print $N}') diff --git a/BootLoaders/Boards/avr/tools/win/do_version.bat b/BootLoaders/Boards/avr/tools/win/do_version.bat index 0166427..d855889 100644 --- a/BootLoaders/Boards/avr/tools/win/do_version.bat +++ b/BootLoaders/Boards/avr/tools/win/do_version.bat @@ -7,31 +7,43 @@ SET BUILD_PATH=%1 SET PROJECT_NAME=%2 SET SKETCH_PATH=%3 SET MULTI_BOARD=%4 -SET EXPORT_FLAG=%5 +SET BOARD_VERSION=%5 +SET EXPORT_FLAG=%6 REM Remove double-quotes from the paths SET BUILD_PATH=%BUILD_PATH:"=% SET SKETCH_PATH=%SKETCH_PATH:"=% +IF %MULTI_BOARD%==MULTI_NO_BOOT SET MULTI_TYPE=avr +IF %MULTI_BOARD%==MULTI_FLASH_FROM_TX SET MULTI_TYPE=avr +IF %MULTI_BOARD%==MULTI_STM32_NO_BOOT SET MULTI_TYPE=stm +IF %MULTI_BOARD%==MULTI_STM32_FLASH_FROM_TX SET MULTI_TYPE=stm +IF %MULTI_BOARD%==MULTI_ORANGERX SET MULTI_TYPE=orx + IF DEFINED DEBUG ( + ECHO. ECHO Sketch Path: %SKETCH_PATH% - ECHO Multi board: %MULTI_BOARD% + ECHO Multi Board: %MULTI_BOARD% + ECHO Multi Board Type: %MULTI_TYPE% + ECHO. ) -SET MULTI_TYPE=avr - -IF EXIST "%1\sketch\Multiprotocol.h" ( - REM ECHO Getting Multi-MODULE firmware version from "%1\sketch\Multiprotocol.h" - FOR /F "tokens=* usebackq skip=2" %%A in (`find "#define VERSION_MAJOR" "%1\sketch\Multiprotocol.h"`) DO FOR /F "tokens=3" %%i in ("%%A") do SET MAJOR_VERSION=%%i - FOR /F "tokens=* usebackq skip=2" %%B in (`find "#define VERSION_MINOR" "%1\sketch\Multiprotocol.h"`) DO FOR /F "tokens=3" %%i in ("%%B") do SET MINOR_VERSION=%%i - FOR /F "tokens=* usebackq skip=2" %%C in (`find "#define VERSION_REVISION" "%1\sketch\Multiprotocol.h"`) DO FOR /F "tokens=3" %%i in ("%%C") do SET REVISION_VERSION=%%i - FOR /F "tokens=* usebackq skip=2" %%D in (`find "#define VERSION_PATCH_LEVEL" "%1\sketch\Multiprotocol.h"`) DO FOR /F "tokens=3" %%i in ("%%D") do SET PATCH_VERSION=%%i +IF EXIST "%BUILD_PATH%\sketch\Multiprotocol.h" ( + IF DEFINED DEBUG ECHO Getting Multi firmware version from "%BUILD_PATH%\sketch\Multiprotocol.h" + FOR /F "tokens=* usebackq" %%A in (`%SystemRoot%\system32\findstr.exe /C:"#define VERSION_MAJOR" "%BUILD_PATH%\sketch\Multiprotocol.h"`) DO FOR /F "tokens=3" %%i in ("%%A") do SET MAJOR_VERSION=%%i + FOR /F "tokens=* usebackq" %%B in (`%SystemRoot%\system32\findstr.exe /C:"#define VERSION_MINOR" "%BUILD_PATH%\sketch\Multiprotocol.h"`) DO FOR /F "tokens=3" %%i in ("%%B") do SET MINOR_VERSION=%%i + FOR /F "tokens=* usebackq" %%C in (`%SystemRoot%\system32\findstr.exe /C:"#define VERSION_REVISION" "%BUILD_PATH%\sketch\Multiprotocol.h"`) DO FOR /F "tokens=3" %%i in ("%%C") do SET REVISION_VERSION=%%i + FOR /F "tokens=* usebackq" %%D in (`%SystemRoot%\system32\findstr.exe /C:"#define VERSION_PATCH_LEVEL" "%BUILD_PATH%\sketch\Multiprotocol.h"`) DO FOR /F "tokens=3" %%i in ("%%D") do SET PATCH_VERSION=%%i SET MULTI_VER=!MAJOR_VERSION!.!MINOR_VERSION!.!REVISION_VERSION!.!PATCH_VERSION! ) ELSE ( SET MULTI_VER= ) -IF DEFINED DEBUG ECHO Multi-MODULE firmware version: %MULTI_VER% +IF DEFINED DEBUG ( + ECHO. + ECHO Multi Firmware Version: %MULTI_VER% + ECHO. +) REM Copy the compiled file to the sketch folder with the version number in the file name IF EXIST "%BUILD_PATH%\%PROJECT_NAME%.hex" ( diff --git a/BootLoaders/Boards/orangerx/variants/xmega32d4/pins_arduino.h b/BootLoaders/Boards/avr/variants/xmega32d4/pins_arduino.h similarity index 100% rename from BootLoaders/Boards/orangerx/variants/xmega32d4/pins_arduino.h rename to BootLoaders/Boards/avr/variants/xmega32d4/pins_arduino.h diff --git a/BootLoaders/Boards/make_archives.sh b/BootLoaders/Boards/make_archives.sh new file mode 100755 index 0000000..b119718 --- /dev/null +++ b/BootLoaders/Boards/make_archives.sh @@ -0,0 +1,26 @@ +#!/bin/bash + +AVR_VERSION=$(grep "^version=[0-9].[0-9].[0-9]" "avr/platform.txt" | awk -F = '{ print $2 }') +STM_VERSION=$(grep "^version=[0-9].[0-9].[0-9]" "stm32/platform.txt" | awk -F = '{ print $2 }') + +echo +echo "AVR Version: $AVR_VERSION" +echo "Creating archive 'package_multi_4in1_avr_board_v$AVR_VERSION.tar.gz'" +tar -czf ../Archives/package_multi_4in1_avr_board_v$AVR_VERSION.tar.gz --transform s/avr/package_multi_4in1_avr_board_v$AVR_VERSION/ avr/* +sleep 1s +echo +echo "Package: package_multi_4in1_avr_board_v$AVR_VERSION.tar.gz" +echo "SHA256: `(sha256sum ../Archives/package_multi_4in1_avr_board_v$AVR_VERSION.tar.gz | awk -v N=1 '{print $N}')`" +echo "Size: `(ls -al ../Archives/package_multi_4in1_avr_board_v$AVR_VERSION.tar.gz | awk -v N=5 '{print $N}')`" +echo +echo "STM Version: $STM_VERSION" +echo "Creating archive 'package_multi_4in1_stm32_board_v$STM_VERSION.tar.gz'" +tar -czf ../Archives/package_multi_4in1_stm32_board_v$STM_VERSION.tar.gz --transform s/stm32/package_multi_4in1_stm32_board_v$STM_VERSION/ stm32/* +sleep 1s +echo +echo "Package: package_multi_4in1_stm_board_v$STM_VERSION.tar.gz" +echo "SHA256: `(sha256sum ../Archives/package_multi_4in1_stm32_board_v$STM_VERSION.tar.gz | awk -v N=1 '{print $N}')`" +echo "Size: `(ls -al ../Archives/package_multi_4in1_stm32_board_v$STM_VERSION.tar.gz | awk -v N=5 '{print $N}')`" +echo +echo Done +echo diff --git a/BootLoaders/Boards/orangerx/boards.txt b/BootLoaders/Boards/orangerx/boards.txt deleted file mode 100644 index 0980eb8..0000000 --- a/BootLoaders/Boards/orangerx/boards.txt +++ /dev/null @@ -1,19 +0,0 @@ -# See: https://github.com/arduino/Arduino/wiki/Arduino-IDE-1.5---3rd-party-Hardware-specification -# See: http://code.google.com/p/arduino/wiki/Platforms - -############################################################## - -############################################################## -## Multi 4-in-1 (OrangeRX) -## -------------------------------------------------- -multixmega32d4.name=Multi 4-in-1 (OrangeRX) -multixmega32d4.build.board=MULTI_ORANGERX -multixmega32d4.upload.protocol=arduino -multixmega32d4.upload.maximum_size=32768 -multixmega32d4.upload.speed=115200 -multixmega32d4.build.mcu=atxmega32d4 -multixmega32d4.build.f_cpu=32000000L -multixmega32d4.build.core=xmega -multixmega32d4.build.variant=xmega32d4 - -############################################################## diff --git a/BootLoaders/Boards/orangerx/platform.local.txt b/BootLoaders/Boards/orangerx/platform.local.txt deleted file mode 100644 index 28b3377..0000000 --- a/BootLoaders/Boards/orangerx/platform.local.txt +++ /dev/null @@ -1,25 +0,0 @@ -## Save hex -recipe.output.tmp_file={build.project_name}.hex -recipe.output.save_file=multi-orx.hex - -## Override some platform.txt settings to create a .bin instead of a .hex file -## The two lines below can be uncommented to have the compiler create a .bin file instead of a .hex file -#compiler.elf2hex.flags=-O binary -R .eeprom -#recipe.objcopy.hex.pattern="{compiler.path}{compiler.elf2hex.cmd}" {compiler.elf2hex.flags} {compiler.elf2hex.extra_flags} "{build.path}/{build.project_name}.elf" "{build.path}/{build.project_name}.bin" - -## Make a .bin version of the .hex file -## The line below can be uncommented to have a .bin file made as well as the .hex file -#recipe.hooks.objcopy.postobjcopy.00.pattern.windows="{compiler.path}{compiler.objcopy.cmd}" -I ihex "{build.path}/{build.project_name}.hex" -O binary "{build.path}/{build.project_name}.bin" - -## Copy hex -# Make a copy of the compiled binary with the version number in the file name -recipe.hooks.objcopy.postobjcopy.01.pattern.windows="{runtime.platform.path}/tools/win/do_version.bat" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} -recipe.hooks.objcopy.postobjcopy.01.pattern.linux="{runtime.platform.path}/tools/linux/do_version" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} -recipe.hooks.objcopy.postobjcopy.01.pattern.linux64="{runtime.platform.path}/tools/linux64/do_version" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} -recipe.hooks.objcopy.postobjcopy.01.pattern.macosx="{runtime.platform.path}/tools/macosx/do_version" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} - -# If we're exporting the hex file, rename it with the version number -recipe.hooks.savehex.postsavehex.01.pattern.windows="{runtime.platform.path}/tools/win/do_version.bat" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} EXPORT -recipe.hooks.savehex.postsavehex.01.pattern.linux="{runtime.platform.path}/tools/linux/do_version" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} EXPORT -recipe.hooks.savehex.postsavehex.01.pattern.linux64="{runtime.platform.path}/tools/linux64/do_version" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} EXPORT -recipe.hooks.savehex.postsavehex.01.pattern.macosx="{runtime.platform.path}/tools/macosx/do_version" "{build.path}" "{build.project_name}" "{build.source.path}" {build.board} EXPORT diff --git a/BootLoaders/Boards/orangerx/platform.txt b/BootLoaders/Boards/orangerx/platform.txt deleted file mode 100644 index da6dcb2..0000000 --- a/BootLoaders/Boards/orangerx/platform.txt +++ /dev/null @@ -1,124 +0,0 @@ -name=Multi 4-in-1 OrangeRX -version=1.0.1 - -# this was borrowed from the installed version of 'platform.txt' -# XMEGA compile variables -# --------------------- - -compiler.warning_flags=-w -compiler.warning_flags.none=-w -compiler.warning_flags.default= -compiler.warning_flags.more=-Wall -compiler.warning_flags.all=-Wall -Wextra - -# Default "compiler.path" is correct, change only if you want to override the initial value -compiler.path={runtime.tools.avr-gcc.path}/bin/ -compiler.c.cmd=avr-gcc -compiler.c.flags=-c -g -Os {compiler.warning_flags} -std=gnu11 -ffunction-sections -fdata-sections -MMD -flto -compiler.c.elf.flags={compiler.warning_flags} -Os -flto -Wl,--gc-sections -compiler.c.elf.cmd=avr-gcc -compiler.S.flags=-c -g -x assembler-with-cpp -flto -compiler.cpp.cmd=avr-g++ -compiler.cpp.flags=-c -g -Os {compiler.warning_flags} -std=gnu++11 -fpermissive -fno-exceptions -ffunction-sections -fdata-sections -fno-threadsafe-statics -MMD -flto -compiler.ar.cmd=avr-gcc-ar -compiler.ar.flags=rcs -compiler.objcopy.cmd=avr-objcopy -compiler.objcopy.eep.flags=-O ihex -j .eeprom --set-section-flags=.eeprom=alloc,load --no-change-warnings --change-section-lma .eeprom=0 -compiler.elf2hex.flags=-O ihex -R .eeprom -compiler.elf2hex.cmd=avr-objcopy -compiler.ldflags= -compiler.size.cmd=avr-size - -# This can be overridden in boards.txt -build.extra_flags= - -# These can be overridden in platform.local.txt -compiler.c.extra_flags= -compiler.c.elf.extra_flags= -compiler.S.extra_flags= -compiler.cpp.extra_flags= -compiler.ar.extra_flags= -compiler.objcopy.eep.extra_flags= -compiler.elf2hex.extra_flags= - -# XMEGA compile patterns -# -------------------- - -## Compile c files -recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.c.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{object_file}" - -## Compile c++ files -recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{object_file}" - -## Compile S files -recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.S.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.S.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{object_file}" - -## Create archives -# archive_file_path is needed for backwards compatibility with IDE 1.6.5 or older, IDE 1.6.6 or newer overrides this value -archive_file_path={build.path}/{archive_file} -recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{archive_file_path}" "{object_file}" - -## Combine gc-sections, archives, and objects -recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} -mmcu={build.mcu} {compiler.c.elf.extra_flags} -o "{build.path}/{build.project_name}.elf" {object_files} "{build.path}/{archive_file}" "-L{build.path}" -lm - -## Create output files (.eep and .hex) -recipe.objcopy.eep.pattern="{compiler.path}{compiler.objcopy.cmd}" {compiler.objcopy.eep.flags} {compiler.objcopy.eep.extra_flags} "{build.path}/{build.project_name}.elf" "{build.path}/{build.project_name}.eep" -recipe.objcopy.hex.pattern="{compiler.path}{compiler.elf2hex.cmd}" {compiler.elf2hex.flags} {compiler.elf2hex.extra_flags} "{build.path}/{build.project_name}.elf" "{build.path}/{build.project_name}.hex" - -## Save hex -recipe.output.tmp_file={build.project_name}.hex -recipe.output.save_file={build.project_name}.{build.variant}.hex - -## Compute size -recipe.size.pattern="{compiler.path}{compiler.size.cmd}" -A "{build.path}/{build.project_name}.elf" -recipe.size.regex=^(?:\.text|\.data|\.bootloader)\s+([0-9]+).* -recipe.size.regex.data=^(?:\.data|\.bss|\.noinit)\s+([0-9]+).* -recipe.size.regex.eeprom=^(?:\.eeprom)\s+([0-9]+).* - -## Preprocessor -preproc.includes.flags=-w -x c++ -M -MG -MP -recipe.preproc.includes="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} {preproc.includes.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} "{source_file}" - -preproc.macros.flags=-w -x c++ -E -CC -recipe.preproc.macros="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} {preproc.macros.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{preprocessed_file_path}" - -# XMEGA Uploader/Programmers tools -# ------------------------------ - -tools.avrdude.path={runtime.tools.avrdude.path} -tools.avrdude.cmd.path={path}/bin/avrdude -# NOTE: change to avrdude.conf path - using the one specified by this hardware package -# THIS is a LOT 'nicer' than overwriting the system file. Some packages actually do that... -tools.avrdude.config.path={runtime.platform.path}/avrdude.conf - -tools.avrdude.upload.params.verbose=-v -tools.avrdude.upload.params.quiet=-q -q -# tools.avrdude.upload.verify is needed for backwards compatibility with IDE 1.6.8 or older, IDE 1.6.9 or newer overrides this value -tools.avrdude.upload.verify= -tools.avrdude.upload.params.noverify=-V -tools.avrdude.upload.pattern="{cmd.path}" "-C{config.path}" {upload.verbose} {upload.verify} -p{build.mcu} -c{upload.protocol} -P{serial.port} -b{upload.speed} -D "-Uflash:w:{build.path}/{build.project_name}.hex:i" - -tools.avrdude.program.params.verbose=-v -tools.avrdude.program.params.quiet=-q -q -# tools.avrdude.program.verify is needed for backwards compatibility with IDE 1.6.8 or older, IDE 1.6.9 or newer overrides this value -tools.avrdude.program.verify= -tools.avrdude.program.params.noverify=-V -tools.avrdude.program.pattern="{cmd.path}" "-C{config.path}" {program.verbose} {program.verify} -p{build.mcu} -c{protocol} {program.extra_params} "-Uflash:w:{build.path}/{build.project_name}.hex:i" - -tools.avrdude.erase.params.verbose=-v -tools.avrdude.erase.params.quiet=-q -q -tools.avrdude.erase.pattern="{cmd.path}" "-C{config.path}" {erase.verbose} -p{build.mcu} -c{protocol} {program.extra_params} -e -Ulock:w:{bootloader.unlock_bits}:m -Ufuse1:w:{bootloader.fuse1}:m -Ufuse2:w:{bootloader.fuse2}:m -Ufuse4:w:{bootloader.fuse4}:m -Ufuse5:w:{bootloader.fuse5}:m - -tools.avrdude.bootloader.params.verbose=-v -tools.avrdude.bootloader.params.quiet=-q -q -tools.avrdude.bootloader.pattern="{cmd.path}" "-C{config.path}" {bootloader.verbose} -p{build.mcu} -c{protocol} {program.extra_params} "-Uboot:w:{runtime.platform.path}/bootloaders/{bootloader.file}:i" -Ulock:w:{bootloader.lock_bits}:m - -tools.avrdude_remote.upload.pattern=/usr/bin/run-avrdude /tmp/sketch.hex {upload.verbose} -p{build.mcu} - -# USB Default Flags -# Default blank usb manufacturer will be filled in at compile time -# - from numeric vendor ID, set to Unknown otherwise -build.usb_manufacturer="Unknown" -build.usb_flags=-DUSB_VID={build.vid} -DUSB_PID={build.pid} '-DUSB_MANUFACTURER={build.usb_manufacturer}' '-DUSB_PRODUCT={build.usb_product}' - - diff --git a/BootLoaders/Boards/orangerx/tools/linux/do_version b/BootLoaders/Boards/orangerx/tools/linux/do_version deleted file mode 100755 index 184015b..0000000 --- a/BootLoaders/Boards/orangerx/tools/linux/do_version +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/bash - -BUILD_PATH=$1 -PROJECT_NAME=$2 -SKETCH_PATH=$3 -MULTI_BOARD=$4 -EXPORT_FLAG=$5 - -MULTI_TYPE=orx - -if [ -e "$BUILD_PATH/sketch/Multiprotocol.h" ]; then - MAJOR_VERSION=$(grep "VERSION_MAJOR" "$BUILD_PATH/sketch/Multiprotocol.h" | awk -v N=3 '{print $N}') - MINOR_VERSION=$(grep "VERSION_MINOR" "$BUILD_PATH/sketch/Multiprotocol.h" | awk -v N=3 '{print $N}') - REVISION_VERSION=$(grep "VERSION_REVISION" "$BUILD_PATH/sketch/Multiprotocol.h" | awk -v N=3 '{print $N}') - PATCH_VERSION=$(grep "VERSION_PATCH" "$BUILD_PATH/sketch/Multiprotocol.h" | awk -v N=3 '{print $N}') - - MULTI_VERSION=$MAJOR_VERSION.$MINOR_VERSION.$REVISION_VERSION.$PATCH_VERSION -else - MULTI_VERSION= -fi - -if [ -e "$BUILD_PATH/$PROJECT_NAME.hex" ]; then - cp "$BUILD_PATH/$PROJECT_NAME.hex" "$BUILD_PATH/multi-$MULTI_TYPE-$MULTI_VERSION.hex" -fi - -if [ -e "$BUILD_PATH/$PROJECT_NAME.bin" ]; then - cp "$BUILD_PATH/$PROJECT_NAME.bin" "$BUILD_PATH/multi-$MULTI_TYPE-$MULTI_VERSION.bin" -fi - -if [ $# -eq 5 ]; then - if [ $EXPORT_FLAG == "EXPORT" ]; then - - if [ -e "$BUILD_PATH/$PROJECT_NAME.hex" ]; then - cp "$BUILD_PATH/$PROJECT_NAME.hex" "$SKETCH_PATH/multi-$MULTI_TYPE-$MULTI_VERSION.hex" - fi - if [ -e "$BUILD_PATH/$PROJECT_NAME.bin" ]; then - cp "$BUILD_PATH/$PROJECT_NAME.bin" "$SKETCH_PATH/multi-$MULTI_TYPE-$MULTI_VERSION.bin" - fi - - if [ -e "$SKETCH_PATH/multi-$MULTI_TYPE.hex" ]; then - rm "$SKETCH_PATH/multi-$MULTI_TYPE.hex" - fi - if [ -e "$SKETCH_PATH/multi-$MULTI_TYPE.bin" ]; then - rm "$SKETCH_PATH/multi-$MULTI_TYPE.bin" - fi - fi -fi diff --git a/BootLoaders/Boards/orangerx/tools/linux64/do_version b/BootLoaders/Boards/orangerx/tools/linux64/do_version deleted file mode 100755 index 184015b..0000000 --- a/BootLoaders/Boards/orangerx/tools/linux64/do_version +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/bash - -BUILD_PATH=$1 -PROJECT_NAME=$2 -SKETCH_PATH=$3 -MULTI_BOARD=$4 -EXPORT_FLAG=$5 - -MULTI_TYPE=orx - -if [ -e "$BUILD_PATH/sketch/Multiprotocol.h" ]; then - MAJOR_VERSION=$(grep "VERSION_MAJOR" "$BUILD_PATH/sketch/Multiprotocol.h" | awk -v N=3 '{print $N}') - MINOR_VERSION=$(grep "VERSION_MINOR" "$BUILD_PATH/sketch/Multiprotocol.h" | awk -v N=3 '{print $N}') - REVISION_VERSION=$(grep "VERSION_REVISION" "$BUILD_PATH/sketch/Multiprotocol.h" | awk -v N=3 '{print $N}') - PATCH_VERSION=$(grep "VERSION_PATCH" "$BUILD_PATH/sketch/Multiprotocol.h" | awk -v N=3 '{print $N}') - - MULTI_VERSION=$MAJOR_VERSION.$MINOR_VERSION.$REVISION_VERSION.$PATCH_VERSION -else - MULTI_VERSION= -fi - -if [ -e "$BUILD_PATH/$PROJECT_NAME.hex" ]; then - cp "$BUILD_PATH/$PROJECT_NAME.hex" "$BUILD_PATH/multi-$MULTI_TYPE-$MULTI_VERSION.hex" -fi - -if [ -e "$BUILD_PATH/$PROJECT_NAME.bin" ]; then - cp "$BUILD_PATH/$PROJECT_NAME.bin" "$BUILD_PATH/multi-$MULTI_TYPE-$MULTI_VERSION.bin" -fi - -if [ $# -eq 5 ]; then - if [ $EXPORT_FLAG == "EXPORT" ]; then - - if [ -e "$BUILD_PATH/$PROJECT_NAME.hex" ]; then - cp "$BUILD_PATH/$PROJECT_NAME.hex" "$SKETCH_PATH/multi-$MULTI_TYPE-$MULTI_VERSION.hex" - fi - if [ -e "$BUILD_PATH/$PROJECT_NAME.bin" ]; then - cp "$BUILD_PATH/$PROJECT_NAME.bin" "$SKETCH_PATH/multi-$MULTI_TYPE-$MULTI_VERSION.bin" - fi - - if [ -e "$SKETCH_PATH/multi-$MULTI_TYPE.hex" ]; then - rm "$SKETCH_PATH/multi-$MULTI_TYPE.hex" - fi - if [ -e "$SKETCH_PATH/multi-$MULTI_TYPE.bin" ]; then - rm "$SKETCH_PATH/multi-$MULTI_TYPE.bin" - fi - fi -fi diff --git a/BootLoaders/Boards/orangerx/tools/macosx/do_version b/BootLoaders/Boards/orangerx/tools/macosx/do_version deleted file mode 100755 index 184015b..0000000 --- a/BootLoaders/Boards/orangerx/tools/macosx/do_version +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/bash - -BUILD_PATH=$1 -PROJECT_NAME=$2 -SKETCH_PATH=$3 -MULTI_BOARD=$4 -EXPORT_FLAG=$5 - -MULTI_TYPE=orx - -if [ -e "$BUILD_PATH/sketch/Multiprotocol.h" ]; then - MAJOR_VERSION=$(grep "VERSION_MAJOR" "$BUILD_PATH/sketch/Multiprotocol.h" | awk -v N=3 '{print $N}') - MINOR_VERSION=$(grep "VERSION_MINOR" "$BUILD_PATH/sketch/Multiprotocol.h" | awk -v N=3 '{print $N}') - REVISION_VERSION=$(grep "VERSION_REVISION" "$BUILD_PATH/sketch/Multiprotocol.h" | awk -v N=3 '{print $N}') - PATCH_VERSION=$(grep "VERSION_PATCH" "$BUILD_PATH/sketch/Multiprotocol.h" | awk -v N=3 '{print $N}') - - MULTI_VERSION=$MAJOR_VERSION.$MINOR_VERSION.$REVISION_VERSION.$PATCH_VERSION -else - MULTI_VERSION= -fi - -if [ -e "$BUILD_PATH/$PROJECT_NAME.hex" ]; then - cp "$BUILD_PATH/$PROJECT_NAME.hex" "$BUILD_PATH/multi-$MULTI_TYPE-$MULTI_VERSION.hex" -fi - -if [ -e "$BUILD_PATH/$PROJECT_NAME.bin" ]; then - cp "$BUILD_PATH/$PROJECT_NAME.bin" "$BUILD_PATH/multi-$MULTI_TYPE-$MULTI_VERSION.bin" -fi - -if [ $# -eq 5 ]; then - if [ $EXPORT_FLAG == "EXPORT" ]; then - - if [ -e "$BUILD_PATH/$PROJECT_NAME.hex" ]; then - cp "$BUILD_PATH/$PROJECT_NAME.hex" "$SKETCH_PATH/multi-$MULTI_TYPE-$MULTI_VERSION.hex" - fi - if [ -e "$BUILD_PATH/$PROJECT_NAME.bin" ]; then - cp "$BUILD_PATH/$PROJECT_NAME.bin" "$SKETCH_PATH/multi-$MULTI_TYPE-$MULTI_VERSION.bin" - fi - - if [ -e "$SKETCH_PATH/multi-$MULTI_TYPE.hex" ]; then - rm "$SKETCH_PATH/multi-$MULTI_TYPE.hex" - fi - if [ -e "$SKETCH_PATH/multi-$MULTI_TYPE.bin" ]; then - rm "$SKETCH_PATH/multi-$MULTI_TYPE.bin" - fi - fi -fi diff --git a/BootLoaders/Boards/orangerx/tools/win/do_version.bat b/BootLoaders/Boards/orangerx/tools/win/do_version.bat deleted file mode 100644 index 3da9306..0000000 --- a/BootLoaders/Boards/orangerx/tools/win/do_version.bat +++ /dev/null @@ -1,67 +0,0 @@ -@ECHO OFF -SETLOCAL EnableDelayedExpansion - -REM SET DEBUG=1 - -SET BUILD_PATH=%1 -SET PROJECT_NAME=%2 -SET SKETCH_PATH=%3 -SET MULTI_BOARD=%4 -SET EXPORT_FLAG=%5 - -REM Remove double-quotes from the paths -SET BUILD_PATH=%BUILD_PATH:"=% -SET SKETCH_PATH=%SKETCH_PATH:"=% - -IF DEFINED DEBUG ( - ECHO Sketch Path: %SKETCH_PATH% - ECHO Multi board: %MULTI_BOARD% -) - -SET MULTI_TYPE=orx - -IF EXIST "%1\sketch\Multiprotocol.h" ( - REM ECHO Getting Multi-MODULE firmware version from "%1\sketch\Multiprotocol.h" - FOR /F "tokens=* usebackq skip=2" %%A in (`find "#define VERSION_MAJOR" "%1\sketch\Multiprotocol.h"`) DO FOR /F "tokens=3" %%i in ("%%A") do SET MAJOR_VERSION=%%i - FOR /F "tokens=* usebackq skip=2" %%B in (`find "#define VERSION_MINOR" "%1\sketch\Multiprotocol.h"`) DO FOR /F "tokens=3" %%i in ("%%B") do SET MINOR_VERSION=%%i - FOR /F "tokens=* usebackq skip=2" %%C in (`find "#define VERSION_REVISION" "%1\sketch\Multiprotocol.h"`) DO FOR /F "tokens=3" %%i in ("%%C") do SET REVISION_VERSION=%%i - FOR /F "tokens=* usebackq skip=2" %%D in (`find "#define VERSION_PATCH_LEVEL" "%1\sketch\Multiprotocol.h"`) DO FOR /F "tokens=3" %%i in ("%%D") do SET PATCH_VERSION=%%i - SET MULTI_VER=!MAJOR_VERSION!.!MINOR_VERSION!.!REVISION_VERSION!.!PATCH_VERSION! -) ELSE ( - SET MULTI_VER= -) - -IF DEFINED DEBUG ECHO Multi-MODULE firmware version: %MULTI_VER% - -REM Copy the compiled file to the sketch folder with the version number in the file name -IF EXIST "%BUILD_PATH%\%PROJECT_NAME%.hex" ( - IF DEFINED DEBUG ECHO COPY "%BUILD_PATH%\%PROJECT_NAME%.hex" "%BUILD_PATH%\multi-%MULTI_TYPE%-%MULTI_VER%.hex" /Y - COPY "%BUILD_PATH%\%PROJECT_NAME%.hex" "%BUILD_PATH%\multi-%MULTI_TYPE%-%MULTI_VER%.hex" /Y >NUL -) - -IF EXIST "%BUILD_PATH%\%PROJECT_NAME%.bin" ( - IF DEFINED DEBUG ECHO COPY "%BUILD_PATH%\%PROJECT_NAME%.bin" "%BUILD_PATH%\multi-%MULTI_TYPE%-%MULTI_VER%.bin" /Y - COPY "%BUILD_PATH%\%PROJECT_NAME%.bin" "%BUILD_PATH%\multi-%MULTI_TYPE%-%MULTI_VER%.bin" /Y >NUL -) - -IF "%EXPORT_FLAG%"=="EXPORT" ( -REM Copy the compiled file to the sketch folder with the version number in the file name - IF EXIST "%BUILD_PATH%\%PROJECT_NAME%.hex" ( - IF DEFINED DEBUG ECHO COPY "%BUILD_PATH%\%PROJECT_NAME%.hex" "%SKETCH_PATH%\multi-%MULTI_TYPE%-%MULTI_VER%.hex" /Y - COPY "%BUILD_PATH%\%PROJECT_NAME%.hex" "%SKETCH_PATH%\multi-%MULTI_TYPE%-%MULTI_VER%.hex" /Y >NUL - ) - - IF EXIST "%BUILD_PATH%\%PROJECT_NAME%.bin" ( - IF DEFINED DEBUG ECHO COPY "%BUILD_PATH%\%PROJECT_NAME%.bin" "%SKETCH_PATH%\multi-%MULTI_TYPE%-%MULTI_VER%.bin" /Y - COPY "%BUILD_PATH%\%PROJECT_NAME%.bin" "%SKETCH_PATH%\multi-%MULTI_TYPE%-%MULTI_VER%.bin" /Y >NUL - ) - - IF EXIST "%SKETCH_PATH%\multi-%MULTI_TYPE%.bin" ( - IF DEFINED DEBUG ECHO DEL "%SKETCH_PATH%\multi-%MULTI_TYPE%.bin" - DEL "%SKETCH_PATH%\multi-%MULTI_TYPE%.bin" >NUL - ) - IF EXIST "%SKETCH_PATH%\multi-%MULTI_TYPE%.hex" ( - IF DEFINED DEBUG ECHO DEL "%SKETCH_PATH%\multi-%MULTI_TYPE%.hex" - DEL "%SKETCH_PATH%\multi-%MULTI_TYPE%.hex" >NUL - ) -) diff --git a/BootLoaders/Boards/stm32/boards.txt b/BootLoaders/Boards/stm32/boards.txt index 0163101..74ada39 100644 --- a/BootLoaders/Boards/stm32/boards.txt +++ b/BootLoaders/Boards/stm32/boards.txt @@ -16,7 +16,7 @@ multistm32f103c.pid.0=0x0004 multistm32f103c.build.variant=generic_stm32f103c multistm32f103c.build.vect=VECT_TAB_ADDR=0x8000000 multistm32f103c.build.core=maple -multistm32f103c.build.board=MULTI_STM32_FLASH_FROM_TX +multistm32f103c.build.board=MULTI_STM32_FLASH_FROM_TX=103 multistm32f103c.upload.use_1200bps_touch=false multistm32f103c.upload.file_type=bin multistm32f103c.upload.auto_reset=true @@ -37,20 +37,20 @@ multistm32f103c.bootloader.tool=serial_upload #---------------------------- UPLOAD METHODS --------------------------- multistm32f103c.menu.upload_method.TxFlashMethod=Flash from Tx +multistm32f103c.menu.upload_method.TxFlashMethod.build.board=MULTI_STM32_FLASH_FROM_TX=103 multistm32f103c.menu.upload_method.TxFlashMethod.upload.tool=tx_upload multistm32f103c.menu.upload_method.TxFlashMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER multistm32f103c.menu.upload_method.TxFlashMethod.build.vect=VECT_TAB_ADDR=0x8002000 multistm32f103c.menu.upload_method.TxFlashMethod.build.ldscript=ld/bootloader_20.ld -multistm32f103c.menu.upload_method.TxFlashMethod.build.board=MULTI_STM32_FLASH_FROM_TX multistm32f103c.menu.upload_method.TxFlashMethod.bootloader.file=Multi4in1/StmMultiBoot.bin multistm32f103c.menu.upload_method.DFUUploadMethod=Upload via USB +multistm32f103c.menu.upload_method.DFUUploadMethod.build.board=MULTI_STM32_NO_BOOT=103 multistm32f103c.menu.upload_method.DFUUploadMethod.upload.protocol=maple_dfu multistm32f103c.menu.upload_method.DFUUploadMethod.upload.tool=maple_upload multistm32f103c.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER multistm32f103c.menu.upload_method.DFUUploadMethod.build.vect=VECT_TAB_ADDR=0x8002000 multistm32f103c.menu.upload_method.DFUUploadMethod.build.ldscript=ld/bootloader_20.ld -multistm32f103c.menu.upload_method.DFUUploadMethod.build.board=MULTI_STM32_NO_BOOT multistm32f103c.menu.upload_method.DFUUploadMethod.upload.usbID=1EAF:0003 multistm32f103c.menu.upload_method.DFUUploadMethod.upload.altID=2 multistm32f103c.menu.upload_method.DFUUploadMethod.bootloader.file=Multi4in1/StmMultiUSB.bin @@ -59,6 +59,6 @@ multistm32f103c.menu.upload_method.serialMethod=Upload via Serial (FTDI) multistm32f103c.menu.upload_method.serialMethod.upload.protocol=maple_serial multistm32f103c.menu.upload_method.serialMethod.upload.tool=serial_upload multistm32f103c.menu.upload_method.serialMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG -multistm32f103c.menu.upload_method.serialMethod.build.board=MULTI_STM32_NO_BOOT +multistm32f103c.menu.upload_method.serialMethod.build.board=MULTI_STM32_NO_BOOT=103 ############################################################## diff --git a/BootLoaders/Boards/stm32/cores/maple/HardwareSerial.cpp b/BootLoaders/Boards/stm32/cores/maple/HardwareSerial.cpp index c993bdf..024efbc 100644 --- a/BootLoaders/Boards/stm32/cores/maple/HardwareSerial.cpp +++ b/BootLoaders/Boards/stm32/cores/maple/HardwareSerial.cpp @@ -193,7 +193,8 @@ size_t HardwareSerial::write(unsigned char ch) { return 1; } +/* edogaldo: Waits for the transmission of outgoing serial data to complete (Arduino 1.0 api specs) */ void HardwareSerial::flush(void) { - usart_reset_rx(this->usart_device); - usart_reset_tx(this->usart_device); + while(!rb_is_empty(this->usart_device->wb)); // wait for TX buffer empty + while(!((this->usart_device->regs->SR) & (1<dev, (uint8)channel); } + +void HardwareTimer::enableDMA(int channel) { + timer_dma_enable_req(this->dev, (uint8)channel); +} + +void HardwareTimer::disableDMA(int channel) { + timer_dma_disable_req(this->dev, (uint8)channel); +} + void HardwareTimer::refresh(void) { timer_generate_update(this->dev); } +void HardwareTimer::setMasterModeTrGo(uint32_t mode) { + this->dev->regs.bas->CR2 &= ~TIMER_CR2_MMS; + this->dev->regs.bas->CR2 |= mode; +} + /* CARLOS Changes to add encoder mode.*/ //direction of movement. (to be better described). diff --git a/BootLoaders/Boards/stm32/cores/maple/HardwareTimer.h b/BootLoaders/Boards/stm32/cores/maple/HardwareTimer.h index 45272ec..bb40dba 100644 --- a/BootLoaders/Boards/stm32/cores/maple/HardwareTimer.h +++ b/BootLoaders/Boards/stm32/cores/maple/HardwareTimer.h @@ -177,7 +177,8 @@ public: * This interrupt handler will be called when the timer's counter * reaches the given channel compare value. * - * @param channel the channel to attach the ISR to, from 1 to 4. + * @param channel the channel to attach the ISR to, from 0 to 4. + * Channel 0 is for overflow interrupt (update interrupt). * @param handler The ISR to attach to the given channel. * @see voidFuncPtr */ @@ -189,7 +190,8 @@ public: * * The handler will no longer be called by this timer. * - * @param channel the channel whose interrupt to detach, from 1 to 4. + * @param channel the channel whose interrupt to detach, from 0 to 4. + * Channel 0 is for overflow interrupt (update interrupt). * @see HardwareTimer::attachInterrupt() */ void detachInterrupt(int channel); @@ -209,6 +211,23 @@ public: */ void refresh(void); + // SYFRE + /** + * @brief Set the Master mode TRGO signal + * These bits allow to select the information to be sent in master mode to slave timers for + * synchronization (TRGO). + * mode: + * TIMER_CR2_MMS_RESET + * TIMER_CR2_MMS_ENABLE + * TIMER_CR2_MMS_UPDATE + * TIMER_CR2_MMS_COMPARE_PULSE + * TIMER_CR2_MMS_COMPARE_OC1REF + * TIMER_CR2_MMS_COMPARE_OC2REF + * TIMER_CR2_MMS_COMPARE_OC3REF + * TIMER_CR2_MMS_COMPARE_OC4REF + */ + void setMasterModeTrGo(uint32_t mode); + //CARLOS. /* added these functions to make sense for the encoder mode. @@ -228,6 +247,12 @@ public: /* Escape hatch */ + /** + * @brief Enable/disable DMA request for the input channel. + */ + void enableDMA(int channel); + void disableDMA(int channel); + /** * @brief Get a pointer to the underlying libmaple timer_dev for * this HardwareTimer instance. diff --git a/BootLoaders/Boards/stm32/cores/maple/IPAddress.cpp b/BootLoaders/Boards/stm32/cores/maple/IPAddress.cpp index b196aad..297307e 100644 --- a/BootLoaders/Boards/stm32/cores/maple/IPAddress.cpp +++ b/BootLoaders/Boards/stm32/cores/maple/IPAddress.cpp @@ -44,6 +44,48 @@ IPAddress::IPAddress(const uint8_t *address) memcpy(_address.bytes, address, sizeof(_address.bytes)); } +bool IPAddress::fromString(const char *address) +{ + // TODO: add support for "a", "a.b", "a.b.c" formats + + uint16_t acc = 0; // Accumulator + uint8_t dots = 0; + + while (*address) + { + char c = *address++; + if (c >= '0' && c <= '9') + { + acc = acc * 10 + (c - '0'); + if (acc > 255) { + // Value out of [0..255] range + return false; + } + } + else if (c == '.') + { + if (dots == 3) { + // Too much dots (there must be 3 dots) + return false; + } + _address.bytes[dots++] = acc; + acc = 0; + } + else + { + // Invalid char + return false; + } + } + + if (dots != 3) { + // Too few dots (there must be 3 dots) + return false; + } + _address.bytes[3] = acc; + return true; +} + IPAddress& IPAddress::operator=(const uint8_t *address) { memcpy(_address.bytes, address, sizeof(_address.bytes)); diff --git a/BootLoaders/Boards/stm32/cores/maple/IPAddress.h b/BootLoaders/Boards/stm32/cores/maple/IPAddress.h index 4ef167e..271b240 100644 --- a/BootLoaders/Boards/stm32/cores/maple/IPAddress.h +++ b/BootLoaders/Boards/stm32/cores/maple/IPAddress.h @@ -46,6 +46,9 @@ public: IPAddress(uint32_t address); IPAddress(const uint8_t *address); + bool fromString(const char *address); + bool fromString(const String &address) { return fromString(address.c_str()); } + // Overloaded cast operator to allow IPAddress objects to be used where a pointer // to a four-byte uint8_t array is expected operator uint32_t() const { return _address.dword; }; diff --git a/BootLoaders/Boards/stm32/cores/maple/Print.cpp b/BootLoaders/Boards/stm32/cores/maple/Print.cpp index 9c924d1..0a71cf0 100644 --- a/BootLoaders/Boards/stm32/cores/maple/Print.cpp +++ b/BootLoaders/Boards/stm32/cores/maple/Print.cpp @@ -99,10 +99,6 @@ size_t Print::print(unsigned long n, int base) { } size_t Print::print(long long n, int base) { - if (base == BYTE) - { - return write((uint8)n); - } if (n < 0) { print('-'); n = -n; @@ -111,19 +107,23 @@ size_t Print::print(long long n, int base) { } size_t Print::print(unsigned long long n, int base) { -size_t c=0; - if (base == BYTE) { - c= write((uint8)n); - } else { - c= printNumber(n, base); - } - return c; + return printNumber(n, base); } size_t Print::print(double n, int digits) { return printFloat(n, digits); } +size_t Print::print(const __FlashStringHelper *ifsh) +{ + return print(reinterpret_cast(ifsh)); +} + +size_t Print::print(const Printable& x) +{ + return x.printTo(*this); +} + size_t Print::println(void) { size_t n = print('\r'); @@ -198,6 +198,20 @@ size_t Print::println(double n, int digits) { return s; } +size_t Print::println(const __FlashStringHelper *ifsh) +{ + size_t n = print(ifsh); + n += println(); + return n; +} + +size_t Print::println(const Printable& x) +{ + size_t n = print(x); + n += println(); + return n; +} + #ifdef SUPPORTS_PRINTF #include #include diff --git a/BootLoaders/Boards/stm32/cores/maple/Print.h b/BootLoaders/Boards/stm32/cores/maple/Print.h index 5961a02..f265fac 100644 --- a/BootLoaders/Boards/stm32/cores/maple/Print.h +++ b/BootLoaders/Boards/stm32/cores/maple/Print.h @@ -25,9 +25,9 @@ #include #include "WString.h" +#include "Printable.h" enum { - BYTE = 0, BIN = 2, OCT = 8, DEC = 10, @@ -51,6 +51,8 @@ public: size_t print(long long, int=DEC); size_t print(unsigned long long, int=DEC); size_t print(double, int=2); + size_t print(const __FlashStringHelper *); + size_t print(const Printable&); size_t println(void); size_t println(const String &s); size_t println(char); @@ -63,6 +65,8 @@ public: size_t println(long long, int=DEC); size_t println(unsigned long long, int=DEC); size_t println(double, int=2); + size_t println(const __FlashStringHelper *); + size_t println(const Printable&); #ifdef SUPPORTS_PRINTF // Roger Clark. Work in progress to add printf support int printf(const char * format, ...); diff --git a/BootLoaders/Boards/stm32/cores/maple/Stream.cpp b/BootLoaders/Boards/stm32/cores/maple/Stream.cpp index 9c581be..991fa87 100644 --- a/BootLoaders/Boards/stm32/cores/maple/Stream.cpp +++ b/BootLoaders/Boards/stm32/cores/maple/Stream.cpp @@ -268,3 +268,68 @@ String Stream::readStringUntil(char terminator) return ret; } + +int Stream::findMulti( struct Stream::MultiTarget *targets, int tCount) { + // any zero length target string automatically matches and would make + // a mess of the rest of the algorithm. + for (struct MultiTarget *t = targets; t < targets+tCount; ++t) { + if (t->len <= 0) + return t - targets; + } + + while (1) { + int c = timedRead(); + if (c < 0) + return -1; + + for (struct MultiTarget *t = targets; t < targets+tCount; ++t) { + // the simple case is if we match, deal with that first. + if (c == t->str[t->index]) { + if (++t->index == t->len) + return t - targets; + else + continue; + } + + // if not we need to walk back and see if we could have matched further + // down the stream (ie '1112' doesn't match the first position in '11112' + // but it will match the second position so we can't just reset the current + // index to 0 when we find a mismatch. + if (t->index == 0) + continue; + + int origIndex = t->index; + do { + --t->index; + // first check if current char works against the new current index + if (c != t->str[t->index]) + continue; + + // if it's the only char then we're good, nothing more to check + if (t->index == 0) { + t->index++; + break; + } + + // otherwise we need to check the rest of the found string + int diff = origIndex - t->index; + size_t i; + for (i = 0; i < t->index; ++i) { + if (t->str[i] != t->str[i + diff]) + break; + } + + // if we successfully got through the previous loop then our current + // index is good. + if (i == t->index) { + t->index++; + break; + } + + // otherwise we just try the next index + } while (t->index); + } + } + // unreachable + return -1; +} diff --git a/BootLoaders/Boards/stm32/cores/maple/Stream.h b/BootLoaders/Boards/stm32/cores/maple/Stream.h index 5cf5ddf..abdcd17 100644 --- a/BootLoaders/Boards/stm32/cores/maple/Stream.h +++ b/BootLoaders/Boards/stm32/cores/maple/Stream.h @@ -55,6 +55,7 @@ class Stream : public Print // parsing methods void setTimeout(unsigned long timeout); // sets maximum milliseconds to wait for stream data, default is 1 second + unsigned long getTimeout(void) { return _timeout; } bool find(char *target); // reads data from the stream until the target string is found bool find(uint8_t *target) { return find ((char *)target); } @@ -64,6 +65,8 @@ class Stream : public Print bool find(uint8_t *target, size_t length) { return find ((char *)target, length); } // returns true if target string is found, false if timed out + bool find(char target) { return find (&target, 1); } + bool findUntil(char *target, char *terminator); // as find but search ends if the terminator string is found bool findUntil(uint8_t *target, char *terminator) { return findUntil((char *)target, terminator); } @@ -97,6 +100,16 @@ class Stream : public Print // this allows format characters (typically commas) in values to be ignored float parseFloat(char skipChar); // as above but the given skipChar is ignored + + struct MultiTarget { + const char *str; // string you're searching for + size_t len; // length of string you're searching for + size_t index; // index used by the search routine. + }; + + // This allows you to search for an arbitrary number of strings. + // Returns index of the target that is found first or -1 if timeout occurs. + int findMulti(struct MultiTarget *targets, int tCount); }; #endif diff --git a/BootLoaders/Boards/stm32/cores/maple/WString.cpp b/BootLoaders/Boards/stm32/cores/maple/WString.cpp index e1d60f4..5332982 100644 --- a/BootLoaders/Boards/stm32/cores/maple/WString.cpp +++ b/BootLoaders/Boards/stm32/cores/maple/WString.cpp @@ -195,7 +195,7 @@ String & String::copy(const __FlashStringHelper *pstr, unsigned int length) void String::move(String &rhs) { if (buffer) { - if (capacity >= rhs.len) { + if (rhs && capacity >= rhs.len) { strcpy(buffer, rhs.buffer); len = rhs.len; rhs.len = 0; diff --git a/BootLoaders/Boards/stm32/cores/maple/WString.h b/BootLoaders/Boards/stm32/cores/maple/WString.h index b047980..0cc27ab 100644 --- a/BootLoaders/Boards/stm32/cores/maple/WString.h +++ b/BootLoaders/Boards/stm32/cores/maple/WString.h @@ -161,6 +161,10 @@ public: void toCharArray(char *buf, unsigned int bufsize, unsigned int index=0) const {getBytes((unsigned char *)buf, bufsize, index);} const char * c_str() const { return buffer; } + char* begin() { return buffer; } + char* end() { return buffer + length(); } + const char* begin() const { return c_str(); } + const char* end() const { return c_str() + length(); } // search int indexOf( char ch ) const; diff --git a/BootLoaders/Boards/stm32/cores/maple/io.h b/BootLoaders/Boards/stm32/cores/maple/io.h index 9b322a2..7b82285 100644 --- a/BootLoaders/Boards/stm32/cores/maple/io.h +++ b/BootLoaders/Boards/stm32/cores/maple/io.h @@ -160,4 +160,6 @@ uint16 analogRead(uint8 pin); */ void shiftOut(uint8 dataPin, uint8 clockPin, uint8 bitOrder, uint8 value); +uint32 shiftIn( uint32 ulDataPin, uint32 ulClockPin, uint32 ulBitOrder ); + #endif diff --git a/BootLoaders/Boards/stm32/cores/maple/itoa.c b/BootLoaders/Boards/stm32/cores/maple/itoa.c index fc35766..33efd14 100644 --- a/BootLoaders/Boards/stm32/cores/maple/itoa.c +++ b/BootLoaders/Boards/stm32/cores/maple/itoa.c @@ -120,8 +120,12 @@ extern char* ltoa( long value, char *string, int radix ) return string; } - -extern char* utoa( unsigned long value, char *string, int radix ) +#if __GNUC__ > 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ > 9 || \ + (__GNUC_MINOR__ == 9 && __GNUC_PATCHLEVEL__ > 2))) +extern char* utoa( unsigned value, char *string, int radix ) +#else +extern char* utoa( unsigned int value, char *string, int radix ) +#endif { return ultoa( value, string, radix ) ; } diff --git a/BootLoaders/Boards/stm32/cores/maple/itoa.h b/BootLoaders/Boards/stm32/cores/maple/itoa.h index 59af109..9997b65 100644 --- a/BootLoaders/Boards/stm32/cores/maple/itoa.h +++ b/BootLoaders/Boards/stm32/cores/maple/itoa.h @@ -31,7 +31,12 @@ extern void itoa( int n, char s[] ) ; extern char* itoa( int value, char *string, int radix ) ; extern char* ltoa( long value, char *string, int radix ) ; -extern char* utoa( unsigned long value, char *string, int radix ) ; +#if __GNUC__ > 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ > 9 || \ + (__GNUC_MINOR__ == 9 && __GNUC_PATCHLEVEL__ > 2))) +extern char* utoa( unsigned value, char *string, int radix ) ; +#else +extern char* utoa( unsigned int value, char *string, int radix ) ; +#endif extern char* ultoa( unsigned long value, char *string, int radix ) ; #endif /* 0 */ diff --git a/BootLoaders/Boards/stm32/cores/maple/libmaple/adc.c b/BootLoaders/Boards/stm32/cores/maple/libmaple/adc.c index 7c48ee4..416cfaa 100644 --- a/BootLoaders/Boards/stm32/cores/maple/libmaple/adc.c +++ b/BootLoaders/Boards/stm32/cores/maple/libmaple/adc.c @@ -59,6 +59,7 @@ void adc_set_extsel(adc_dev *dev, adc_extsel_event event) { uint32 cr2 = dev->regs->CR2; cr2 &= ~ADC_CR2_EXTSEL; cr2 |= event; + cr2 |= ADC_CR2_EXTTRIG; dev->regs->CR2 = cr2; } diff --git a/BootLoaders/Boards/stm32/cores/maple/libmaple/adc_f1.c b/BootLoaders/Boards/stm32/cores/maple/libmaple/adc_f1.c index d099f6d..5305b02 100644 --- a/BootLoaders/Boards/stm32/cores/maple/libmaple/adc_f1.c +++ b/BootLoaders/Boards/stm32/cores/maple/libmaple/adc_f1.c @@ -203,7 +203,7 @@ void adc_foreach(void (*fn)(adc_dev*)) { #endif } -void adc_config_gpio(adc_dev *ignored, gpio_dev *gdev, uint8 bit) { +void adc_config_gpio(adc_dev *ignored __attribute__((unused)), gpio_dev *gdev, uint8 bit) { gpio_set_mode(gdev, bit, GPIO_INPUT_ANALOG); } diff --git a/BootLoaders/Boards/stm32/cores/maple/libmaple/dma_f1.c b/BootLoaders/Boards/stm32/cores/maple/libmaple/dma_f1.c index 6400d15..c7c3c00 100644 --- a/BootLoaders/Boards/stm32/cores/maple/libmaple/dma_f1.c +++ b/BootLoaders/Boards/stm32/cores/maple/libmaple/dma_f1.c @@ -341,7 +341,6 @@ void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *addr) { * @see dma_attach_interrupt() * @see dma_enable() */ -__deprecated void dma_setup_transfer(dma_dev *dev, dma_channel channel, __io void *peripheral_address, diff --git a/BootLoaders/Boards/stm32/cores/maple/libmaple/gpio_f1.c b/BootLoaders/Boards/stm32/cores/maple/libmaple/gpio_f1.c index ecd015d..6de16f5 100644 --- a/BootLoaders/Boards/stm32/cores/maple/libmaple/gpio_f1.c +++ b/BootLoaders/Boards/stm32/cores/maple/libmaple/gpio_f1.c @@ -142,7 +142,6 @@ gpio_pin_mode gpio_get_mode(gpio_dev *dev, uint8 pin) { gpio_reg_map *regs = dev->regs; __io uint32 *cr = ®s->CRL + (pin >> 3); uint32 shift = (pin & 0x7) * 4; - uint32 tmp = *cr; uint32 crMode = (*cr>>shift) & 0x0F; diff --git a/BootLoaders/Boards/stm32/cores/maple/libmaple/spi.c b/BootLoaders/Boards/stm32/cores/maple/libmaple/spi.c index 1020c5b..e0ee90d 100644 --- a/BootLoaders/Boards/stm32/cores/maple/libmaple/spi.c +++ b/BootLoaders/Boards/stm32/cores/maple/libmaple/spi.c @@ -84,7 +84,7 @@ void spi_slave_enable(spi_dev *dev, spi_mode mode, uint32 flags) { } /** - * @brief Nonblocking SPI transmit. + * @brief Blocking SPI transmit. * @param dev SPI port to use for transmission * @param buf Buffer to transmit. The sizeof buf's elements are * inferred from dev's data frame format (i.e., are @@ -93,15 +93,21 @@ void spi_slave_enable(spi_dev *dev, spi_mode mode, uint32 flags) { * @return Number of elements transmitted. */ uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len) { - uint32 txed = 0; - uint8 byte_frame = spi_dff(dev) == SPI_DFF_8_BIT; - while (spi_is_tx_empty(dev) && (txed < len)) { - if (byte_frame) { - dev->regs->DR = ((const uint8*)buf)[txed++]; - } else { - dev->regs->DR = ((const uint16*)buf)[txed++]; - } - } + uint32 txed = len; + spi_reg_map *regs = dev->regs; + if ( spi_dff(dev) == SPI_DFF_8_BIT ) { + const uint8 * dp8 = (const uint8*)buf; + while ( len-- ) { + while ( (regs->SR & SPI_SR_TXE)==0 ) ; //while ( spi_is_tx_empty(dev)==0 ); // wait Tx to be empty + regs->DR = *dp8++; + } + } else { + const uint16 * dp16 = (const uint16*)buf; + while ( len-- ) { + while ( (regs->SR & SPI_SR_TXE)==0 ) ; //while ( spi_is_tx_empty(dev)==0 ); // wait Tx to be empty + regs->DR = *dp16++; + } + } return txed; } diff --git a/BootLoaders/Boards/stm32/cores/maple/libmaple/spi_f1.c b/BootLoaders/Boards/stm32/cores/maple/libmaple/spi_f1.c index bbea5a4..d920761 100644 --- a/BootLoaders/Boards/stm32/cores/maple/libmaple/spi_f1.c +++ b/BootLoaders/Boards/stm32/cores/maple/libmaple/spi_f1.c @@ -54,7 +54,7 @@ spi_dev *SPI3 = &spi3; * Routines */ -void spi_config_gpios(spi_dev *ignored, +void spi_config_gpios(spi_dev *ignored __attribute__((unused)), uint8 as_master, gpio_dev *nss_dev, uint8 nss_bit, diff --git a/BootLoaders/Boards/stm32/cores/maple/libmaple/timer.c b/BootLoaders/Boards/stm32/cores/maple/libmaple/timer.c index d548d14..393a19b 100644 --- a/BootLoaders/Boards/stm32/cores/maple/libmaple/timer.c +++ b/BootLoaders/Boards/stm32/cores/maple/libmaple/timer.c @@ -327,7 +327,7 @@ static void output_compare_mode(timer_dev *dev, uint8 channel) { } //added by CARLOS. -static void encoder_mode(timer_dev *dev, uint8 channel) { +static void encoder_mode(timer_dev *dev, uint8 channel __attribute__((unused))) { //prescaler. //(dev->regs).gen->PSC = 1; diff --git a/BootLoaders/Boards/stm32/cores/maple/libmaple/usart_f1.c b/BootLoaders/Boards/stm32/cores/maple/libmaple/usart_f1.c index 96d16b0..5fee3a8 100644 --- a/BootLoaders/Boards/stm32/cores/maple/libmaple/usart_f1.c +++ b/BootLoaders/Boards/stm32/cores/maple/libmaple/usart_f1.c @@ -203,15 +203,15 @@ void usart_foreach(void (*fn)(usart_dev*)) { void __irq_usart1(void) { usart_irq(&usart1_rb, &usart1_wb, USART1_BASE); } +/* +void __irq_usart2(void) { + usart_irq(&usart2_rb, &usart2_wb, USART2_BASE); +} -//void __irq_usart2(void) { - // usart_irq(&usart2_rb, &usart2_wb, USART2_BASE); -//} - -//void __irq_usart3(void) { - // usart_irq(&usart3_rb, &usart3_wb, USART3_BASE); -//} - +void __irq_usart3(void) { + usart_irq(&usart3_rb, &usart3_wb, USART3_BASE); +} +*/ #ifdef STM32_HIGH_DENSITY void __irq_uart4(void) { usart_irq(&uart4_rb, &uart4_wb, UART4_BASE); diff --git a/BootLoaders/Boards/stm32/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c b/BootLoaders/Boards/stm32/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c index 448c05d..cba050f 100644 --- a/BootLoaders/Boards/stm32/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c +++ b/BootLoaders/Boards/stm32/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c @@ -62,8 +62,8 @@ #if !(defined(BOARD_maple) || defined(BOARD_maple_RET6) || \ defined(BOARD_maple_mini) || defined(BOARD_maple_native)) -#warning USB CDC ACM relies on LeafLabs board-specific configuration.\ - You may have problems on non-LeafLabs boards. +//#warning USB CDC ACM relies on LeafLabs board-specific configuration.\ +// You may have problems on non-LeafLabs boards. #endif static void vcomDataTxCb(void); @@ -261,18 +261,28 @@ static ONE_DESCRIPTOR String_Descriptor[N_STRING_DESCRIPTORS] = { /* I/O state */ -#define CDC_SERIAL_BUFFER_SIZE 512 +#define CDC_SERIAL_RX_BUFFER_SIZE 256 // must be power of 2 +#define CDC_SERIAL_RX_BUFFER_SIZE_MASK (CDC_SERIAL_RX_BUFFER_SIZE-1) /* Received data */ -static volatile uint8 vcomBufferRx[CDC_SERIAL_BUFFER_SIZE]; -/* Read index into vcomBufferRx */ -static volatile uint32 rx_offset = 0; -/* Number of bytes left to transmit */ -static volatile uint32 n_unsent_bytes = 0; -/* Are we currently sending an IN packet? */ -static volatile uint8 transmitting = 0; -/* Number of unread bytes */ -static volatile uint32 n_unread_bytes = 0; +static volatile uint8 vcomBufferRx[CDC_SERIAL_RX_BUFFER_SIZE]; +/* Write index to vcomBufferRx */ +static volatile uint32 rx_head; +/* Read index from vcomBufferRx */ +static volatile uint32 rx_tail; + +#define CDC_SERIAL_TX_BUFFER_SIZE 256 // must be power of 2 +#define CDC_SERIAL_TX_BUFFER_SIZE_MASK (CDC_SERIAL_TX_BUFFER_SIZE-1) +// Tx data +static volatile uint8 vcomBufferTx[CDC_SERIAL_TX_BUFFER_SIZE]; +// Write index to vcomBufferTx +static volatile uint32 tx_head; +// Read index from vcomBufferTx +static volatile uint32 tx_tail; +// Are we currently sending an IN packet? +static volatile int8 transmitting; + + /* Other state (line coding, DTR/RTS) */ @@ -374,9 +384,13 @@ void usb_cdcacm_enable(gpio_dev *disc_dev, uint8 disc_bit) { /* Present ourselves to the host. Writing 0 to "disc" pin must * pull USB_DP pin up while leaving USB_DM pulled down by the * transceiver. See USB 2.0 spec, section 7.1.7.3. */ - gpio_set_mode(disc_dev, disc_bit, GPIO_OUTPUT_PP); - gpio_write_bit(disc_dev, disc_bit, 0); - + + if (disc_dev!=NULL) + { + gpio_set_mode(disc_dev, disc_bit, GPIO_OUTPUT_PP); + gpio_write_bit(disc_dev, disc_bit, 0); + } + /* Initialize the USB peripheral. */ usb_init_usblib(USBLIB, ep_int_in, ep_int_out); } @@ -385,7 +399,10 @@ void usb_cdcacm_disable(gpio_dev *disc_dev, uint8 disc_bit) { /* Turn off the interrupt and signal disconnect (see e.g. USB 2.0 * spec, section 7.1.7.3). */ nvic_irq_disable(NVIC_USB_LP_CAN_RX0); - gpio_write_bit(disc_dev, disc_bit, 1); + if (disc_dev!=NULL) + { + gpio_write_bit(disc_dev, disc_bit, 1); + } } void usb_cdcacm_putc(char ch) { @@ -393,30 +410,34 @@ void usb_cdcacm_putc(char ch) { ; } -/* This function is blocking. +/* This function is non-blocking. * - * It copies data from a usercode buffer into the USB peripheral TX + * It copies data from a user buffer into the USB peripheral TX * buffer, and returns the number of bytes copied. */ -uint32 usb_cdcacm_tx(const uint8* buf, uint32 len) { - /* Last transmission hasn't finished, so abort. */ - while ( usb_cdcacm_is_transmitting()>0 ) ; // wait for end of transmission +uint32 usb_cdcacm_tx(const uint8* buf, uint32 len) +{ + if (len==0) return 0; // no data to send - /* We can only put USB_CDCACM_TX_EPSIZE bytes in the buffer. */ - if (len > USB_CDCACM_TX_EPSIZE) { - len = USB_CDCACM_TX_EPSIZE; - } + uint32 head = tx_head; // load volatile variable + uint32 tx_unsent = (head - tx_tail) & CDC_SERIAL_TX_BUFFER_SIZE_MASK; - /* Queue bytes for sending. */ - if (len) { - usb_copy_to_pma(buf, len, USB_CDCACM_TX_ADDR); + // We can only put bytes in the buffer if there is place + if (len > (CDC_SERIAL_TX_BUFFER_SIZE-tx_unsent-1) ) { + len = (CDC_SERIAL_TX_BUFFER_SIZE-tx_unsent-1); } - // We still need to wait for the interrupt, even if we're sending - // zero bytes. (Sending zero-size packets is useful for flushing - // host-side buffers.) - usb_set_ep_tx_count(USB_CDCACM_TX_ENDP, len); - n_unsent_bytes = len; - transmitting = 1; - usb_set_ep_tx_stat(USB_CDCACM_TX_ENDP, USB_EP_STAT_TX_VALID); + if (len==0) return 0; // buffer full + + uint16 i; + // copy data from user buffer to USB Tx buffer + for (i=0; i0 ? transmitting : 0); } uint16 usb_cdcacm_get_pending(void) { - return n_unsent_bytes; + return (tx_head - tx_tail) & CDC_SERIAL_TX_BUFFER_SIZE_MASK; } -/* Nonblocking byte receive. +/* Non-blocking byte receive. * * Copies up to len bytes from our private data buffer (*NOT* the PMA) * into buf and deq's the FIFO. */ -uint32 usb_cdcacm_rx(uint8* buf, uint32 len) { +uint32 usb_cdcacm_rx(uint8* buf, uint32 len) +{ /* Copy bytes to buffer. */ uint32 n_copied = usb_cdcacm_peek(buf, len); /* Mark bytes as read. */ - n_unread_bytes -= n_copied; - rx_offset = (rx_offset + n_copied) % CDC_SERIAL_BUFFER_SIZE; + uint16 tail = rx_tail; // load volatile variable + tail = (tail + n_copied) & CDC_SERIAL_RX_BUFFER_SIZE_MASK; + rx_tail = tail; // store volatile variable - /* If all bytes have been read, re-enable the RX endpoint, which - * was set to NAK when the current batch of bytes was received. */ - if (n_unread_bytes == 0) { - usb_set_ep_rx_count(USB_CDCACM_RX_ENDP, USB_CDCACM_RX_EPSIZE); + uint32 rx_unread = (rx_head - tail) & CDC_SERIAL_RX_BUFFER_SIZE_MASK; + // If buffer was emptied to a pre-set value, re-enable the RX endpoint + if ( rx_unread <= 64 ) { // experimental value, gives the best performance usb_set_ep_rx_stat(USB_CDCACM_RX_ENDP, USB_EP_STAT_RX_VALID); - } - + } return n_copied; } -/* Nonblocking byte lookahead. +/* Non-blocking byte lookahead. * * Looks at unread bytes without marking them as read. */ -uint32 usb_cdcacm_peek(uint8* buf, uint32 len) { +uint32 usb_cdcacm_peek(uint8* buf, uint32 len) +{ int i; - uint32 head = rx_offset; + uint32 tail = rx_tail; + uint32 rx_unread = (rx_head-tail) & CDC_SERIAL_RX_BUFFER_SIZE_MASK; - if (len > n_unread_bytes) { - len = n_unread_bytes; + if (len > rx_unread) { + len = rx_unread; } for (i = 0; i < len; i++) { - buf[i] = vcomBufferRx[head]; - head = (head + 1) % CDC_SERIAL_BUFFER_SIZE; + buf[i] = vcomBufferRx[tail]; + tail = (tail + 1) & CDC_SERIAL_RX_BUFFER_SIZE_MASK; } return len; } -uint32 usb_cdcacm_peek_ex(uint8* buf, uint32 offset, uint32 len) { +uint32 usb_cdcacm_peek_ex(uint8* buf, uint32 offset, uint32 len) +{ int i; - uint32 head = (rx_offset + offset) % CDC_SERIAL_BUFFER_SIZE; + uint32 tail = (rx_tail + offset) & CDC_SERIAL_RX_BUFFER_SIZE_MASK ; + uint32 rx_unread = (rx_head-tail) & CDC_SERIAL_RX_BUFFER_SIZE_MASK; - if (len + offset > n_unread_bytes) { - len = n_unread_bytes - offset; + if (len + offset > rx_unread) { + len = rx_unread - offset; } for (i = 0; i < len; i++) { - buf[i] = vcomBufferRx[head]; - head = (head + 1) % CDC_SERIAL_BUFFER_SIZE; + buf[i] = vcomBufferRx[tail]; + tail = (tail + 1) & CDC_SERIAL_RX_BUFFER_SIZE_MASK; } return len; @@ -495,12 +520,12 @@ uint32 usb_cdcacm_peek_ex(uint8* buf, uint32 offset, uint32 len) { /* Roger Clark. Added. for Arduino 1.0 API support of Serial.peek() */ int usb_cdcacm_peek_char() { - if (n_unread_bytes == 0) + if (usb_cdcacm_data_available() == 0) { return -1; } - return vcomBufferRx[rx_offset]; + return vcomBufferRx[rx_tail]; } uint8 usb_cdcacm_get_dtr() { @@ -534,41 +559,75 @@ int usb_cdcacm_get_n_data_bits(void) { return line_coding.bDataBits; } - /* * Callbacks */ - -static void vcomDataTxCb(void) { - n_unsent_bytes = 0; - transmitting = 0; +static void vcomDataTxCb(void) +{ + uint32 tail = tx_tail; // load volatile variable + uint32 tx_unsent = (tx_head - tail) & CDC_SERIAL_TX_BUFFER_SIZE_MASK; + if (tx_unsent==0) { + if ( (--transmitting)==0) goto flush; // no more data to send + return; // it was already flushed, keep Tx endpoint disabled + } + transmitting = 1; + // We can only send up to USB_CDCACM_TX_EPSIZE bytes in the endpoint. + if (tx_unsent > USB_CDCACM_TX_EPSIZE) { + tx_unsent = USB_CDCACM_TX_EPSIZE; + } + // copy the bytes from USB Tx buffer to PMA buffer + uint32 *dst = usb_pma_ptr(USB_CDCACM_TX_ADDR); + uint16 tmp = 0; + uint16 val; + int i; + for (i = 0; i < tx_unsent; i++) { + val = vcomBufferTx[tail]; + tail = (tail + 1) & CDC_SERIAL_TX_BUFFER_SIZE_MASK; + if (i&1) { + *dst++ = tmp | (val<<8); + } else { + tmp = val; + } + } + if ( tx_unsent&1 ) { + *dst = tmp; + } + tx_tail = tail; // store volatile variable +flush: + // enable Tx endpoint + usb_set_ep_tx_count(USB_CDCACM_TX_ENDP, tx_unsent); + usb_set_ep_tx_stat(USB_CDCACM_TX_ENDP, USB_EP_STAT_TX_VALID); } -static void vcomDataRxCb(void) { - uint32 ep_rx_size; - uint32 tail = (rx_offset + n_unread_bytes) % CDC_SERIAL_BUFFER_SIZE; - uint8 ep_rx_data[USB_CDCACM_RX_EPSIZE]; + +static void vcomDataRxCb(void) +{ + uint32 head = rx_head; // load volatile variable + + uint32 ep_rx_size = usb_get_ep_rx_count(USB_CDCACM_RX_ENDP); + // This copy won't overwrite unread bytes as long as there is + // enough room in the USB Rx buffer for next packet + uint32 *src = usb_pma_ptr(USB_CDCACM_RX_ADDR); + uint16 tmp = 0; + uint8 val; uint32 i; - - usb_set_ep_rx_stat(USB_CDCACM_RX_ENDP, USB_EP_STAT_RX_NAK); - ep_rx_size = usb_get_ep_rx_count(USB_CDCACM_RX_ENDP); - /* This copy won't overwrite unread bytes, since we've set the RX - * endpoint to NAK, and will only set it to VALID when all bytes - * have been read. */ - usb_copy_from_pma((uint8*)ep_rx_data, ep_rx_size, - USB_CDCACM_RX_ADDR); - for (i = 0; i < ep_rx_size; i++) { - vcomBufferRx[tail] = ep_rx_data[i]; - tail = (tail + 1) % CDC_SERIAL_BUFFER_SIZE; + if (i&1) { + val = tmp>>8; + } else { + tmp = *src++; + val = tmp&0xFF; + } + vcomBufferRx[head] = val; + head = (head + 1) & CDC_SERIAL_RX_BUFFER_SIZE_MASK; } + rx_head = head; // store volatile variable - n_unread_bytes += ep_rx_size; - - if ( n_unread_bytes == 0 ) { - usb_set_ep_rx_count(USB_CDCACM_RX_ENDP, USB_CDCACM_RX_EPSIZE); - usb_set_ep_rx_stat(USB_CDCACM_RX_ENDP, USB_EP_STAT_RX_VALID); - } + uint32 rx_unread = (head - rx_tail) & CDC_SERIAL_RX_BUFFER_SIZE_MASK; + // only enable further Rx if there is enough room to receive one more packet + if ( rx_unread < (CDC_SERIAL_RX_BUFFER_SIZE-USB_CDCACM_RX_EPSIZE) ) { + usb_set_ep_rx_stat(USB_CDCACM_RX_ENDP, USB_EP_STAT_RX_VALID); + } if (rx_hook) { rx_hook(USB_CDCACM_HOOK_RX, 0); @@ -646,10 +705,11 @@ static void usbReset(void) { SetDeviceAddress(0); /* Reset the RX/TX state */ - n_unread_bytes = 0; - n_unsent_bytes = 0; - rx_offset = 0; - transmitting = 0; + rx_head = 0; + rx_tail = 0; + tx_head = 0; + tx_tail = 0; + transmitting = -1; } static RESULT usbDataSetup(uint8 request) { diff --git a/BootLoaders/Boards/stm32/cores/maple/libmaple/usb/stm32f1/usb_reg_map.c b/BootLoaders/Boards/stm32/cores/maple/libmaple/usb/stm32f1/usb_reg_map.c index ea60cb3..3f5446a 100644 --- a/BootLoaders/Boards/stm32/cores/maple/libmaple/usb/stm32f1/usb_reg_map.c +++ b/BootLoaders/Boards/stm32/cores/maple/libmaple/usb/stm32f1/usb_reg_map.c @@ -29,7 +29,7 @@ /* TODO these could use some improvement; they're fairly * straightforward ports of the analogous ST code. The PMA blit * routines in particular are obvious targets for performance - * measurement and tuning. */ + * measurement and tuning. void usb_copy_to_pma(const uint8 *buf, uint16 len, uint16 pma_offset) { uint16 *dst = (uint16*)usb_pma_ptr(pma_offset); @@ -57,7 +57,7 @@ void usb_copy_from_pma(uint8 *buf, uint16 len, uint16 pma_offset) { *dst = *src & 0xFF; } } - + */ static void usb_set_ep_rx_count_common(uint32 *rxc, uint16 count) { uint16 nblocks; if (count > 62) { @@ -76,12 +76,12 @@ static void usb_set_ep_rx_count_common(uint32 *rxc, uint16 count) { *rxc = nblocks << 10; } } - +/* void usb_set_ep_rx_buf0_count(uint8 ep, uint16 count) { uint32 *rxc = usb_ep_rx_buf0_count_ptr(ep); usb_set_ep_rx_count_common(rxc, count); } - +*/ void usb_set_ep_rx_count(uint8 ep, uint16 count) { uint32 *rxc = usb_ep_rx_count_ptr(ep); usb_set_ep_rx_count_common(rxc, count); diff --git a/BootLoaders/Boards/stm32/cores/maple/libmaple/util.c b/BootLoaders/Boards/stm32/cores/maple/libmaple/util.c index 4c0b2c8..f488ea4 100644 --- a/BootLoaders/Boards/stm32/cores/maple/libmaple/util.c +++ b/BootLoaders/Boards/stm32/cores/maple/libmaple/util.c @@ -88,7 +88,7 @@ void _fail(const char* file, int line, const char* exp) { * Provide an __assert_func handler to libc so that calls to assert() * get redirected to _fail. */ -void __assert_func(const char* file, int line, const char* method, +void __assert_func(const char* file, int line, const char* method __attribute__((unused)), const char* expression) { _fail(file, line, expression); } diff --git a/BootLoaders/Boards/stm32/cores/maple/new.cpp b/BootLoaders/Boards/stm32/cores/maple/new.cpp new file mode 100644 index 0000000..f189775 --- /dev/null +++ b/BootLoaders/Boards/stm32/cores/maple/new.cpp @@ -0,0 +1,36 @@ +/* + Copyright (c) 2014 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include + +void *operator new(size_t size) { + return malloc(size); +} + +void *operator new[](size_t size) { + return malloc(size); +} + +void operator delete(void * ptr) { + free(ptr); +} + +void operator delete[](void * ptr) { + free(ptr); +} + diff --git a/BootLoaders/Boards/stm32/cores/maple/sdio.cpp b/BootLoaders/Boards/stm32/cores/maple/sdio.cpp new file mode 100644 index 0000000..8bd9491 --- /dev/null +++ b/BootLoaders/Boards/stm32/cores/maple/sdio.cpp @@ -0,0 +1,198 @@ +/****************************************************************************** + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/sdio.c + * @author stevstrong + * @brief Secure digital input/output interface. + */ + +#include +#include +#include +#include "wirish.h" + + +//#include +//#include +//#include +//#include "wirish.h" +//#include "boards.h" +// + +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) + +sdio_dev * SDIO = SDIO_BASE; + +#define DELAY_LONG 10 +#define DELAY_SHORT 1 + +uint8_t dly = DELAY_LONG; // microseconds delay after accessing registers + +/* + * SDIO convenience routines + */ +void sdio_gpios_init(void) +{ + gpio_set_mode(PIN_MAP[BOARD_SDIO_D0].gpio_device, PIN_MAP[BOARD_SDIO_D0].gpio_bit, GPIO_AF_OUTPUT_PP); + gpio_set_mode(PIN_MAP[BOARD_SDIO_D1].gpio_device, PIN_MAP[BOARD_SDIO_D1].gpio_bit, GPIO_AF_OUTPUT_PP); + gpio_set_mode(PIN_MAP[BOARD_SDIO_D2].gpio_device, PIN_MAP[BOARD_SDIO_D2].gpio_bit, GPIO_AF_OUTPUT_PP); + gpio_set_mode(PIN_MAP[BOARD_SDIO_D3].gpio_device, PIN_MAP[BOARD_SDIO_D3].gpio_bit, GPIO_AF_OUTPUT_PP); + gpio_set_mode(PIN_MAP[BOARD_SDIO_CLK].gpio_device, PIN_MAP[BOARD_SDIO_CLK].gpio_bit, GPIO_AF_OUTPUT_PP); + gpio_set_mode(PIN_MAP[BOARD_SDIO_CMD].gpio_device, PIN_MAP[BOARD_SDIO_CMD].gpio_bit, GPIO_AF_OUTPUT_PP); + /* + * Todo just remove it, not needed for F1. + */ + /* + gpio_set_af_mode(BOARD_SDIO_D0, 12); + gpio_set_af_mode(BOARD_SDIO_D1, 12); + gpio_set_af_mode(BOARD_SDIO_D2, 12); + gpio_set_af_mode(BOARD_SDIO_D3, 12); + gpio_set_af_mode(BOARD_SDIO_CLK, 12); + gpio_set_af_mode(BOARD_SDIO_CMD, 12); + */ +} + +void sdio_gpios_deinit(void) +{ + gpio_set_mode(PIN_MAP[BOARD_SDIO_D0].gpio_device, PIN_MAP[BOARD_SDIO_D0].gpio_bit, GPIO_INPUT_FLOATING); + gpio_set_mode(PIN_MAP[BOARD_SDIO_D1].gpio_device, PIN_MAP[BOARD_SDIO_D1].gpio_bit, GPIO_INPUT_FLOATING); + gpio_set_mode(PIN_MAP[BOARD_SDIO_D2].gpio_device, PIN_MAP[BOARD_SDIO_D2].gpio_bit, GPIO_INPUT_FLOATING); + gpio_set_mode(PIN_MAP[BOARD_SDIO_D3].gpio_device, PIN_MAP[BOARD_SDIO_D3].gpio_bit, GPIO_INPUT_FLOATING); + gpio_set_mode(PIN_MAP[BOARD_SDIO_CLK].gpio_device, PIN_MAP[BOARD_SDIO_CLK].gpio_bit, GPIO_INPUT_FLOATING); + gpio_set_mode(PIN_MAP[BOARD_SDIO_CMD].gpio_device, PIN_MAP[BOARD_SDIO_CMD].gpio_bit, GPIO_INPUT_FLOATING); + + /* + * Todo just remove it, not needed for F1. + */ + /* + gpio_set_af_mode(BOARD_SDIO_D0, 0); + gpio_set_af_mode(BOARD_SDIO_D1, 0); + gpio_set_af_mode(BOARD_SDIO_D2, 0); + gpio_set_af_mode(BOARD_SDIO_D3, 0); + gpio_set_af_mode(BOARD_SDIO_CLK, 0); + gpio_set_af_mode(BOARD_SDIO_CMD, 0); + */ +} + +/** + * @brief Initialize and reset the SDIO device. + */ +void sdio_init(void) +{ + rcc_clk_enable(RCC_SDIO); + rcc_reset_dev(RCC_SDIO); +} + +void sdio_power_on(void) +{ + SDIO->POWER = SDIO_POWER_PWRCTRL_ON; +// After a data write, data cannot be written to this register for three SDIOCLK clock periods +// plus two PCLK2 clock periods. + delay_us(DELAY_LONG); +} + +void sdio_power_off(void) +{ + SDIO->POWER = SDIO_POWER_PWRCTRL_OFF; +// After a data write, data cannot be written to this register for three SDIOCLK clock periods +// plus two PCLK2 clock periods. + delay_us(DELAY_LONG); +} + +void sdio_set_clock(uint32_t clk) +{ + if (clk>24000000UL) clk = 24000000UL; // limit the SDIO master clock to 24MHz + + if (clk<1000000) dly = DELAY_LONG; + else dly = DELAY_SHORT; + + sdio_disable(); + SDIO->CLKCR = (SDIO->CLKCR & (~(SDIO_CLKCR_CLKDIV|SDIO_CLKCR_BYPASS))) | SDIO_CLKCR_CLKEN | (((SDIOCLK/clk)-2)&SDIO_CLKCR_CLKDIV); + delay_us(dly); +} + +void sdio_set_dbus_width(uint16_t bus_w) +{ + SDIO->CLKCR = (SDIO->CLKCR & (~SDIO_CLKCR_WIDBUS)) | bus_w; + delay_us(dly); +} + +void sdio_set_dblock_size(uint8_t dbsize) +{ + SDIO->DCTRL = (SDIO->DCTRL&(~SDIO_DCTRL_DBLOCKSIZE)) | ((dbsize&0xF)<<4); + delay_us(dly); +} + +void sdio_enable(void) +{ + SDIO->CLKCR |= SDIO_CLKCR_CLKEN; + delay_us(dly); +} + +void sdio_disable(void) +{ + SDIO->CLKCR ^= SDIO_CLKCR_CLKEN; + delay_us(dly); +} + +/** + * @brief Configure and enable the SDIO device. + */ +void sdio_begin(void) +{ + sdio_gpios_init(); + sdio_init(); + sdio_power_on(); + // Set initial SCK rate. + sdio_set_clock(400000); + delay_us(200); // generate 80 pulses at 400kHz +} + +/** + * @brief Disables the SDIO device. + */ +void sdio_end(void) +{ + sdio_disable(); + while ( sdio_cmd_xfer_ongoing() ); + sdio_power_off(); + rcc_clk_disable(RCC_SDIO); + sdio_gpios_deinit(); +} + +/** + * @brief Send command by the SDIO device. + */ +uint8_t sdio_cmd_send(uint16_t cmd_index_resp_type, uint32_t arg) +{ + uint8_t retries = 10; // in case of errors + do { // retry command if errors detected + // clear interrupt flags - IMPORTANT!!! + SDIO->ICR = SDIO_ICR_CMD_FLAGS; + // write command + SDIO->ARG = arg; + SDIO->CMD = (uint32_t)(SDIO_CMD_CPSMEN | cmd_index_resp_type ); + while ( (SDIO->STA&SDIO_STA_CMDACT) ) ; // wait for actual command transfer to finish + // wait for response, if the case + if ( cmd_index_resp_type&(SDIO_CMD_WAIT_SHORT_RESP|SDIO_CMD_WAIT_LONG_RESP) ) { + while ( !(SDIO->STA&(SDIO_STA_CMDREND|SDIO_STA_CMD_ERROR_FLAGS)) ) ; + } else break; // no response required + if ( SDIO->STA&(SDIO_STA_CMDREND|SDIO_STA_CTIMEOUT) ) + break; // response received or timeout + // ignore CRC error for CMD5 and ACMD41 + if ( ((cmd_index_resp_type&SDIO_CMD_CMDINDEX)==5) || ((cmd_index_resp_type&SDIO_CMD_CMDINDEX)==41) ) + break; + } while ( (--retries) ); + return (uint8_t)retries; +} + +#endif // defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) diff --git a/BootLoaders/Boards/stm32/cores/maple/stm32f1/wiring_pulse_f1.cpp b/BootLoaders/Boards/stm32/cores/maple/stm32f1/wiring_pulse_f1.cpp index 3abac9d..e0d560b 100644 --- a/BootLoaders/Boards/stm32/cores/maple/stm32f1/wiring_pulse_f1.cpp +++ b/BootLoaders/Boards/stm32/cores/maple/stm32f1/wiring_pulse_f1.cpp @@ -1,5 +1,6 @@ #include #include "boards.h" +#include "variant.h" /* Measures the length (in microseconds) of a pulse on the pin; state is HIGH * or LOW, the type of pulse to measure. Works on pulses from 2-3 microseconds * to 3 minutes in length, but must be called at least a few dozen microseconds @@ -28,13 +29,13 @@ */ uint32_t pulseIn( uint32_t pin, uint32_t state, uint32_t timeout ) { - // cache the port and bit of the pin in order to speed up the + // cache the IDR address and bit of the pin in order to speed up the // pulse width measuring loop and achieve finer resolution. calling // digitalRead() instead yields much coarser resolution. - gpio_dev *dev=PIN_MAP[pin].gpio_device; - uint32_t bit = (1U << PIN_MAP[pin].gpio_bit); - + __io uint32_t * const idr = portInputRegister(digitalPinToPort(pin)); + const uint32_t bit = digitalPinToBitMask(pin); + const uint32_t stateMask = (state ? bit:0); uint32_t width = 0; // keep initialization out of time critical area @@ -45,23 +46,23 @@ uint32_t pulseIn( uint32_t pin, uint32_t state, uint32_t timeout ) volatile uint32_t dummyWidth=0; // wait for any previous pulse to end - while ( (dev->regs->IDR & bit) == bit) { + while ((*idr & bit) == stateMask) { if (numloops++ == maxloops) { return 0; } - dummyWidth++; + dummyWidth++; } // wait for the pulse to start - while ((dev->regs->IDR & bit) != bit) { + while ((*idr & bit) != stateMask) { if (numloops++ == maxloops) { return 0; } - dummyWidth++; + dummyWidth++; } // wait for the pulse to stop - while ((dev->regs->IDR & bit) == bit) { + while ((*idr & bit) == stateMask) { if (numloops++ == maxloops) { return 0; } diff --git a/BootLoaders/Boards/stm32/cores/maple/stm32f1/wirish_digital_f1.cpp b/BootLoaders/Boards/stm32/cores/maple/stm32f1/wirish_digital_f1.cpp index f16181d..3ea5ed0 100644 --- a/BootLoaders/Boards/stm32/cores/maple/stm32f1/wirish_digital_f1.cpp +++ b/BootLoaders/Boards/stm32/cores/maple/stm32f1/wirish_digital_f1.cpp @@ -80,10 +80,13 @@ void pinMode(uint8 pin, WiringPinMode mode) { gpio_set_mode(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit, outputMode); if (PIN_MAP[pin].timer_device != NULL) { - /* Enable/disable timer channels if we're switching into or - * out of PWM. */ + if ( pwm ) { // we're switching into PWM, enable timer channels timer_set_mode(PIN_MAP[pin].timer_device, PIN_MAP[pin].timer_channel, - pwm ? TIMER_PWM : TIMER_DISABLED); + TIMER_PWM ); + } else { // disable channel output in non pwm-Mode + timer_cc_disable(PIN_MAP[pin].timer_device, + PIN_MAP[pin].timer_channel); + } } } diff --git a/BootLoaders/Boards/stm32/cores/maple/tone.cpp b/BootLoaders/Boards/stm32/cores/maple/tone.cpp new file mode 100644 index 0000000..b249a78 --- /dev/null +++ b/BootLoaders/Boards/stm32/cores/maple/tone.cpp @@ -0,0 +1,205 @@ +/////////////////////////////////////////////////////////////////////// +// +// tone(pin,frequency[,duration]) generate a tone on a given pin +// +// noTone(pin) switch off the tone on the pin +// +// setToneTimerChannel(timer,channel) force use of given timer/channel +// +/////////////////////////////////////////////////////////////////////// + +#include "Arduino.h" +#include + + +#define PinTimer(pin) (PIN_MAP[pin].timer_device->clk_id-RCC_TIMER1+1) +#define PinChannel(pin) (PIN_MAP[pin].timer_channel) + +// if USE_PIN_TIMER is set, the PWM timer/channel is used for PWM pins +#define USE_PIN_TIMER + +// if USE_BSRR is set the tone pin will be written via the fast BSRR register +// instead of using the slow digitalWrite() function in the interrupt handler +#define USE_BSRR + +// construct static timer array ( + + +#ifdef STM32_HIGH_DENSITY +// define default timer and channel + #ifndef TONE_TIMER + #define TONE_TIMER 8 + #endif + #ifndef TONE_CHANNEL + #define TONE_CHANNEL 8 + #endif + + HardwareTimer TTimer1(1), TTimer2(2), TTimer3(3), TTimer4(4),TTimer5(5), TTimer6(6), TTimer7(7), TTimer8(8); + HardwareTimer *TTimer[8] = { &TTimer1,&TTimer2,&TTimer3,&TTimer4,&TTimer5,&TTimer6,&TTimer7,&TTimer8 }; +#else + // define default timer and channel + #ifndef TONE_TIMER + #define TONE_TIMER 4 + #endif + #ifndef TONE_CHANNEL + #define TONE_CHANNEL 4 + #endif + + HardwareTimer TTimer1(1), TTimer2(2), TTimer3(3), TTimer4(4); + HardwareTimer *TTimer[4] = { &TTimer1,&TTimer2,&TTimer3,&TTimer4 }; +#endif + + +uint8_t tone_force_channel = 0; // forced timer channel +uint8_t tone_force_ntimer = 0; // forced timer + +HardwareTimer *tone_timer;// = TTimer[TONE_TIMER-1]; // timer used to generate frequency +uint8_t tone_channel = TONE_CHANNEL; // timer channel used to generate frequency +uint8_t tone_ntimer = TONE_TIMER; // timer used to generate frequency + +bool tone_state = true; // last pin state for toggling +short tone_pin = -1; // pin for outputting sound +short tone_freq = 444; // tone frequency (0=pause) +volatile uint32_t tone_nhw = 0; // tone duration in number of half waves +uint16_t tone_tcount = 0; // time between handler calls in 1/36 usec +uint16_t tone_ncount = 0; // handler call between toggling +uint16_t tone_n = 0; // remaining handler calls before toggling +uint32_t tone_next = 0; // counter value of next interrupt + +#ifdef USE_BSRR +volatile uint32_t *tone_bsrr; // BSRR set register (lower 16 bits) +uint32_t tone_smask=0; // BSRR set bitmask +uint32_t tone_rmask=0; // BSRR reset bitmask +#endif + + +//////////////////////////////////////////////////////////////////////////////// +// timer hander for tone with no duration specified, +// will keep going until noTone() is called +void tone_handler_1(void) { + tone_next += tone_tcount; // comparator value for next interrupt + tone_timer->setCompare(tone_channel, tone_next); // and install it + if(--tone_n == 0){ + tone_state = !tone_state; // toggle tone output + +#ifdef USE_BSRR + if(tone_state) + *tone_bsrr = tone_smask; + else + *tone_bsrr = tone_rmask; +#else + digitalWrite(tone_pin,tone_state);// and output it +#endif + + tone_n = tone_ncount; // reset interrupt counter + } +} + +//////////////////////////////////////////////////////////////////////////////// +// timer hander for tone with a specified duration, +// will stop automatically when duration time is up. +void tone_handler_2(void) { + tone_next += tone_tcount; + tone_timer->setCompare(tone_channel, tone_next); + if(--tone_n == 0){ + if(tone_freq>0){ // toggle pin + tone_state = !tone_state; +#ifdef USE_BSRR + if(tone_state) + *tone_bsrr = tone_smask; + else + *tone_bsrr = tone_rmask; +#else + digitalWrite(tone_pin,tone_state);// and output it +#endif + } + tone_n = tone_ncount; + if(!--tone_nhw){ // check if tone duration has finished + tone_timer->pause(); // disable timer + pinMode(tone_pin, INPUT); // disable tone pin + } + } +} + +//////////////////////////////////////////////////////////////////////////////// +// play a tone on given pin with given frequency and optional duration in msec +void tone(uint32_t pin, uint32_t freq, uint32_t duration) { + tone_pin = pin; + +#ifdef USE_PIN_TIMER + // if the pin has a PWM timer/channel, use it (unless the timer/channel are forced) + if(PinChannel(tone_pin) && !tone_force_channel){ + tone_channel = PinChannel(tone_pin); + tone_ntimer = PinTimer(tone_pin); + } else +#endif + { + // set timer and channel to default resp values forced with setToneTimerChannel + tone_ntimer = tone_force_channel?tone_force_ntimer:TONE_TIMER; + tone_channel = tone_force_channel?tone_force_channel:TONE_CHANNEL; + } + + tone_timer = TTimer[tone_ntimer-1]; + tone_freq = freq; + tone_nhw = 0; + tone_next = 0; + + tone_timer->pause(); + + if(freq > 0){ + uint32_t count = (F_CPU/4)/freq; // timer counts per half wave + tone_ncount = tone_n = (count>>16)+1; // number of 16-bit count chunk + tone_tcount = count/tone_ncount; // size of count chunk + if(duration > 0) // number of half waves to be generated + tone_nhw = ((duration*freq)/1000)<<1; + else // no duration specified, continuous sound until noTone() called + tone_nhw = 0; + + pinMode(tone_pin, PWM); // configure output pin + pinMode(tone_pin, OUTPUT); // configure output pin + +#ifdef USE_BSRR + // Set up BSRR register values for fast ISR + tone_bsrr = &((PIN_MAP[tone_pin].gpio_device)->regs->BSRR); + tone_smask = (BIT(PIN_MAP[tone_pin].gpio_bit)); + tone_rmask = tone_smask<<16; +#endif + + // Set up an interrupt on given timer and channel + tone_next = tone_tcount; // prepare channel compare register + tone_timer->setMode(tone_channel,TIMER_OUTPUT_COMPARE); + tone_timer->setCompare(tone_channel,tone_next); + // attach corresponding handler routine + tone_timer->attachInterrupt(tone_channel,tone_nhw?tone_handler_2:tone_handler_1); + + // Refresh the tone timer + tone_timer->refresh(); + + // Start the timer counting + tone_timer->resume(); + + } else { + + // detach handler routine + tone_timer->detachInterrupt(tone_channel); + // disactive pin by configuring it as input + pinMode(tone_pin, INPUT); + + } + + //while(tone_nhw) ; // blocks till duration elapsed +} + +//////////////////////////////////////////////////////////////////////////////// +// disable tone on specified pin, if any +void noTone(uint32_t pin){ + tone(pin,0,0); // it's all handled in tone() +} + +//////////////////////////////////////////////////////////////////////////////// +// set timer and channel to some different value +// must be called before calling tone() or after noTone() was called +void setToneTimerChannel(uint8_t ntimer, uint8_t channel){ + tone_force_ntimer = ntimer; + tone_force_channel = channel; +} diff --git a/BootLoaders/Boards/stm32/cores/maple/tone.h b/BootLoaders/Boards/stm32/cores/maple/tone.h new file mode 100644 index 0000000..cf27051 --- /dev/null +++ b/BootLoaders/Boards/stm32/cores/maple/tone.h @@ -0,0 +1,28 @@ +/* + Copyright (c) 2015 Arduino LLC. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#pragma once + +#ifdef __cplusplus + +#include "Arduino.h" + +void tone(uint32_t _pin, uint32_t frequency, uint32_t duration = 0); +void noTone(uint32_t _pin); + +#endif diff --git a/BootLoaders/Boards/stm32/cores/maple/usb_serial.cpp b/BootLoaders/Boards/stm32/cores/maple/usb_serial.cpp index ab8816b..e6d5cb0 100644 --- a/BootLoaders/Boards/stm32/cores/maple/usb_serial.cpp +++ b/BootLoaders/Boards/stm32/cores/maple/usb_serial.cpp @@ -54,6 +54,9 @@ static void ifaceSetupHook(unsigned, void*); */ #define USB_TIMEOUT 50 +#if BOARD_HAVE_SERIALUSB +bool USBSerial::_hasBegun = false; +#endif USBSerial::USBSerial(void) { #if !BOARD_HAVE_SERIALUSB @@ -62,8 +65,13 @@ USBSerial::USBSerial(void) { } void USBSerial::begin(void) { + #if BOARD_HAVE_SERIALUSB - usb_cdcacm_enable(BOARD_USB_DISC_DEV, BOARD_USB_DISC_BIT); + if (_hasBegun) + return; + _hasBegun = true; + + usb_cdcacm_enable(BOARD_USB_DISC_DEV, (uint8_t)BOARD_USB_DISC_BIT); usb_cdcacm_set_hooks(USB_CDCACM_HOOK_RX, rxHook); usb_cdcacm_set_hooks(USB_CDCACM_HOOK_IFACE_SETUP, ifaceSetupHook); #endif @@ -75,6 +83,7 @@ void USBSerial::begin(unsigned long ignoreBaud) volatile unsigned long removeCompilerWarningsIgnoreBaud=ignoreBaud; ignoreBaud=removeCompilerWarningsIgnoreBaud; + begin(); } void USBSerial::begin(unsigned long ignoreBaud, uint8_t ignore) { @@ -83,13 +92,16 @@ volatile uint8_t removeCompilerWarningsIgnore=ignore; ignoreBaud=removeCompilerWarningsIgnoreBaud; ignore=removeCompilerWarningsIgnore; + begin(); } void USBSerial::end(void) { #if BOARD_HAVE_SERIALUSB - usb_cdcacm_disable(BOARD_USB_DISC_DEV, BOARD_USB_DISC_BIT); + usb_cdcacm_disable(BOARD_USB_DISC_DEV, (uint8_t)BOARD_USB_DISC_BIT); usb_cdcacm_remove_hooks(USB_CDCACM_HOOK_RX | USB_CDCACM_HOOK_IFACE_SETUP); + _hasBegun = false; #endif + } size_t USBSerial::write(uint8 ch) { @@ -100,44 +112,23 @@ size_t n = 0; size_t USBSerial::write(const char *str) { size_t n = 0; - this->write(str, strlen(str)); + this->write((const uint8*)str, strlen(str)); return n; } -size_t USBSerial::write(const void *buf, uint32 len) { +size_t USBSerial::write(const uint8 *buf, uint32 len) +{ size_t n = 0; - if (!this->isConnected() || !buf) { + if (!(bool) *this || !buf) { return 0; } uint32 txed = 0; - uint32 old_txed = 0; - uint32 start = millis(); - - uint32 sent = 0; - - while (txed < len && (millis() - start < USB_TIMEOUT)) { - sent = usb_cdcacm_tx((const uint8*)buf + txed, len - txed); - txed += sent; - if (old_txed != txed) { - start = millis(); - } - old_txed = txed; + while (txed < len) { + txed += usb_cdcacm_tx((const uint8*)buf + txed, len - txed); } - -#if 0 -// this code leads to a serious performance drop and appears to be -// unnecessary - everything seems to work fine without, -jcw, 2015-11-05 -// see http://stm32duino.com/posting.php?mode=quote&f=3&p=7746 - if (sent == USB_CDCACM_TX_EPSIZE) { - while (usb_cdcacm_is_transmitting() != 0) { - } - /* flush out to avoid having the pc wait for more data */ - usb_cdcacm_tx(NULL, 0); - } -#endif - return n; + return n; } int USBSerial::available(void) { @@ -168,19 +159,28 @@ void USBSerial::flush(void) return; } -uint32 USBSerial::read(void *buf, uint32 len) { - if (!buf) { - return 0; - } - +uint32 USBSerial::read(uint8 * buf, uint32 len) { uint32 rxed = 0; while (rxed < len) { - rxed += usb_cdcacm_rx((uint8*)buf + rxed, len - rxed); + rxed += usb_cdcacm_rx(buf + rxed, len - rxed); } return rxed; } +size_t USBSerial::readBytes(char *buf, const size_t& len) +{ + size_t rxed=0; + unsigned long startMillis; + startMillis = millis(); + if (len <= 0) return 0; + do { + rxed += usb_cdcacm_rx((uint8 *)buf + rxed, len - rxed); + if (rxed == len) return rxed; + } while(millis() - startMillis < _timeout); + return rxed; +} + /* Blocks forever until 1 byte is received */ int USBSerial::read(void) { uint8 b; @@ -203,10 +203,6 @@ uint8 USBSerial::pending(void) { return usb_cdcacm_get_pending(); } -uint8 USBSerial::isConnected(void) { - return usb_is_connected(USBLIB) && usb_is_configured(USBLIB) && usb_cdcacm_get_dtr(); -} - uint8 USBSerial::getDTR(void) { return usb_cdcacm_get_dtr(); } @@ -215,6 +211,10 @@ uint8 USBSerial::getRTS(void) { return usb_cdcacm_get_rts(); } +USBSerial::operator bool() { + return usb_is_connected(USBLIB) && usb_is_configured(USBLIB) && usb_cdcacm_get_dtr(); +} + #if BOARD_HAVE_SERIALUSB #ifdef SERIAL_USB USBSerial Serial; @@ -236,7 +236,7 @@ enum reset_state_t { static reset_state_t reset_state = DTR_UNSET; -static void ifaceSetupHook(unsigned hook, void *requestvp) { +static void ifaceSetupHook(unsigned hook __attribute__((unused)), void *requestvp) { uint8 request = *(uint8*)requestvp; // Ignore requests we're not interested in. @@ -290,7 +290,7 @@ static void wait_reset(void) { #define STACK_TOP 0x20000800 #define EXC_RETURN 0xFFFFFFF9 #define DEFAULT_CPSR 0x61000000 -static void rxHook(unsigned hook, void *ignored) { +static void rxHook(unsigned hook __attribute__((unused)), void *ignored __attribute__((unused))) { /* FIXME this is mad buggy; we need a new reset sequence. E.g. NAK * after each RX means you can't reset if any bytes are waiting. */ if (reset_state == DTR_NEGEDGE) { diff --git a/BootLoaders/Boards/stm32/cores/maple/usb_serial.h b/BootLoaders/Boards/stm32/cores/maple/usb_serial.h index 740ab0f..8351593 100644 --- a/BootLoaders/Boards/stm32/cores/maple/usb_serial.h +++ b/BootLoaders/Boards/stm32/cores/maple/usb_serial.h @@ -44,38 +44,51 @@ public: void begin(void); - // Roger Clark. Added dummy function so that existing Arduino sketches which specify baud rate will compile. - void begin(unsigned long); - void begin(unsigned long, uint8_t); + // Roger Clark. Added dummy function so that existing Arduino sketches which specify baud rate will compile. + void begin(unsigned long); + void begin(unsigned long, uint8_t); void end(void); - operator bool() { return true; } // Roger Clark. This is needed because in cardinfo.ino it does if (!Serial) . It seems to be a work around for the Leonardo that we needed to implement just to be compliant with the API - virtual int available(void);// Changed to virtual - uint32 read(void *buf, uint32 len); - // uint8 read(void); + size_t readBytes(char *buf, const size_t& len); + uint32 read(uint8 * buf, uint32 len); + // uint8 read(void); - // Roger Clark. added functions to support Arduino 1.0 API + // Roger Clark. added functions to support Arduino 1.0 API virtual int peek(void); virtual int read(void); int availableForWrite(void); virtual void flush(void); - - + + size_t write(uint8); size_t write(const char *str); - size_t write(const void*, uint32); + size_t write(const uint8*, uint32); uint8 getRTS(); uint8 getDTR(); - uint8 isConnected(); uint8 pending(); + + /* SukkoPera: This is the Arduino way to check if an USB CDC serial + * connection is open. + + * Used for instance in cardinfo.ino. + */ + operator bool(); + + /* Old libmaple way to check for serial connection. + * + * Deprecated, use the above. + */ + uint8 isConnected() __attribute__((deprecated("Use !Serial instead"))) { return (bool) *this; } + +protected: + static bool _hasBegun; }; -#ifdef SERIAL_USB - extern USBSerial Serial; +#ifdef SERIAL_USB + extern USBSerial Serial; #endif #endif - diff --git a/BootLoaders/Boards/stm32/cores/maple/wirish.h b/BootLoaders/Boards/stm32/cores/maple/wirish.h index c2ab4f3..eb07c77 100644 --- a/BootLoaders/Boards/stm32/cores/maple/wirish.h +++ b/BootLoaders/Boards/stm32/cores/maple/wirish.h @@ -76,6 +76,7 @@ #include #include +#include typedef unsigned int word; // typedef uint16 word;// definition from Arduino website, now appears to be incorrect for 32 bit devices @@ -103,5 +104,7 @@ typedef unsigned int word; #define clockCyclesToMicroseconds(a) ( ((a) * 1000L) / (F_CPU / 1000L) ) #define microsecondsToClockCycles(a) ( (a) * (F_CPU / 1000000L) ) +#define digitalPinToInterrupt(pin) (pin) + #endif diff --git a/BootLoaders/Boards/stm32/cores/maple/wirish_math.cpp b/BootLoaders/Boards/stm32/cores/maple/wirish_math.cpp index 3b682d3..f8ada9f 100644 --- a/BootLoaders/Boards/stm32/cores/maple/wirish_math.cpp +++ b/BootLoaders/Boards/stm32/cores/maple/wirish_math.cpp @@ -47,3 +47,12 @@ long random(long howsmall, long howbig) { return random(diff) + howsmall; } +extern uint16_t makeWord( uint16_t w ) +{ + return w ; +} + +extern uint16_t makeWord( uint8_t h, uint8_t l ) +{ + return (h << 8) | l ; +} diff --git a/BootLoaders/Boards/stm32/cores/maple/wirish_math.h b/BootLoaders/Boards/stm32/cores/maple/wirish_math.h index d103d86..b85253f 100644 --- a/BootLoaders/Boards/stm32/cores/maple/wirish_math.h +++ b/BootLoaders/Boards/stm32/cores/maple/wirish_math.h @@ -33,6 +33,7 @@ #define _WIRISH_WIRISH_MATH_H_ #include +#include /** * @brief Initialize the pseudo-random number generator. @@ -78,11 +79,12 @@ long random(long min, long max); * @param toEnd the end of the value's mapped range. * @return the mapped value. */ -static inline long map(long value, long fromStart, long fromEnd, - long toStart, long toEnd) { - return (value - fromStart) * (toEnd - toStart) / (fromEnd - fromStart) + - toStart; -} + // Fix by Pito 9/2017 + static inline int32_t map(int32_t value, int32_t fromStart, int32_t fromEnd, + int32_t toStart, int32_t toEnd) { + return ((int64_t)(value - fromStart) * (toEnd - toStart)) / (fromEnd - fromStart) + + toStart; + } #define PI 3.1415926535897932384626433832795 #define HALF_PI 1.5707963267948966192313216916398 @@ -161,4 +163,9 @@ double sqrt(double x); */ double pow(double x, double y); +extern uint16_t makeWord( uint16_t w ) ; +extern uint16_t makeWord( uint8_t h, uint8_t l ) ; + +#define word(...) makeWord(__VA_ARGS__) + #endif diff --git a/BootLoaders/Boards/stm32/cores/maple/wirish_shift.cpp b/BootLoaders/Boards/stm32/cores/maple/wirish_shift.cpp index 2fb1f80..a263a07 100644 --- a/BootLoaders/Boards/stm32/cores/maple/wirish_shift.cpp +++ b/BootLoaders/Boards/stm32/cores/maple/wirish_shift.cpp @@ -35,3 +35,28 @@ void shiftOut(uint8 dataPin, uint8 clockPin, uint8 bitOrder, uint8 value) { gpio_toggle_bit(PIN_MAP[clockPin].gpio_device, PIN_MAP[clockPin].gpio_bit);// togglePin(clockPin); } } + +uint32_t shiftIn( uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder ) +{ + uint8_t value = 0 ; + uint8_t i ; + + + for ( i=0 ; i < 8 ; ++i ) + { + digitalWrite( ulClockPin, HIGH ) ; + + if ( ulBitOrder == LSBFIRST ) + { + value |= digitalRead( ulDataPin ) << i ; + } + else + { + value |= digitalRead( ulDataPin ) << (7 - i) ; + } + + digitalWrite( ulClockPin, LOW ) ; + } + + return value ; +} diff --git a/BootLoaders/Boards/stm32/cores/maple/wirish_time.cpp b/BootLoaders/Boards/stm32/cores/maple/wirish_time.cpp index 08fd2d1..6404bec 100644 --- a/BootLoaders/Boards/stm32/cores/maple/wirish_time.cpp +++ b/BootLoaders/Boards/stm32/cores/maple/wirish_time.cpp @@ -32,11 +32,15 @@ #include #include +#include "Arduino.h" void delay(unsigned long ms) { uint32 start = millis(); - while (millis() - start < ms) - ; + do + { + yield(); + } + while (millis() - start < ms); } void delayMicroseconds(uint32 us) { diff --git a/BootLoaders/Boards/stm32/cores/maple/wirish_types.h b/BootLoaders/Boards/stm32/cores/maple/wirish_types.h index 195cda8..14fb692 100644 --- a/BootLoaders/Boards/stm32/cores/maple/wirish_types.h +++ b/BootLoaders/Boards/stm32/cores/maple/wirish_types.h @@ -55,7 +55,6 @@ typedef struct stm32_pin_info { uint8 gpio_bit; /**< Pin's GPIO port bit. */ uint8 timer_channel; /**< Timer channel, or 0 if none. */ uint8 adc_channel; /**< Pin ADC channel, or ADCx if none. */ - uint8 pinMode; /**< mode specific by pinMode call (Roger Clark added to optimize compatibility with Arduino API*/ } stm32_pin_info; /** diff --git a/BootLoaders/Boards/stm32/libraries/EEPROM/EEPROM.cpp b/BootLoaders/Boards/stm32/libraries/EEPROM/EEPROM.cpp index 2cfd648..289a93a 100644 --- a/BootLoaders/Boards/stm32/libraries/EEPROM/EEPROM.cpp +++ b/BootLoaders/Boards/stm32/libraries/EEPROM/EEPROM.cpp @@ -521,6 +521,28 @@ uint16 EEPROMClass::write(uint16 Address, uint16 Data) return status; } +/** + * @brief Writes/upadtes variable data in EEPROM. + The value is written only if differs from the one already saved at the same address. + * @param VirtAddress: Variable virtual address + * @param Data: 16 bit data to be written + * @retval Success or error status: + * - EEPROM_SAME_VALUE: If new Data matches existing EEPROM Data + * - FLASH_COMPLETE: on success + * - EEPROM_BAD_ADDRESS: if address = 0xFFFF + * - EEPROM_PAGE_FULL: if valid page is full + * - EEPROM_NO_VALID_PAGE: if no valid page was found + * - EEPROM_OUT_SIZE: if no empty EEPROM variables + * - Flash error code: on write Flash error + */ +uint16 EEPROMClass::update(uint16 Address, uint16 Data) +{ + if (read(Address) == Data) + return EEPROM_SAME_VALUE; + else + return write(Address, Data); +} + /** * @brief Return number of variable * @retval Number of variables diff --git a/BootLoaders/Boards/stm32/libraries/EEPROM/EEPROM.h b/BootLoaders/Boards/stm32/libraries/EEPROM/EEPROM.h index 8a8320b..2957476 100644 --- a/BootLoaders/Boards/stm32/libraries/EEPROM/EEPROM.h +++ b/BootLoaders/Boards/stm32/libraries/EEPROM/EEPROM.h @@ -47,6 +47,7 @@ enum : uint16 EEPROM_BAD_ADDRESS = ((uint16)0x0082), EEPROM_BAD_FLASH = ((uint16)0x0083), EEPROM_NOT_INIT = ((uint16)0x0084), + EEPROM_SAME_VALUE = ((uint16)0x0085), EEPROM_NO_VALID_PAGE = ((uint16)0x00AB) }; @@ -67,6 +68,7 @@ public: uint16 read (uint16 address); uint16 read (uint16 address, uint16 *data); uint16 write(uint16 address, uint16 data); + uint16 update(uint16 address, uint16 data); uint16 count(uint16 *); uint16 maxcount(void); diff --git a/BootLoaders/Boards/stm32/libraries/SPI/src/SPI.cpp b/BootLoaders/Boards/stm32/libraries/SPI/src/SPI.cpp index 4eeec38..c07e2ea 100644 --- a/BootLoaders/Boards/stm32/libraries/SPI/src/SPI.cpp +++ b/BootLoaders/Boards/stm32/libraries/SPI/src/SPI.cpp @@ -31,7 +31,6 @@ #include "SPI.h" -//#define SPI_DEBUG #include #include @@ -41,6 +40,8 @@ #include "boards.h" //#include "HardwareSerial.h" +/** Time in ms for DMA receive timeout */ +#define DMA_TIMEOUT 100 #if CYCLES_PER_MICROSECOND != 72 /* TODO [0.2.0?] something smarter than this */ @@ -90,79 +91,80 @@ static const spi_pins board_spi_pins[] __FLASH__ = { * Constructor */ -SPIClass::SPIClass(uint32 spi_num) { +SPIClass::SPIClass(uint32 spi_num) +{ + _currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed - _currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed - - switch (spi_num) { #if BOARD_NR_SPI >= 1 case 1: _currentSetting->spi_d = SPI1; + _spi1_this = (void*) this; break; #endif #if BOARD_NR_SPI >= 2 case 2: _currentSetting->spi_d = SPI2; + _spi2_this = (void*) this; break; #endif #if BOARD_NR_SPI >= 3 case 3: _currentSetting->spi_d = SPI3; + _spi3_this = (void*) this; break; #endif default: ASSERT(0); } - - // Init things specific to each SPI device - // clock divider setup is a bit of hack, and needs to be improved at a later date. - _settings[0].spi_d = SPI1; - _settings[0].clockDivider = determine_baud_rate(_settings[0].spi_d, _settings[0].clock); - _settings[0].spiDmaDev = DMA1; - _settings[0].spiTxDmaChannel = DMA_CH3; - _settings[0].spiRxDmaChannel = DMA_CH2; - _settings[1].spi_d = SPI2; - _settings[1].clockDivider = determine_baud_rate(_settings[1].spi_d, _settings[1].clock); - _settings[1].spiDmaDev = DMA1; - _settings[1].spiTxDmaChannel = DMA_CH5; - _settings[1].spiRxDmaChannel = DMA_CH4; + + // Init things specific to each SPI device + // clock divider setup is a bit of hack, and needs to be improved at a later date. + _settings[0].spi_d = SPI1; + _settings[0].clockDivider = determine_baud_rate(_settings[0].spi_d, _settings[0].clock); + _settings[0].spiDmaDev = DMA1; + _settings[0].spiTxDmaChannel = DMA_CH3; + _settings[0].spiRxDmaChannel = DMA_CH2; + _settings[1].spi_d = SPI2; + _settings[1].clockDivider = determine_baud_rate(_settings[1].spi_d, _settings[1].clock); + _settings[1].spiDmaDev = DMA1; + _settings[1].spiTxDmaChannel = DMA_CH5; + _settings[1].spiRxDmaChannel = DMA_CH4; #if BOARD_NR_SPI >= 3 - _settings[2].spi_d = SPI3; - _settings[2].clockDivider = determine_baud_rate(_settings[2].spi_d, _settings[2].clock); - _settings[2].spiDmaDev = DMA2; - _settings[2].spiTxDmaChannel = DMA_CH2; - _settings[2].spiRxDmaChannel = DMA_CH1; -#endif - - //pinMode(BOARD_SPI_DEFAULT_SS,OUTPUT); + _settings[2].spi_d = SPI3; + _settings[2].clockDivider = determine_baud_rate(_settings[2].spi_d, _settings[2].clock); + _settings[2].spiDmaDev = DMA2; + _settings[2].spiTxDmaChannel = DMA_CH2; + _settings[2].spiRxDmaChannel = DMA_CH1; +#endif + + // added for DMA callbacks. + _currentSetting->state = SPI_STATE_IDLE; } /* * Set up/tear down */ void SPIClass::updateSettings(void) { - uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_SW_SLAVE | SPI_SOFT_SS); - #ifdef SPI_DEBUG - Serial.print("spi_master_enable("); Serial.print(_currentSetting->clockDivider); Serial.print(","); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")"); - #endif - spi_master_enable(_currentSetting->spi_d, (spi_baud_rate)_currentSetting->clockDivider, (spi_mode)_currentSetting->dataMode, flags); + uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_SW_SLAVE | SPI_SOFT_SS); + spi_master_enable(_currentSetting->spi_d, (spi_baud_rate)_currentSetting->clockDivider, (spi_mode)_currentSetting->dataMode, flags); } void SPIClass::begin(void) { spi_init(_currentSetting->spi_d); configure_gpios(_currentSetting->spi_d, 1); updateSettings(); + // added for DMA callbacks. + _currentSetting->state = SPI_STATE_READY; } void SPIClass::beginSlave(void) { spi_init(_currentSetting->spi_d); configure_gpios(_currentSetting->spi_d, 0); - uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_SW_SLAVE); - #ifdef SPI_DEBUG - Serial.print("spi_slave_enable("); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")"); - #endif + uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_RX_ONLY); spi_slave_enable(_currentSetting->spi_d, (spi_mode)_currentSetting->dataMode, flags); + // added for DMA callbacks. + _currentSetting->state = SPI_STATE_READY; } void SPIClass::end(void) { @@ -181,28 +183,25 @@ void SPIClass::end(void) { while (spi_is_busy(_currentSetting->spi_d)) ; spi_peripheral_disable(_currentSetting->spi_d); + // added for DMA callbacks. + // Need to add unsetting the callbacks for the DMA channels. + _currentSetting->state = SPI_STATE_IDLE; } /* Roger Clark added 3 functions */ void SPIClass::setClockDivider(uint32_t clockDivider) { - #ifdef SPI_DEBUG - Serial.print("Clock divider set to "); Serial.println(clockDivider); - #endif - _currentSetting->clockDivider = clockDivider; - uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_BR); - _currentSetting->spi_d->regs->CR1 = cr1 | (clockDivider & SPI_CR1_BR); + _currentSetting->clockDivider = clockDivider; + uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_BR); + _currentSetting->spi_d->regs->CR1 = cr1 | (clockDivider & SPI_CR1_BR); } void SPIClass::setBitOrder(BitOrder bitOrder) { - #ifdef SPI_DEBUG - Serial.print("Bit order set to "); Serial.println(bitOrder); - #endif - _currentSetting->bitOrder = bitOrder; - uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_LSBFIRST); - if ( bitOrder==LSBFIRST ) cr1 |= SPI_CR1_LSBFIRST; - _currentSetting->spi_d->regs->CR1 = cr1; + _currentSetting->bitOrder = bitOrder; + uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_LSBFIRST); + if ( bitOrder==LSBFIRST ) cr1 |= SPI_CR1_LSBFIRST; + _currentSetting->spi_d->regs->CR1 = cr1; } /* Victor Perez. Added to test changing datasize from 8 to 16 bit modes on the fly. @@ -211,9 +210,11 @@ void SPIClass::setBitOrder(BitOrder bitOrder) */ void SPIClass::setDataSize(uint32 datasize) { - _currentSetting->dataSize = datasize; - uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_DFF); - _currentSetting->spi_d->regs->CR1 = cr1 | (datasize & SPI_CR1_DFF); + _currentSetting->dataSize = datasize; + uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_DFF); + uint8 en = spi_is_enabled(_currentSetting->spi_d); + spi_peripheral_disable(_currentSetting->spi_d); + _currentSetting->spi_d->regs->CR1 = cr1 | (datasize & SPI_CR1_DFF) | en; } void SPIClass::setDataMode(uint8_t dataMode) @@ -243,59 +244,44 @@ bit 0 - CPHA : Clock phase If someone finds this is not the case or sees a logic error with this let me know ;-) */ - #ifdef SPI_DEBUG - Serial.print("Data mode set to "); Serial.println(dataMode); - #endif - _currentSetting->dataMode = dataMode; - uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_CPOL|SPI_CR1_CPHA); - _currentSetting->spi_d->regs->CR1 = cr1 | (dataMode & (SPI_CR1_CPOL|SPI_CR1_CPHA)); + _currentSetting->dataMode = dataMode; + uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_CPOL|SPI_CR1_CPHA); + _currentSetting->spi_d->regs->CR1 = cr1 | (dataMode & (SPI_CR1_CPOL|SPI_CR1_CPHA)); } void SPIClass::beginTransaction(uint8_t pin, SPISettings settings) { - #ifdef SPI_DEBUG - Serial.println("SPIClass::beginTransaction"); - #endif - //_SSPin=pin; - //pinMode(_SSPin,OUTPUT); - //digitalWrite(_SSPin,LOW); - setBitOrder(settings.bitOrder); - setDataMode(settings.dataMode); - setDataSize(settings.dataSize); - setClockDivider(determine_baud_rate(_currentSetting->spi_d, settings.clock)); - begin(); + setBitOrder(settings.bitOrder); + setDataMode(settings.dataMode); + setDataSize(settings.dataSize); + setClockDivider(determine_baud_rate(_currentSetting->spi_d, settings.clock)); + begin(); } void SPIClass::beginTransactionSlave(SPISettings settings) { - #ifdef SPI_DEBUG - Serial.println(F("SPIClass::beginTransactionSlave")); - #endif - setBitOrder(settings.bitOrder); - setDataMode(settings.dataMode); - setDataSize(settings.dataSize); - beginSlave(); + setBitOrder(settings.bitOrder); + setDataMode(settings.dataMode); + setDataSize(settings.dataSize); + beginSlave(); } void SPIClass::endTransaction(void) { - #ifdef SPI_DEBUG - Serial.println("SPIClass::endTransaction"); - #endif - //digitalWrite(_SSPin,HIGH); + //digitalWrite(_SSPin,HIGH); #if false // code from SAM core - uint8_t mode = interruptMode; - if (mode > 0) { - if (mode < 16) { - if (mode & 1) PIOA->PIO_IER = interruptMask[0]; - if (mode & 2) PIOB->PIO_IER = interruptMask[1]; - if (mode & 4) PIOC->PIO_IER = interruptMask[2]; - if (mode & 8) PIOD->PIO_IER = interruptMask[3]; - } else { - if (interruptSave) interrupts(); - } - } + uint8_t mode = interruptMode; + if (mode > 0) { + if (mode < 16) { + if (mode & 1) PIOA->PIO_IER = interruptMask[0]; + if (mode & 2) PIOB->PIO_IER = interruptMask[1]; + if (mode & 4) PIOC->PIO_IER = interruptMask[2]; + if (mode & 8) PIOD->PIO_IER = interruptMask[3]; + } else { + if (interruptSave) interrupts(); + } + } #endif } @@ -304,211 +290,354 @@ void SPIClass::endTransaction(void) * I/O */ -uint8 SPIClass::read(void) { - uint8 buf[1]; - this->read(buf, 1); - return buf[0]; +uint16 SPIClass::read(void) +{ + while ( spi_is_rx_nonempty(_currentSetting->spi_d)==0 ) ; + return (uint16)spi_rx_reg(_currentSetting->spi_d); } -void SPIClass::read(uint8 *buf, uint32 len) { - uint32 rxed = 0; - while (rxed < len) { - while (!spi_is_rx_nonempty(_currentSetting->spi_d)) - ; - buf[rxed++] = (uint8)spi_rx_reg(_currentSetting->spi_d); +void SPIClass::read(uint8 *buf, uint32 len) +{ + if ( len == 0 ) return; + spi_rx_reg(_currentSetting->spi_d); // clear the RX buffer in case a byte is waiting on it. + spi_reg_map * regs = _currentSetting->spi_d->regs; + // start sequence: write byte 0 + regs->DR = 0x00FF; // write the first byte + // main loop + while ( (--len) ) { + while( !(regs->SR & SPI_SR_TXE) ); // wait for TXE flag + noInterrupts(); // go atomic level - avoid interrupts to surely get the previously received data + regs->DR = 0x00FF; // write the next data item to be transmitted into the SPI_DR register. This clears the TXE flag. + while ( !(regs->SR & SPI_SR_RXNE) ); // wait till data is available in the DR register + *buf++ = (uint8)(regs->DR); // read and store the received byte. This clears the RXNE flag. + interrupts(); // let systick do its job } + // read remaining last byte + while ( !(regs->SR & SPI_SR_RXNE) ); // wait till data is available in the Rx register + *buf++ = (uint8)(regs->DR); // read and store the received byte } -void SPIClass::write(uint16 data) { - // this->write(&data, 1); - - /* Added for 16bit data Victor Perez. Roger Clark - * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion, * by taking the Tx code from transfer(byte) - * The original method, of calling write(*data, length) . - * This almost doubles the speed of this function. - */ - - spi_tx_reg(_currentSetting->spi_d, data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)." - while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..." - while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." +void SPIClass::write(uint16 data) +{ + /* Added for 16bit data Victor Perez. Roger Clark + * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion, + * by taking the Tx code from transfer(byte) + * This almost doubles the speed of this function. + */ + spi_tx_reg(_currentSetting->spi_d, data); // write the data to be transmitted into the SPI_DR register (this clears the TXE flag) + while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..." + while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." } -//void SPIClass::write(uint8 byte) { - // this->write(&byte, 1); +void SPIClass::write16(uint16 data) +{ + // Added by stevestrong: write two consecutive bytes in 8 bit mode (DFF=0) + spi_tx_reg(_currentSetting->spi_d, data>>8); // write high byte + while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // Wait until TXE=1 + spi_tx_reg(_currentSetting->spi_d, data); // write low byte + while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // Wait until TXE=1 + while (spi_is_busy(_currentSetting->spi_d) != 0); // wait until BSY=0 +} - /* Roger Clark - * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion, * by taking the Tx code from transfer(byte) - * The original method, of calling write(*data, length) . - * This almost doubles the speed of this function. - */ - -// spi_tx_reg(_currentSetting->spi_d, byte); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)." -// while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..." -// while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." -//} - -void SPIClass::write(const uint8 *data, uint32 length) { - uint32 txed = 0; - while (txed < length) { - txed += spi_tx(_currentSetting->spi_d, data + txed, length - txed); +void SPIClass::write(uint16 data, uint32 n) +{ + // Added by stevstrong: Repeatedly send same data by the specified number of times + spi_reg_map * regs = _currentSetting->spi_d->regs; + while ( (n--)>0 ) { + regs->DR = data; // write the data to be transmitted into the SPI_DR register (this clears the TXE flag) + while ( (regs->SR & SPI_SR_TXE)==0 ) ; // wait till Tx empty } - while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "4. After writing the last data item into the SPI_DR register, wait until TXE=1 ..." - while (spi_is_busy(_currentSetting->spi_d) != 0); // "... then wait until BSY=0, this indicates that the transmission of the last data is complete." - // taken from SdSpiSTM32F1.cpp - Victor's lib, and adapted to support device selection - if (spi_is_rx_nonempty(_currentSetting->spi_d)) { - uint8_t b = spi_rx_reg(_currentSetting->spi_d); - } + while ( (regs->SR & SPI_SR_BSY) != 0); // wait until BSY=0 before returning } -uint16_t SPIClass::transfer16(uint16_t wr_data) const { - spi_tx_reg(_currentSetting->spi_d, wr_data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)." - while (spi_is_rx_nonempty(_currentSetting->spi_d) == 0); // "4. Wait until RXNE=1 ..." - uint16_t rd_data = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data." -// while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..." -// while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." - return rd_data; +void SPIClass::write(const void *data, uint32 length) +{ + spi_dev * spi_d = _currentSetting->spi_d; + spi_tx(spi_d, data, length); // data can be array of bytes or words + while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..." + while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." } -uint8 SPIClass::transfer(uint8 byte) const { - spi_tx_reg(_currentSetting->spi_d, byte); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)." - while (spi_is_rx_nonempty(_currentSetting->spi_d) == 0); // "4. Wait until RXNE=1 ..." - uint8 b = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data." - while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..." - while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." - return b; +uint8 SPIClass::transfer(uint8 byte) const +{ + spi_dev * spi_d = _currentSetting->spi_d; + spi_rx_reg(spi_d); // read any previous data + spi_tx_reg(spi_d, byte); // Write the data item to be transmitted into the SPI_DR register + while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..." + while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." + return (uint8)spi_rx_reg(spi_d); // "... and read the last received data." } + +uint16_t SPIClass::transfer16(uint16_t data) const +{ + // Modified by stevestrong: write & read two consecutive bytes in 8 bit mode (DFF=0) + // This is more effective than two distinct byte transfers + spi_dev * spi_d = _currentSetting->spi_d; + spi_rx_reg(spi_d); // read any previous data + spi_tx_reg(spi_d, data>>8); // write high byte + while (spi_is_tx_empty(spi_d) == 0); // wait until TXE=1 + while (spi_is_busy(spi_d) != 0); // wait until BSY=0 + uint16_t ret = spi_rx_reg(spi_d)<<8; // read and shift high byte + spi_tx_reg(spi_d, data); // write low byte + while (spi_is_tx_empty(spi_d) == 0); // wait until TXE=1 + while (spi_is_busy(spi_d) != 0); // wait until BSY=0 + ret += spi_rx_reg(spi_d); // read low byte + return ret; +} + /* Roger Clark and Victor Perez, 2015 * Performs a DMA SPI transfer with at least a receive buffer. * If a TX buffer is not provided, FF is sent over and over for the lenght of the transfer. * On exit TX buffer is not modified, and RX buffer cotains the received data. * Still in progress. */ -uint8 SPIClass::dmaTransfer(uint8 *transmitBuf, uint8 *receiveBuf, uint16 length) { - if (length == 0) return 0; - uint8 b = 0; - if (spi_is_rx_nonempty(_currentSetting->spi_d) == 1) b = spi_rx_reg(_currentSetting->spi_d); //Clear the RX buffer in case a byte is waiting on it. -// dma1_ch3_Active=true; +void SPIClass::dmaTransferSet(const void *transmitBuf, void *receiveBuf) { dma_init(_currentSetting->spiDmaDev); -// dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event); - - // RX - spi_rx_dma_enable(_currentSetting->spi_d); - dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR, DMA_SIZE_8BITS, - receiveBuf, DMA_SIZE_8BITS, (DMA_MINC_MODE | DMA_TRNS_CMPLT));// receive buffer DMA - dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, length); - - // TX - spi_tx_dma_enable(_currentSetting->spi_d); - if (!transmitBuf) { - static uint8_t ff = 0XFF; - transmitBuf = &ff; - dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, DMA_SIZE_8BITS, - transmitBuf, DMA_SIZE_8BITS, (DMA_FROM_MEM | DMA_TRNS_CMPLT));// Transmit FF repeatedly - } - else { - dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, DMA_SIZE_8BITS, - transmitBuf, DMA_SIZE_8BITS, (DMA_MINC_MODE | DMA_FROM_MEM | DMA_TRNS_CMPLT));// Transmit buffer DMA - } - dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length); - - dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);// enable receive - dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit - -// while (dma1_ch3_Active); -// if (receiveBuf) { - uint32_t m = millis(); - while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & 0x2)==0) {//Avoid interrupts and just loop waiting for the flag to be set. - if ((millis() - m) > 100) { -// dma1_ch3_Active = 0; - b = 2; - break; - } + //spi_rx_dma_enable(_currentSetting->spi_d); + //spi_tx_dma_enable(_currentSetting->spi_d); + dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS; + dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size, + receiveBuf, dma_bit_size, (DMA_MINC_MODE | DMA_TRNS_CMPLT ));// receive buffer DMA + if (!transmitBuf) { + transmitBuf = &ff; + dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size, + (volatile void*)transmitBuf, dma_bit_size, (DMA_FROM_MEM));// Transmit FF repeatedly } - dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel); + else { + dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size, + (volatile void*)transmitBuf, dma_bit_size, (DMA_MINC_MODE | DMA_FROM_MEM ));// Transmit buffer DMA + } + dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, DMA_PRIORITY_LOW); + dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, DMA_PRIORITY_VERY_HIGH); +} -// } - while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..." - while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." +uint8 SPIClass::dmaTransferRepeat(uint16 length) { + if (length == 0) return 0; + if (spi_is_rx_nonempty(_currentSetting->spi_d) == 1) spi_rx_reg(_currentSetting->spi_d); + _currentSetting->state = SPI_STATE_TRANSFER; + dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, length); + dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length); + dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);// enable receive + dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit + spi_rx_dma_enable(_currentSetting->spi_d); + spi_tx_dma_enable(_currentSetting->spi_d); + if (_currentSetting->receiveCallback){ + return 0; + } + //uint32_t m = millis(); + uint8 b = 0; + uint32_t m = millis(); + while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) { + //Avoid interrupts and just loop waiting for the flag to be set. + if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; } + } + + while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..." + while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." + spi_tx_dma_disable(_currentSetting->spi_d); + spi_rx_dma_disable(_currentSetting->spi_d); dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel); - dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel); - spi_rx_dma_disable(_currentSetting->spi_d); // And disable generation of DMA request from the SPI port so other peripherals can use the channels - spi_tx_dma_disable(_currentSetting->spi_d); - if (spi_is_rx_nonempty(_currentSetting->spi_d) != 0){; // "4. Wait until RXNE=1 ..." - uint8 x = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data." - } + dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel); + dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel); + dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel); + _currentSetting->state = SPI_STATE_READY; return b; } +/* Roger Clark and Victor Perez, 2015 +* Performs a DMA SPI transfer with at least a receive buffer. +* If a TX buffer is not provided, FF is sent over and over for the length of the transfer. +* On exit TX buffer is not modified, and RX buffer contains the received data. +* Still in progress. +*/ + +uint8 SPIClass::dmaTransfer(const void *transmitBuf, void *receiveBuf, uint16 length) { + dmaTransferSet(transmitBuf, receiveBuf); + return dmaTransferRepeat(length); +} + /* Roger Clark and Victor Perez, 2015 * Performs a DMA SPI send using a TX buffer. * On exit TX buffer is not modified. * Still in progress. +* 2016 - stevstrong - reworked to automatically detect bit size from SPI setting */ -uint8 SPIClass::dmaSend(uint8 *transmitBuf, uint16 length, bool minc) { - if (length == 0) return 0; - uint32 flags = ((DMA_MINC_MODE * minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT); - uint8 b = 0; -// dma1_ch3_Active=true; - dma_init(_currentSetting->spiDmaDev); -// dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event); - // TX - spi_tx_dma_enable(_currentSetting->spi_d); - dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, DMA_SIZE_8BITS, - transmitBuf, DMA_SIZE_8BITS, flags);// Transmit buffer DMA - dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length); - dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit - -// while (dma1_ch3_Active); - while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & 0x2)==0); //Avoid interrupts and just loop waiting for the flag to be set. - dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel); +void SPIClass::dmaSendSet(const void * transmitBuf, bool minc) { + uint32 flags = ( (DMA_MINC_MODE*minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT); + dma_init(_currentSetting->spiDmaDev); + dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS; + dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size, + (volatile void*)transmitBuf, dma_bit_size, flags);// Transmit buffer DMA + dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, DMA_PRIORITY_LOW); +} - while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..." - while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." - dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel); - spi_tx_dma_disable(_currentSetting->spi_d); - if (spi_is_rx_nonempty(_currentSetting->spi_d) != 0){; // "4. Wait until RXNE=1 ..." - uint8 x = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data." - } +uint8 SPIClass::dmaSendRepeat(uint16 length) { + if (length == 0) return 0; + dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel); + dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length); + _currentSetting->state = SPI_STATE_TRANSMIT; + dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit + spi_tx_dma_enable(_currentSetting->spi_d); + if (_currentSetting->transmitCallback) + { + return 0; + } + uint32_t m = millis(); + uint8 b = 0; + while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) { + //Avoid interrupts and just loop waiting for the flag to be set. + if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; } + } + while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..." + while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." + spi_tx_dma_disable(_currentSetting->spi_d); + dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel); + dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel); + _currentSetting->state = SPI_STATE_READY; return b; } -uint8 SPIClass::dmaSend(uint16 *transmitBuf, uint16 length, bool minc) { - if (length == 0) return 0; - uint32 flags = ((DMA_MINC_MODE * minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT); - uint8 b; - dma1_ch3_Active=true; +uint8 SPIClass::dmaSend(const void * transmitBuf, uint16 length, bool minc) { + dmaSendSet(transmitBuf, minc); + return dmaSendRepeat(length); +} + +uint8 SPIClass::dmaSendAsync(const void * transmitBuf, uint16 length, bool minc) { + uint8 b = 0; + + if (_currentSetting->state != SPI_STATE_READY) + { + + uint32_t m = millis(); + while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {//Avoid interrupts and just loop waiting for the flag to be set. + //delayMicroseconds(10); + if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; } + } + + while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..." + while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." + spi_tx_dma_disable(_currentSetting->spi_d); + dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel); + _currentSetting->state = SPI_STATE_READY; + } + + if (length == 0) return 0; + uint32 flags = ( (DMA_MINC_MODE*minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT); + dma_init(_currentSetting->spiDmaDev); -// dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event); + // TX + dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS; + dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size, + (volatile void*)transmitBuf, dma_bit_size, flags);// Transmit buffer DMA + dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length); + dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel); + dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit + spi_tx_dma_enable(_currentSetting->spi_d); - // TX - spi_tx_dma_enable(_currentSetting->spi_d); - dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, DMA_SIZE_16BITS, - transmitBuf, DMA_SIZE_16BITS, flags);// Transmit buffer DMA - dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length); - dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit - -// while (dma1_ch3_Active); - while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & 0x2)==0); //Avoid interrupts and just loop waiting for the flag to be set. - dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel); + _currentSetting->state = SPI_STATE_TRANSMIT; - while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..." - while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." - dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel); - spi_tx_dma_disable(_currentSetting->spi_d); - if (spi_is_rx_nonempty(_currentSetting->spi_d) != 0){; // "4. Wait until RXNE=1 ..." - b = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data." - } return b; } +/* + New functions added to manage callbacks. + Victor Perez 2017 +*/ + +void SPIClass::onReceive(void(*callback)(void)) { + _currentSetting->receiveCallback = callback; + if (callback){ + switch (_currentSetting->spi_d->clk_id) { + case RCC_SPI1: + dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi1EventCallback); + break; + case RCC_SPI2: + dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi2EventCallback); + break; + #if BOARD_NR_SPI >= 3 + case RCC_SPI3: + dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi3EventCallback); + break; + #endif + default: + ASSERT(0); + } + } + else { + dma_detach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel); + } +} + +void SPIClass::onTransmit(void(*callback)(void)) { + _currentSetting->transmitCallback = callback; + if (callback){ + switch (_currentSetting->spi_d->clk_id) { + case RCC_SPI1: + dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi1EventCallback); + break; + case RCC_SPI2: + dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi2EventCallback); + break; + #if BOARD_NR_SPI >= 3 + case RCC_SPI3: + dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi3EventCallback); + break; + #endif + default: + ASSERT(0); + } + } + else { + dma_detach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel); + } +} + +/* + TODO: check if better to first call the customer code, next disable the DMA requests. + Also see if we need to check whether callbacks are set or not, may be better to be checked during the initial setup and only set the callback to EventCallback if they are set. +*/ + +void SPIClass::EventCallback() { + while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..." + while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0" + switch (_currentSetting->state) { + case SPI_STATE_TRANSFER: + while (spi_is_rx_nonempty(_currentSetting->spi_d)); + _currentSetting->state = SPI_STATE_READY; + spi_tx_dma_disable(_currentSetting->spi_d); + spi_rx_dma_disable(_currentSetting->spi_d); + //dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel); + //dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel); + + if (_currentSetting->receiveCallback) + { + _currentSetting->receiveCallback(); + } + break; + case SPI_STATE_TRANSMIT: + _currentSetting->state = SPI_STATE_READY; + spi_tx_dma_disable(_currentSetting->spi_d); + //dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel); + if (_currentSetting->transmitCallback) + { + _currentSetting->transmitCallback(); + } + + break; + default: + // we shouldn't get here, so better to add an assert and fail. + return; + } +} + void SPIClass::attachInterrupt(void) { - // Should be enableInterrupt() + // Should be enableInterrupt() } void SPIClass::detachInterrupt(void) { - // Should be disableInterrupt() + // Should be disableInterrupt() } /* @@ -536,28 +665,39 @@ uint8 SPIClass::nssPin(void) { */ uint8 SPIClass::send(uint8 data) { - uint8 buf[] = {data}; - return this->send(buf, 1); + this->write(data); + return 1; } uint8 SPIClass::send(uint8 *buf, uint32 len) { - uint32 txed = 0; - uint8 ret = 0; - while (txed < len) { - this->write(buf[txed++]); - ret = this->read(); - } - return ret; + this->write(buf, len); + return len; } uint8 SPIClass::recv(void) { return this->read(); } - /* - * Auxiliary functions - */ + DMA call back functions, one per port. +*/ + +void SPIClass::_spi1EventCallback() +{ + reinterpret_cast(_spi1_this)->EventCallback(); +} + +void SPIClass::_spi2EventCallback() { + reinterpret_cast(_spi2_this)->EventCallback(); +} +#if BOARD_NR_SPI >= 3 +void SPIClass::_spi3EventCallback() { + reinterpret_cast(_spi3_this)->EventCallback(); +} +#endif +/* +* Auxiliary functions +*/ static const spi_pins* dev_to_spi_pins(spi_dev *dev) { switch (dev->clk_id) { @@ -598,8 +738,8 @@ static void configure_gpios(spi_dev *dev, bool as_master) { disable_pwm(mosii); spi_config_gpios(dev, as_master, nssi->gpio_device, nssi->gpio_bit, - scki->gpio_device, scki->gpio_bit, misoi->gpio_bit, - mosii->gpio_bit); + scki->gpio_device, scki->gpio_bit, misoi->gpio_bit, + mosii->gpio_bit); } static const spi_baud_rate baud_rates[8] __FLASH__ = { @@ -614,26 +754,23 @@ static const spi_baud_rate baud_rates[8] __FLASH__ = { }; /* - * Note: This assumes you're on a LeafLabs-style board - * (CYCLES_PER_MICROSECOND == 72, APB2 at 72MHz, APB1 at 36MHz). - */ +* Note: This assumes you're on a LeafLabs-style board +* (CYCLES_PER_MICROSECOND == 72, APB2 at 72MHz, APB1 at 36MHz). +*/ static spi_baud_rate determine_baud_rate(spi_dev *dev, uint32_t freq) { - uint32_t clock = 0, i; - #ifdef SPI_DEBUG - Serial.print("determine_baud_rate("); Serial.print(freq); Serial.println(")"); - #endif + uint32_t clock = 0, i; switch (rcc_dev_clk(dev->clk_id)) { - case RCC_APB2: clock = STM32_PCLK2; break; // 72 Mhz - case RCC_APB1: clock = STM32_PCLK1; break; // 36 Mhz + case RCC_APB2: clock = STM32_PCLK2; break; // 72 Mhz + case RCC_APB1: clock = STM32_PCLK1; break; // 36 Mhz } clock /= 2; i = 0; while (i < 7 && freq < clock) { - clock /= 2; - i++; + clock /= 2; + i++; } - return baud_rates[i]; + return baud_rates[i]; } SPIClass SPI(1); diff --git a/BootLoaders/Boards/stm32/libraries/SPI/src/SPI.h b/BootLoaders/Boards/stm32/libraries/SPI/src/SPI.h index e949051..09c50a4 100644 --- a/BootLoaders/Boards/stm32/libraries/SPI/src/SPI.h +++ b/BootLoaders/Boards/stm32/libraries/SPI/src/SPI.h @@ -99,6 +99,13 @@ #define DATA_SIZE_8BIT SPI_CR1_DFF_8_BIT #define DATA_SIZE_16BIT SPI_CR1_DFF_16_BIT +typedef enum { + SPI_STATE_IDLE, + SPI_STATE_READY, + SPI_STATE_RECEIVE, + SPI_STATE_TRANSMIT, + SPI_STATE_TRANSFER + } spi_mode_t; class SPISettings { public: SPISettings(uint32_t clock, BitOrder bitOrder, uint8_t dataMode) { @@ -115,6 +122,13 @@ public: init_MightInline(clock, bitOrder, dataMode, dataSize); } } + SPISettings(uint32_t clock) { + if (__builtin_constant_p(clock)) { + init_AlwaysInline(clock, MSBFIRST, SPI_MODE0, DATA_SIZE_8BIT); + } else { + init_MightInline(clock, MSBFIRST, SPI_MODE0, DATA_SIZE_8BIT); + } + } SPISettings() { init_AlwaysInline(4000000, MSBFIRST, SPI_MODE0, DATA_SIZE_8BIT); } private: void init_MightInline(uint32_t clock, BitOrder bitOrder, uint8_t dataMode, uint32_t dataSize) { @@ -127,21 +141,31 @@ private: this->dataSize = dataSize; } uint32_t clock; + uint32_t dataSize; + uint32_t clockDivider; BitOrder bitOrder; uint8_t dataMode; - uint32_t dataSize; - + uint8_t _SSPin; + volatile spi_mode_t state; spi_dev *spi_d; - uint8_t _SSPin; - uint32_t clockDivider; dma_channel spiRxDmaChannel, spiTxDmaChannel; dma_dev* spiDmaDev; + void (*receiveCallback)(void) = NULL; + void (*transmitCallback)(void) = NULL; friend class SPIClass; }; -volatile static bool dma1_ch3_Active; +/* + Should move this to within the class once tested out, just for tidyness +*/ +static uint8_t __attribute__ ((unused)) ff = 0XFF; +static void __attribute__ ((unused)) (*_spi1_this); +static void __attribute__ ((unused)) (*_spi2_this); +#if BOARD_NR_SPI >= 3 +static void __attribute__ ((unused)) (*_spi3_this); +#endif /** * @brief Wirish SPI interface. @@ -152,8 +176,6 @@ volatile static bool dma1_ch3_Active; class SPIClass { public: - - /** * @param spiPortNumber Number of the SPI port to manage. */ @@ -163,8 +185,6 @@ public: * Set up/tear down */ - - /** * @brief Equivalent to begin(SPI_1_125MHZ, MSBFIRST, 0). */ @@ -210,46 +230,55 @@ public: */ void setDataSize(uint32 ds); - + /* Victor Perez 2017. Added to set and clear callback functions for callback + * on DMA transfer completion. + * onReceive used to set the callback in case of dmaTransfer (tx/rx), once rx is completed + * onTransmit used to set the callback in case of dmaSend (tx only). That function + * will NOT be called in case of TX/RX + */ + void onReceive(void(*)(void)); + void onTransmit(void(*)(void)); + /* * I/O */ /** - * @brief Return the next unread byte. + * @brief Return the next unread byte/word. * - * If there is no unread byte waiting, this function will block + * If there is no unread byte/word waiting, this function will block * until one is received. */ - uint8 read(void); + uint16 read(void); /** * @brief Read length bytes, storing them into buffer. * @param buffer Buffer to store received bytes into. - * @param length Number of bytes to store in buffer. This + * @param length Number of bytes to store in buffer. This * function will block until the desired number of * bytes have been read. */ void read(uint8 *buffer, uint32 length); /** - * @brief Transmit a byte. - * @param data Byte to transmit. - */ -// void write(uint8 data); - - /** - * @brief Transmit a half word. + * @brief Transmit one byte/word. * @param data to transmit. */ - void write(uint16 data); - + void write(uint16 data); + void write16(uint16 data); // write 2 bytes in 8 bit mode (DFF=0) + /** - * @brief Transmit multiple bytes. - * @param buffer Bytes to transmit. - * @param length Number of bytes in buffer to transmit. + * @brief Transmit one byte/word a specified number of times. + * @param data to transmit. */ - void write(const uint8 *buffer, uint32 length); + void write(uint16 data, uint32 n); + + /** + * @brief Transmit multiple bytes/words. + * @param buffer Bytes/words to transmit. + * @param length Number of bytes/words in buffer to transmit. + */ + void write(const void * buffer, uint32 length); /** * @brief Transmit a byte, then return the next unread byte. @@ -261,9 +290,10 @@ public: */ uint8 transfer(uint8 data) const; uint16_t transfer16(uint16_t data) const; - + /** * @brief Sets up a DMA Transfer for "length" bytes. + * The transfer mode (8 or 16 bit mode) is evaluated from the SPI peripheral setting. * * This function transmits and receives to buffers. * @@ -271,31 +301,25 @@ public: * @param receiveBuf buffer Bytes to save received data. * @param length Number of bytes in buffer to transmit. */ - uint8 dmaTransfer(uint8 *transmitBuf, uint8 *receiveBuf, uint16 length); + uint8 dmaTransfer(const void * transmitBuf, void * receiveBuf, uint16 length); + void dmaTransferSet(const void *transmitBuf, void *receiveBuf); + uint8 dmaTransferRepeat(uint16 length); /** - * @brief Sets up a DMA Transmit for bytes. + * @brief Sets up a DMA Transmit for SPI 8 or 16 bit transfer mode. + * The transfer mode (8 or 16 bit mode) is evaluated from the SPI peripheral setting. * - * This function transmits and does not care about the RX fifo. - * - * @param transmitBuf buffer Bytes to transmit, - * @param length Number of bytes in buffer to transmit. - * @param minc Set to use Memory Increment mode, clear to use Circular mode. - */ - uint8 dmaSend(uint8 *transmitBuf, uint16 length, bool minc = 1); - - /** - * @brief Sets up a DMA Transmit for half words. - * SPI PERFIPHERAL MUST BE SET TO 16 BIT MODE BEFORE - * - * This function transmits and does not care about the RX fifo. + * This function only transmits and does not care about the RX fifo. * * @param data buffer half words to transmit, * @param length Number of bytes in buffer to transmit. - * @param minc Set to use Memory Increment mode (default if blank), clear to use Circular mode. + * @param minc Set to use Memory Increment mode, clear to use Circular mode. */ - uint8 dmaSend(uint16 *transmitBuf, uint16 length, bool minc = 1); + uint8 dmaSend(const void * transmitBuf, uint16 length, bool minc = 1); + void dmaSendSet(const void * transmitBuf, bool minc); + uint8 dmaSendRepeat(uint16 length); + uint8 dmaSendAsync(const void * transmitBuf, uint16 length, bool minc = 1); /* * Pin accessors */ @@ -327,23 +351,20 @@ public: * this HardwareSPI instance. */ spi_dev* c_dev(void) { return _currentSetting->spi_d; } - - - spi_dev *dev(){ return _currentSetting->spi_d;} - - /** - * @brief Sets the number of the SPI peripheral to be used by - * this HardwareSPI instance. - * - * @param spi_num Number of the SPI port. 1-2 in low density devices - * or 1-3 in high density devices. - */ - - void setModule(int spi_num) - { - _currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed - } + spi_dev *dev(){ return _currentSetting->spi_d;} + + /** + * @brief Sets the number of the SPI peripheral to be used by + * this HardwareSPI instance. + * + * @param spi_num Number of the SPI port. 1-2 in low density devices + * or 1-3 in high density devices. + */ + void setModule(int spi_num) + { + _currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed + } /* -- The following methods are deprecated --------------------------- */ @@ -376,21 +397,25 @@ public: * @see HardwareSPI::read() */ uint8 recv(void); - + private: -/* - static inline void DMA1_CH3_Event() { - dma1_ch3_Active = 0; -// dma_disable(DMA1, DMA_CH3); -// dma_disable(DMA1, DMA_CH2); - - // To Do. Need to wait for - } -*/ + SPISettings _settings[BOARD_NR_SPI]; SPISettings *_currentSetting; - + void updateSettings(void); + /* + * Functions added for DMA transfers with Callback. + * Experimental. + */ + + void EventCallback(void); + + static void _spi1EventCallback(void); + static void _spi2EventCallback(void); + #if BOARD_NR_SPI >= 3 + static void _spi3EventCallback(void); + #endif /* spi_dev *spi_d; uint8_t _SSPin; diff --git a/BootLoaders/Boards/stm32/platform.txt b/BootLoaders/Boards/stm32/platform.txt index 75cf2c6..d008733 100644 --- a/BootLoaders/Boards/stm32/platform.txt +++ b/BootLoaders/Boards/stm32/platform.txt @@ -1,10 +1,12 @@ -# +# +# Customized for the STM32 multi 4-in-1 board. +# Based on an STM32F103CB MCU. # # For more info: # https://github.com/arduino/Arduino/wiki/Arduino-IDE-1.5---3rd-party-Hardware-specification name=Multi 4-in-1 STM32 -version=1.0.0 +version=1.0.3 compiler.warning_flags=-w -DDEBUG_LEVEL=DEBUG_NONE compiler.warning_flags.none=-w -DDEBUG_LEVEL=DEBUG_NONE @@ -46,8 +48,6 @@ build.hs_flag= build.upload_flags= build.extra_flags= {build.upload_flags} {build.cpu_flags} {build.hs_flag} {build.common_flags} - - # These can be overridden in platform.local.txt compiler.c.extra_flags= compiler.c.elf.extra_flags="-L{build.variant.path}/ld" @@ -56,12 +56,8 @@ compiler.S.extra_flags= compiler.ar.extra_flags= compiler.elf2hex.extra_flags= - compiler.libs.c.flags="-I{build.system.path}/libmaple" "-I{build.system.path}/libmaple/include" "-I{build.system.path}/libmaple/stm32f1/include" "-I{build.system.path}/libmaple/usb/stm32f1" "-I{build.system.path}/libmaple/usb/usb_lib" - - - # USB Flags # --------- ## build.usb_flags=-DUSB_VID={build.vid} -DUSB_PID={build.pid} -DUSBCON '-DUSB_MANUFACTURER={build.usb_manufacturer}' '-DUSB_PRODUCT={build.usb_product}' diff --git a/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/atomic.h b/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/atomic.h new file mode 100644 index 0000000..db5e489 --- /dev/null +++ b/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/atomic.h @@ -0,0 +1,69 @@ +/* +* This is port of Dean Camera's ATOMIC_BLOCK macros for AVR to ARM Cortex M3 +* v1.0 +* Mark Pendrith, Nov 27, 2012. +* +* From Mark: +* >When I ported the macros I emailed Dean to ask what attribution would be +* >appropriate, and here is his response: +* > +* >>Mark, +* >>I think it's great that you've ported the macros; consider them +* >>public domain, to do with whatever you wish. I hope you find them useful. +* >> +* >>Cheers! +* >>- Dean +*/ + +#ifndef _CORTEX_M3_ATOMIC_H_ +#define _CORTEX_M3_ATOMIC_H_ + +static __inline__ uint32_t __get_primask(void) \ +{ uint32_t primask = 0; \ + __asm__ volatile ("MRS %[result], PRIMASK\n\t":[result]"=r"(primask)::); \ + return primask; } // returns 0 if interrupts enabled, 1 if disabled + +static __inline__ void __set_primask(uint32_t setval) \ +{ __asm__ volatile ("MSR PRIMASK, %[value]\n\t""dmb\n\t""dsb\n\t""isb\n\t"::[value]"r"(setval):); \ + __asm__ volatile ("" ::: "memory");} + +static __inline__ uint32_t __iSeiRetVal(void) \ +{ __asm__ volatile ("CPSIE i\n\t""dmb\n\t""dsb\n\t""isb\n\t"); \ + __asm__ volatile ("" ::: "memory"); return 1; } + +static __inline__ uint32_t __iCliRetVal(void) \ +{ __asm__ volatile ("CPSID i\n\t""dmb\n\t""dsb\n\t""isb\n\t"); \ + __asm__ volatile ("" ::: "memory"); return 1; } + +static __inline__ void __iSeiParam(const uint32_t *__s) \ +{ __asm__ volatile ("CPSIE i\n\t""dmb\n\t""dsb\n\t""isb\n\t"); \ + __asm__ volatile ("" ::: "memory"); (void)__s; } + +static __inline__ void __iCliParam(const uint32_t *__s) \ +{ __asm__ volatile ("CPSID i\n\t""dmb\n\t""dsb\n\t""isb\n\t"); \ + __asm__ volatile ("" ::: "memory"); (void)__s; } + +static __inline__ void __iRestore(const uint32_t *__s) \ +{ __set_primask(*__s); __asm__ volatile ("dmb\n\t""dsb\n\t""isb\n\t"); \ + __asm__ volatile ("" ::: "memory"); } + + +#define ATOMIC_BLOCK(type) \ +for ( type, __ToDo = __iCliRetVal(); __ToDo ; __ToDo = 0 ) + +#define ATOMIC_RESTORESTATE \ +uint32_t primask_save __attribute__((__cleanup__(__iRestore))) = __get_primask() + +#define ATOMIC_FORCEON \ +uint32_t primask_save __attribute__((__cleanup__(__iSeiParam))) = 0 + +#define NONATOMIC_BLOCK(type) \ +for ( type, __ToDo = __iSeiRetVal(); __ToDo ; __ToDo = 0 ) + +#define NONATOMIC_RESTORESTATE \ +uint32_t primask_save __attribute__((__cleanup__(__iRestore))) = __get_primask() + +#define NONATOMIC_FORCEOFF \ +uint32_t primask_save __attribute__((__cleanup__(__iCliParam))) = 0 + +#endif diff --git a/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/ring_buffer.h b/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/ring_buffer.h index eb38634..e99fe62 100644 --- a/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/ring_buffer.h +++ b/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/ring_buffer.h @@ -52,9 +52,9 @@ extern "C"{ * One byte is left free to distinguish empty from full. */ typedef struct ring_buffer { volatile uint8 *buf; /**< Buffer items are stored into */ - uint16 head; /**< Index of the next item to remove */ - uint16 tail; /**< Index where the next item will get inserted */ - uint16 size; /**< Buffer capacity minus one */ + volatile uint16 head; /**< Index of the next item to remove */ + volatile uint16 tail; /**< Index where the next item will get inserted */ + volatile uint16 size; /**< Buffer capacity minus one */ } ring_buffer; /** diff --git a/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/sdio.h b/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/sdio.h new file mode 100644 index 0000000..dec31c8 --- /dev/null +++ b/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/sdio.h @@ -0,0 +1,270 @@ +/****************************************************************************** + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file sdio.h + * @brief Secure digital input/output interface. + */ + +#ifndef _SDIO_H_ +#define _SDIO_H_ + +#include +#include +#include + + +/* +#include +#include + +//#include +#include +//#include + */ + +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) + +/* + * DMA controller and channel used in STM32F103 + */ + +#define SDIO_DMA_DEV DMA2 +#define SDIO_DMA_CHANNEL DMA_CH4 +/* +#ifdef __cplusplus +extern "C" { +#endif +*/ + +/* + * Register maps and devices + */ + +// SDIO register map type +typedef struct sdio_reg_map { + __io uint32 POWER; // 0x00 + __io uint32 CLKCR; // 0x04 + __io uint32 ARG; // 0x08 + __io uint32 CMD; // 0x0C + __io uint32 RESPCMD; // 0x10 (0x3F) + const uint32 RESP[4]; // 0x14 - contain the card status, which is part of the received response. + __io uint32 DTIMER; // 0x24 - contains the data timeout period, in card bus clock periods. + __io uint32 DLEN; // 0x28 (0x01FF FFFF) - contains the number of data bytes to be transferred + __io uint32 DCTRL; // 0x2C + __io uint32 DCOUNT; // 0x30 (0x01FF FFFF) + __io uint32 STA; // 0x34 + __io uint32 ICR; // 0x38 + __io uint32 MASK; // 0x3C + const uint32 RESERVED1[2]; + __io uint32 FIFOCNT; // 0x48 (0x01FF FFFF) + const uint32 RESERVED2[13]; + __io uint32 FIFO; // 0x80 +} sdio_reg_map; +#define sdio_dev sdio_reg_map + +/** SDIO register map base pointer */ +#define SDIO_BASE ((struct sdio_reg_map*)0x40018000) + +extern sdio_dev * SDIO; + +/* + * Register bit definitions + */ + +/* NOR/PSRAM chip-select control registers */ + +// SDIO_POWER register bits +// At least seven HCLK clock periods are needed between two write accesses to this register. +// After a data write, data cannot be written to this register for three SDIOCLK clock periods +// plus two PCLK2 clock periods. +#define SDIO_POWER_PWRCTRL_OFF 0x00 +#define SDIO_POWER_PWRCTRL_ON 0x03 + +// SDIO_CLKCR register bits +// Controls the SDIO_CK output clock. +// After a data write, data cannot be written to this register for three SDIOCLK clock periods +// plus two PCLK2 clock periods. SDIO_CK can also be stopped during the read wait interval +// for SD I/O cards: in this case the SDIO_CLKCR register does not control SDIO_CK. +#define SDIO_CLKCR_HWFC_EN (1<<14) // HW Flow Control enable - DON'T USE!!! (see errata sheet 2.12.1) + // Overrun errors (Rx mode) and FIFO underrun (Tx mode) + // should be managed by the application software. +#define SDIO_CLKCR_NEGEDGE (1<<13) // SDIO_CK de-phasing selection bit - DON'T USE!!! (see errata sheet 2.12.4) +#define SDIO_CLKCR_WIDBUS (3<<11) // Data bus width +#define SDIO_CLKCR_WIDBUS_1BIT (0<<11) // 1 bit (SDIO_D0 used) +#define SDIO_CLKCR_WIDBUS_4BIT (1<<11) // 4-bit (SDIO_D[3:0] used) +#define SDIO_CLKCR_BYPASS (1<<10) // Clock divider bypass enable bit - SDIO_CK = SDIOCLK, CLKDIV not relevant. +#define SDIO_CLKCR_PWRSAV (1<<9) // 0: SDIO_CK clock is always enabled, 1: SDIO_CK is only enabled when the bus is active +#define SDIO_CLKCR_CLKEN (1<<8) // Clock enable +#define SDIO_CLKCR_CLKDIV (0xFF) // SDIO_CK = SDIOCLK / [CLKDIV + 2] +#define SDIOCLK 72000000UL // SDIO master clock frequency + +// SDIO_CMD register bits +// After a data write, data cannot be written to this register for three SDIOCLK clock periods +// plus two PCLK2 clock periods. +// MultiMediaCards can send two kinds of response: short responses, 48 bits long, or long +// responses,136 bits long. SD card and SD I/O card can send only short responses, the +// argument can vary according to the type of response: the software will distinguish the type +// of response according to the sent command. CE-ATA devices send only short responses. +#define SDIO_CMD_ATACMD (1<<14) +#define SDIO_CMD_NIEN (1<<13) +#define SDIO_CMD_ENCMDCOMPL (1<<12) +#define SDIO_CMD_SDIOSUSPEND (1<<11) +#define SDIO_CMD_CPSMEN (1<<10) +#define SDIO_CMD_WAITPEND (1<<9) +#define SDIO_CMD_WAITINT (1<<8) +#define SDIO_CMD_WAITRESP (3<<6) +#define SDIO_CMD_WAIT_NO_RESP (0<<6) +#define SDIO_CMD_WAIT_SHORT_RESP (1<<6) +#define SDIO_CMD_WAIT_LONG_RESP (3<<6) +#define SDIO_CMD_CMDINDEX (0x3F) + +// SDIO_DLEN register bits +// For a block data transfer, the value in the data length register must be a multiple of the block +// size (see SDIO_DCTRL). A data transfer must be written to the data timer register and the +// data length register before being written to the data control register. +// For an SDIO multibyte transfer the value in the data length register must be between 1 and 512. +#define SDIO_DLEN_DATALENGTH (0x01FFFFFF) + +// SDIO_DCTRL register bits +// Controls the data path state machine (DPSM). +// After a data write, data cannot be written to this register for three SDIOCLK clock periods +// plus two PCLK2 clock periods. +#define SDIO_DCTRL_SDIOEN (1<<11) // the DPSM performs an SD I/O-card-specific operation. +#define SDIO_DCTRL_RWMODE (1<<10) // 0: Read Wait control stopping SDIO_D2, 1:Read Wait control using SDIO_CK +#define SDIO_DCTRL_RWSTOP (1<<9) // 0: Read wait in progress if RWSTART bit is set, 1: Enable for read wait stop if RWSTART bit is set +#define SDIO_DCTRL_RWSTART (1<<8) // read wait operation starts +#define SDIO_DCTRL_DBLOCKSIZE (0xF<<4) // Define the data block length when the block data transfer mode is selected: 2^N bytes +#define SDIO_BLOCKSIZE_64 (6<<4) +#define SDIO_BLOCKSIZE_512 (9<<4) +#define SDIO_DCTRL_DMAEN (1<<3) // DMA enable +#define SDIO_DCTRL_DTMODE (1<<2) // Data transfer mode selection: 0: Block data transfer, 1: Stream or SDIO multi-byte data transfer +#define SDIO_DCTRL_DTDIR (1<<1) // Data transfer direction selection: 0: From controller to card, 1: From card to controller. +#define SDIO_DIR_TX (0<<1) +#define SDIO_DIR_RX (1<<1) +#define SDIO_DCTRL_DTEN (1<<0) // Start data transfer. Depending on the direction bit, DTDIR, + // the DPSM moves to the Wait_S, Wait_R state or Readwait if RW Start is set immediately at + // the beginning of the transfer. It is not necessary to clear the enable bit after the end of a data + // transfer but the SDIO_DCTRL must be updated to enable a new data transfer +// The meaning of the DTMODE bit changes according to the value of the SDIOEN bit: +// When DTEN=0 and DTMODE=1, the MultiMediaCard stream mode is enabled. +// When DTEN=1 and DTMODE=1, the peripheral enables an SDIO multi-byte transfer. + +// SDIO_STA register bits +#define SDIO_STA_CEATAEND (1<<23) // CE-ATA command completion signal received for CMD61 +#define SDIO_STA_SDIOIT (1<<22) // SDIO interrupt received +#define SDIO_STA_RXDAVL (1<<21) // Data available in receive FIFO +#define SDIO_STA_TXDAVL (1<<20) // Data available in transmit FIFO +#define SDIO_STA_RXFIFOE (1<<19) // Receive FIFO empty +#define SDIO_STA_TXFIFOE (1<<18) // Transmit FIFO empty (2 words) +#define SDIO_STA_RXFIFOF (1<<17) // Receive FIFO full (2 words before the FIFO is full.) +#define SDIO_STA_TXFIFOF (1<<16) // Transmit FIFO full +#define SDIO_STA_RXFIFOHF (1<<15) // Receive FIFO half full: there are at least 8 words in the FIFO +#define SDIO_STA_TXFIFOHE (1<<14) // Transmit FIFO half empty: at least 8 words can be written into the FIFO +#define SDIO_STA_RXACT (1<<13) // Data receive in progress +#define SDIO_STA_TXACT (1<<12) // Data transmit in progress +#define SDIO_STA_CMDACT (1<<11) // Command transfer in progress +#define SDIO_STA_DBCKEND (1<<10) // Data block sent/received (CRC check passed) +#define SDIO_STA_STBITERR (1<<9) // Start bit not detected on all data signals in wide bus mode +#define SDIO_STA_DATAEND (1<<8) // Data end (data counter SDIOCOUNT is zero) +#define SDIO_STA_CMDSENT (1<<7) // Command sent (no response required) +#define SDIO_STA_CMDREND (1<<6) // Command response received (CRC check passed) +#define SDIO_STA_RXOVERR (1<<5) // Received FIFO overrun error +#define SDIO_STA_TXUNDERR (1<<4) // Transmit FIFO underrun error +#define SDIO_STA_DTIMEOUT (1<<3) // Data timeout +#define SDIO_STA_CTIMEOUT (1<<2) // Command response timeout. The Command TimeOut period has a fixed value of 64 SDIO_CK clock periods. +#define SDIO_STA_DCRCFAIL (1<<1) // Data block sent/received (CRC check failed) +#define SDIO_STA_CCRCFAIL (1<<0) // Command response received (CRC check failed) + +#define SDIO_STA_CMD_ERROR_FLAGS (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL) +#define SDIO_STA_TRX_ERROR_FLAGS (SDIO_STA_STBITERR | SDIO_STA_RXOVERR | SDIO_STA_TXUNDERR | SDIO_STA_DTIMEOUT | SDIO_STA_DCRCFAIL) +#define SDIO_STA_TRX_ACT_FLAGS (SDIO_STA_RXACT|SDIO_STA_TXACT) + +// SDIO_ICR register bits (WO - write only) +#define SDIO_ICR_CEATAENDC (1<<23) // clear CEATAEND flag +#define SDIO_ICR_SDIOITC (1<<22) // clear SDIOIT flag +#define SDIO_ICR_DBCKENDC (1<<10) // clear DBCKENDC flag +#define SDIO_ICR_STBITERRC (1<<9) // clear STBITERRC flag +#define SDIO_ICR_DATAENDC (1<<8) // clear DATAENDC flag +#define SDIO_ICR_CMDSENTC (1<<7) // clear CMDSENTC flag +#define SDIO_ICR_CMDRENDC (1<<6) // clear CMDREND flag +#define SDIO_ICR_RXOVERRC (1<<5) // clear RXOVERR flag +#define SDIO_ICR_TXUNDERRC (1<<4) // clear TXUNDERR flag +#define SDIO_ICR_DTIMEOUTC (1<<3) // clear DTIMEOUT flag +#define SDIO_ICR_CTIMEOUTC (1<<2) // clear CTIMEOUT flag +#define SDIO_ICR_DCRCFAILC (1<<1) // clear DCRCFAIL flag +#define SDIO_ICR_CCRCFAILC (1<<0) // clear CCRCFAIL flag + +#define SDIO_ICR_CMD_FLAGS (SDIO_ICR_CEATAENDC | SDIO_ICR_SDIOITC | SDIO_ICR_CMDSENTC | SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC) +#define SDIO_ICR_DATA_FLAGS (SDIO_ICR_DBCKENDC | SDIO_ICR_STBITERRC | SDIO_ICR_DATAENDC | SDIO_ICR_RXOVERRC | SDIO_ICR_TXUNDERRC | SDIO_ICR_DTIMEOUTC | SDIO_ICR_DCRCFAILC) + +// SDIO_MASK register bits +// Determines which status flags generate an interrupt request by setting the corresponding bit to 1b. +#define SDIO_MASK_CEATAENDIE (1<<23) // enable CEATAEND interrupt +#define SDIO_MASK_SDIOITIE (1<<22) // enable SDIOIT interrupt +#define SDIO_MASK_RXDAVLIE (1<<21) // enable RXDAVL interrupt +#define SDIO_MASK_TXDAVLIE (1<<20) // enable TXDAVL interrupt +#define SDIO_MASK_RXFIFOEIE (1<<19) // enable RXFIFOE interrupt +#define SDIO_MASK_TXFIFOEIE (1<<18) // enable TXFIFOE interrupt +#define SDIO_MASK_RXFIFOFIE (1<<17) // enable RXFIFOF interrupt +#define SDIO_MASK_TXFIFOFIE (1<<16) // enable TXFIFOF interrupt +#define SDIO_MASK_RXFIFOHFIE (1<<15) // enable RXFIFOHF interrupt +#define SDIO_MASK_TXFIFOHEIE (1<<14) // enable TXFIFOHE interrupt +#define SDIO_MASK_RXACTIE (1<<13) // enable RXACT interrupt +#define SDIO_MASK_TXACTIE (1<<12) // enable TXACT interrupt +#define SDIO_MASK_CMDACTIE (1<<11) // enable CMDACT interrupt +#define SDIO_MASK_DBCKENDIE (1<<10) // enable DBCKENDC interrupt +#define SDIO_MASK_STBITERRIE (1<<9) // enable STBITERR interrupt +#define SDIO_MASK_DATAENDIE (1<<8) // enable DATAENDC interrupt +#define SDIO_MASK_CMDSENTIE (1<<7) // enable CMDSENTC interrupt +#define SDIO_MASK_CMDRENDIE (1<<6) // enable CMDREND interrupt +#define SDIO_MASK_RXOVERRIE (1<<5) // enable RXOVERR interrupt +#define SDIO_MASK_TXUNDERRIE (1<<4) // enable TXUNDERR interrupt +#define SDIO_MASK_DTIMEOUTIE (1<<3) // enable DTIMEOUT interrupt +#define SDIO_MASK_CTIMEOUTIE (1<<2) // enable CTIMEOUT interrupt +#define SDIO_MASK_DCRCFAILIE (1<<1) // enable DCRCFAIL interrupt +#define SDIO_MASK_CCRCFAILIE (1<<0) // enable CCRCFAIL interrupt + + +void sdio_enable(void); +void sdio_disable(void); +void sdio_begin(void); +uint8_t sdio_cmd_send(uint16_t cmd_index_resp_type, uint32_t arg); +void sdio_set_clock(uint32_t clk); +void sdio_set_dbus_width(uint16_t bus_w); +void sdio_set_dblock_size(uint8_t dbsize); +//void sdio_trx_enable(uint8_t dir); +inline void sdio_trx_enable(void) +{ + SDIO->DCTRL |= SDIO_DCTRL_DTEN; // enable data transfer +} + +inline uint32_t sdio_cmd_xfer_ongoing(void) { return (SDIO->STA&SDIO_STA_CMDACT); } +inline uint32_t sdio_cmd_complete(void) { return (SDIO->STA&SDIO_STA_CMDSENT); } + +inline void sdio_setup_transfer(uint32_t dtimer, uint32_t dlen, uint16_t flags) +{ + SDIO->ICR = SDIO_ICR_DATA_FLAGS; // clear data access relevant flags + SDIO->DTIMER = dtimer; + SDIO->DLEN = dlen; + SDIO->DCTRL = flags;// | SDIO_DCTRL_DTEN; // enable data transfer +} + +/* +#ifdef __cplusplus +} // extern "C" +#endif +*/ + +#endif /* (STM32_HIGH_DENSITY) || (STM32_XL_DENSITY) */ + +#endif diff --git a/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/systick.h b/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/systick.h index 551f800..51d0c56 100644 --- a/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/systick.h +++ b/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/systick.h @@ -108,6 +108,12 @@ static inline uint32 systick_check_underflow(void) { return SYSTICK_BASE->CSR & SYSTICK_CSR_COUNTFLAG; } +/** + * @brief prototype for systick_attach_callback + * + */ +extern void systick_attach_callback(void (*callback)(void)); + #ifdef __cplusplus } // extern "C" #endif diff --git a/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/timer.h b/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/timer.h index 59b3403..2c83e5e 100644 --- a/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/timer.h +++ b/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/timer.h @@ -785,6 +785,22 @@ static inline void timer_dma_disable_trg_req(timer_dev *dev) { *bb_perip(&(dev->regs).gen->DIER, TIMER_DIER_TDE_BIT) = 0; } +/** + * @brief Enable a timer's update DMA request + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL + */ +static inline void timer_dma_enable_upd_req(timer_dev *dev) { + *bb_perip(&(dev->regs).gen->DIER, TIMER_DIER_UDE_BIT) = 1; +} + +/** + * @brief Disable a timer's update DMA request + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL + */ +static inline void timer_dma_disable_upd_req(timer_dev *dev) { + *bb_perip(&(dev->regs).gen->DIER, TIMER_DIER_UDE_BIT) = 0; +} + /** * @brief Enable a timer channel's DMA request. * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL @@ -812,6 +828,7 @@ static inline void timer_dma_disable_req(timer_dev *dev, uint8 channel) { * @see timer_channel */ static inline void timer_enable_irq(timer_dev *dev, uint8 interrupt) { + *bb_perip(&(dev->regs).adv->SR, interrupt) = 0; // clear interrupt flag *bb_perip(&(dev->regs).adv->DIER, interrupt) = 1; } diff --git a/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/usart.h b/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/usart.h index fa7c7fb..245ddab 100644 --- a/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/usart.h +++ b/BootLoaders/Boards/stm32/system/libmaple/include/libmaple/usart.h @@ -439,8 +439,8 @@ static inline void usart_disable_all(void) { /** * @brief Transmit one character on a serial port. * - * This function blocks until the character has been successfully - * transmitted. + * This function blocks until the character has been queued + * for transmission. * * @param dev Serial port to send on. * @param byte Byte to transmit. diff --git a/BootLoaders/Boards/stm32/system/libmaple/include/util/atomic.h b/BootLoaders/Boards/stm32/system/libmaple/include/util/atomic.h new file mode 100644 index 0000000..db5e489 --- /dev/null +++ b/BootLoaders/Boards/stm32/system/libmaple/include/util/atomic.h @@ -0,0 +1,69 @@ +/* +* This is port of Dean Camera's ATOMIC_BLOCK macros for AVR to ARM Cortex M3 +* v1.0 +* Mark Pendrith, Nov 27, 2012. +* +* From Mark: +* >When I ported the macros I emailed Dean to ask what attribution would be +* >appropriate, and here is his response: +* > +* >>Mark, +* >>I think it's great that you've ported the macros; consider them +* >>public domain, to do with whatever you wish. I hope you find them useful. +* >> +* >>Cheers! +* >>- Dean +*/ + +#ifndef _CORTEX_M3_ATOMIC_H_ +#define _CORTEX_M3_ATOMIC_H_ + +static __inline__ uint32_t __get_primask(void) \ +{ uint32_t primask = 0; \ + __asm__ volatile ("MRS %[result], PRIMASK\n\t":[result]"=r"(primask)::); \ + return primask; } // returns 0 if interrupts enabled, 1 if disabled + +static __inline__ void __set_primask(uint32_t setval) \ +{ __asm__ volatile ("MSR PRIMASK, %[value]\n\t""dmb\n\t""dsb\n\t""isb\n\t"::[value]"r"(setval):); \ + __asm__ volatile ("" ::: "memory");} + +static __inline__ uint32_t __iSeiRetVal(void) \ +{ __asm__ volatile ("CPSIE i\n\t""dmb\n\t""dsb\n\t""isb\n\t"); \ + __asm__ volatile ("" ::: "memory"); return 1; } + +static __inline__ uint32_t __iCliRetVal(void) \ +{ __asm__ volatile ("CPSID i\n\t""dmb\n\t""dsb\n\t""isb\n\t"); \ + __asm__ volatile ("" ::: "memory"); return 1; } + +static __inline__ void __iSeiParam(const uint32_t *__s) \ +{ __asm__ volatile ("CPSIE i\n\t""dmb\n\t""dsb\n\t""isb\n\t"); \ + __asm__ volatile ("" ::: "memory"); (void)__s; } + +static __inline__ void __iCliParam(const uint32_t *__s) \ +{ __asm__ volatile ("CPSID i\n\t""dmb\n\t""dsb\n\t""isb\n\t"); \ + __asm__ volatile ("" ::: "memory"); (void)__s; } + +static __inline__ void __iRestore(const uint32_t *__s) \ +{ __set_primask(*__s); __asm__ volatile ("dmb\n\t""dsb\n\t""isb\n\t"); \ + __asm__ volatile ("" ::: "memory"); } + + +#define ATOMIC_BLOCK(type) \ +for ( type, __ToDo = __iCliRetVal(); __ToDo ; __ToDo = 0 ) + +#define ATOMIC_RESTORESTATE \ +uint32_t primask_save __attribute__((__cleanup__(__iRestore))) = __get_primask() + +#define ATOMIC_FORCEON \ +uint32_t primask_save __attribute__((__cleanup__(__iSeiParam))) = 0 + +#define NONATOMIC_BLOCK(type) \ +for ( type, __ToDo = __iSeiRetVal(); __ToDo ; __ToDo = 0 ) + +#define NONATOMIC_RESTORESTATE \ +uint32_t primask_save __attribute__((__cleanup__(__iRestore))) = __get_primask() + +#define NONATOMIC_FORCEOFF \ +uint32_t primask_save __attribute__((__cleanup__(__iCliParam))) = 0 + +#endif diff --git a/BootLoaders/Boards/stm32/system/libmaple/stm32f1/include/series/dma.h b/BootLoaders/Boards/stm32/system/libmaple/stm32f1/include/series/dma.h index bedb602..56e559b 100644 --- a/BootLoaders/Boards/stm32/system/libmaple/stm32f1/include/series/dma.h +++ b/BootLoaders/Boards/stm32/system/libmaple/stm32f1/include/series/dma.h @@ -152,7 +152,7 @@ typedef struct dma_tube_reg_map { #define DMA_ISR_TEIF (1 << DMA_ISR_TEIF_BIT) #define DMA_ISR_HTIF (1 << DMA_ISR_HTIF_BIT) -#define DMA_ISR_TCID (1 << DMA_ISR_TCIF_BIT) +#define DMA_ISR_TCIF (1 << DMA_ISR_TCIF_BIT) #define DMA_ISR_GIF (1 << DMA_ISR_GIF_BIT) #define DMA_ISR_TEIF7_BIT 27 @@ -559,7 +559,6 @@ typedef enum dma_mode_flags { * * (It's not possible to fully configure a DMA stream on F2 with just * this information, so this interface is too tied to the F1.) */ -__deprecated void dma_setup_transfer(dma_dev *dev, dma_channel channel, __io void *peripheral_address, diff --git a/BootLoaders/Boards/stm32/system/libmaple/stm32f1/include/series/i2c.h b/BootLoaders/Boards/stm32/system/libmaple/stm32f1/include/series/i2c.h index f407955..3565503 100644 --- a/BootLoaders/Boards/stm32/system/libmaple/stm32f1/include/series/i2c.h +++ b/BootLoaders/Boards/stm32/system/libmaple/stm32f1/include/series/i2c.h @@ -59,7 +59,7 @@ extern i2c_dev* const I2C2; * For internal use */ -static inline uint32 _i2c_bus_clk(i2c_dev *dev) { +static inline uint32 _i2c_bus_clk(i2c_dev *dev __attribute__((unused))) { /* Both I2C peripherals are on APB1 */ return STM32_PCLK1 / (1000 * 1000); } diff --git a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/adc.h b/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/adc.h deleted file mode 100644 index 175fe11..0000000 --- a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/adc.h +++ /dev/null @@ -1,335 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2012 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/stm32f2/include/series/adc.h - * @author Marti Bolivar , - * @brief STM32F2 ADC support. - */ - -#ifndef _LIBMAPLE_STM32F2_ADC_H_ -#define _LIBMAPLE_STM32F2_ADC_H_ - -#include - -/* - * Devices - */ - -extern const struct adc_dev *ADC1; -extern const struct adc_dev *ADC2; -extern const struct adc_dev *ADC3; - -/* - * Common register map - */ - -/** ADC common register map type */ -typedef struct adc_common_reg_map { - __io uint32 CSR; /**< Common status register */ - __io uint32 CCR; /**< Common control register */ - __io uint32 CDR; /**< - * @brief Common regular data register - * for dual and triple modes */ -} adc_common_reg_map; - -/* - * Register map base pointers - */ - -/** ADC1 register map base pointer. */ -#define ADC1_BASE ((struct adc_reg_map*)0x40012000) -/** ADC2 register map base pointer. */ -#define ADC2_BASE ((struct adc_reg_map*)0x40012100) -/** ADC3 register map base pointer. */ -#define ADC3_BASE ((struct adc_reg_map*)0x40012200) -/** ADC common register map base pointer. */ -#define ADC_COMMON_BASE ((struct adc_common_reg_map*)0x40012300) - -/* - * Register bit definitions - */ - -/* Status register */ - -/** Overrun bit. */ -#define ADC_SR_OVR_BIT 5 -/** Overrun. */ -#define ADC_SR_OVR (1U << ADC_SR_OVR_BIT) - -/* Control register 1 */ - -/** Overrun interrupt enable bit. */ -#define ADC_CR1_OVRIE_BIT 26 - -/** Overrun interrupt error enable. */ -#define ADC_CR1_OVRIE (1U << ADC_CR1_OVRIE_BIT) -/** Conversion resolution. */ -#define ADC_CR1_RES (0x3U << 24) -/** Conversion resolution: 12 bit (at least 15 ADCCLK cycles). */ -#define ADC_CR1_RES_12BIT (0x0U << 24) -/** Conversion resolution: 10 bit (at least 13 ADCCLK cycles). */ -#define ADC_CR1_RES_10BIT (0x1U << 24) -/** Conversion resolution: 8 bit (at least 11 ADCCLK cycles). */ -#define ADC_CR1_RES_8BIT (0x2U << 24) -/** Conversion resolution: 6 bit (at least 9 ADCCLK cycles). */ -#define ADC_CR1_RES_6BIT (0x3U << 24) - -/* Control register 2 */ - -#define ADC_CR2_SWSTART_BIT 30 -#define ADC_CR2_JSWSTART_BIT 22 -#define ADC_CR2_ALIGN_BIT 11 -#define ADC_CR2_EOCS_BIT 10 -#define ADC_CR2_DDS_BIT 9 -#define ADC_CR2_DMA_BIT 8 -#define ADC_CR2_CONT_BIT 1 -#define ADC_CR2_ADON_BIT 0 - -#define ADC_CR2_SWSTART (1U << ADC_CR2_SWSTART_BIT) -#define ADC_CR2_EXTEN (0x3 << 28) -#define ADC_CR2_EXTEN_DISABLED (0x0 << 28) -#define ADC_CR2_EXTEN_RISE (0x1 << 28) -#define ADC_CR2_EXTEN_FALL (0x2 << 28) -#define ADC_CR2_EXTEN_RISE_FALL (0x3 << 28) -#define ADC_CR2_EXTSEL (0xF << 24) -#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 24) -#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 24) -#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 24) -#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 24) -#define ADC_CR2_EXTSEL_TIM2_CC3 (0x4 << 24) -#define ADC_CR2_EXTSEL_TIM2_CC4 (0x5 << 24) -#define ADC_CR2_EXTSEL_TIM1_TRGO (0x6 << 24) -#define ADC_CR2_EXTSEL_TIM3_CC1 (0x7 << 24) -#define ADC_CR2_EXTSEL_TIM3_TRGO (0x8 << 24) -#define ADC_CR2_EXTSEL_TIM4_CC4 (0x9 << 24) -#define ADC_CR2_EXTSEL_TIM5_CC1 (0xA << 24) -#define ADC_CR2_EXTSEL_TIM5_CC2 (0xB << 24) -#define ADC_CR2_EXTSEL_TIM5_CC3 (0xC << 24) -#define ADC_CR2_EXTSEL_TIM8_CC1 (0xD << 24) -#define ADC_CR2_EXTSEL_TIM8_TRGO (0xE << 24) -#define ADC_CR2_EXTSEL_TIM1_EXTI11 (0xF << 24) -#define ADC_CR2_JSWSTART (1U << ADC_CR2_JSWSTART_BIT) -#define ADC_CR2_JEXTEN (0x3 << 20) -#define ADC_CR2_JEXTEN_DISABLED (0x0 << 20) -#define ADC_CR2_JEXTEN_RISE (0x1 << 20) -#define ADC_CR2_JEXTEN_FALL (0x2 << 20) -#define ADC_CR2_JEXTEN_RISE_FALL (0x3 << 20) -#define ADC_CR2_JEXTSEL (0xF << 16) -#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x0 << 16) -#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x1 << 16) -#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x2 << 16) -#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x3 << 16) -#define ADC_CR2_JEXTSEL_TIM3_CC2 (0x4 << 16) -#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x5 << 16) -#define ADC_CR2_JEXTSEL_TIM4_CC1 (0x6 << 16) -#define ADC_CR2_JEXTSEL_TIM4_CC2 (0x7 << 16) -#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x8 << 16) -#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x9 << 16) -#define ADC_CR2_JEXTSEL_TIM5_CC4 (0xA << 16) -#define ADC_CR2_JEXTSEL_TIM5_TRGO (0xB << 16) -#define ADC_CR2_JEXTSEL_TIM8_CC2 (0xC << 16) -#define ADC_CR2_JEXTSEL_TIM8_CC3 (0xD << 16) -#define ADC_CR2_JEXTSEL_TIM8_CC4 (0xE << 16) -#define ADC_CR2_JEXTSEL_TIM1_EXTI15 (0xF << 16) -#define ADC_CR2_ALIGN (1U << ADC_CR2_ALIGN_BIT) -#define ADC_CR2_ALIGN_RIGHT (0U << ADC_CR2_ALIGN_BIT) -#define ADC_CR2_ALIGN_LEFT (1U << ADC_CR2_ALIGN_BIT) -#define ADC_CR2_EOCS (1U << ADC_CR2_EOCS_BIT) -#define ADC_CR2_EOCS_SEQUENCE (0U << ADC_CR2_EOCS_BIT) -#define ADC_CR2_EOCS_CONVERSION (1U << ADC_CR2_EOCS_BIT) -#define ADC_CR2_DDS (1U << ADC_CR2_DDS_BIT) -#define ADC_CR2_DMA (1U << ADC_CR2_DMA_BIT) -#define ADC_CR2_CONT (1U << ADC_CR2_CONT_BIT) -#define ADC_CR2_ADON (1U << ADC_CR2_ADON_BIT) - -/* Common status register */ - -#define ADC_CSR_OVR3_BIT 21 -#define ADC_CSR_STRT3_BIT 20 -#define ADC_CSR_JSTRT3_BIT 19 -#define ADC_CSR_JEOC3_BIT 18 -#define ADC_CSR_EOC3_BIT 17 -#define ADC_CSR_AWD3_BIT 16 -#define ADC_CSR_OVR2_BIT 13 -#define ADC_CSR_STRT2_BIT 12 -#define ADC_CSR_JSTRT2_BIT 11 -#define ADC_CSR_JEOC2_BIT 10 -#define ADC_CSR_EOC2_BIT 9 -#define ADC_CSR_AWD2_BIT 8 -#define ADC_CSR_OVR1_BIT 5 -#define ADC_CSR_STRT1_BIT 4 -#define ADC_CSR_JSTRT1_BIT 3 -#define ADC_CSR_JEOC1_BIT 2 -#define ADC_CSR_EOC1_BIT 1 -#define ADC_CSR_AWD1_BIT 0 - -#define ADC_CSR_OVR3 (1U << ADC_CSR_OVR3_BIT) -#define ADC_CSR_STRT3 (1U << ADC_CSR_STRT3_BIT) -#define ADC_CSR_JSTRT3 (1U << ADC_CSR_JSTRT3_BIT) -#define ADC_CSR_JEOC3 (1U << ADC_CSR_JEOC3_BIT) -#define ADC_CSR_EOC3 (1U << ADC_CSR_EOC3_BIT) -#define ADC_CSR_AWD3 (1U << ADC_CSR_AWD3_BIT) -#define ADC_CSR_OVR2 (1U << ADC_CSR_OVR2_BIT) -#define ADC_CSR_STRT2 (1U << ADC_CSR_STRT2_BIT) -#define ADC_CSR_JSTRT2 (1U << ADC_CSR_JSTRT2_BIT) -#define ADC_CSR_JEOC2 (1U << ADC_CSR_JEOC2_BIT) -#define ADC_CSR_EOC2 (1U << ADC_CSR_EOC2_BIT) -#define ADC_CSR_AWD2 (1U << ADC_CSR_AWD2_BIT) -#define ADC_CSR_OVR1 (1U << ADC_CSR_OVR1_BIT) -#define ADC_CSR_STRT1 (1U << ADC_CSR_STRT1_BIT) -#define ADC_CSR_JSTRT1 (1U << ADC_CSR_JSTRT1_BIT) -#define ADC_CSR_JEOC1 (1U << ADC_CSR_JEOC1_BIT) -#define ADC_CSR_EOC1 (1U << ADC_CSR_EOC1_BIT) -#define ADC_CSR_AWD1 (1U << ADC_CSR_AWD1_BIT) - -/* Common control register */ - -#define ADC_CCR_TSVREFE_BIT 23 -#define ADC_CCR_VBATE_BIT 22 -#define ADC_CCR_DDS_BIT 13 - -#define ADC_CCR_TSVREFE (1U << ADC_CCR_TSVREFE_BIT) -#define ADC_CCR_VBATE (1U << ADC_CCR_VBATE_BIT) -#define ADC_CCR_ADCPRE (0x3 << 16) -#define ADC_CCR_ADCPRE_PCLK2_DIV_2 (0x0 << 16) -#define ADC_CCR_ADCPRE_PCLK2_DIV_4 (0x1 << 16) -#define ADC_CCR_ADCPRE_PCLK2_DIV_6 (0x2 << 16) -#define ADC_CCR_ADCPRE_PCLK2_DIV_8 (0x3 << 16) -#define ADC_CCR_DMA (0x3 << 14) -#define ADC_CCR_DMA_DIS (0x0 << 14) -#define ADC_CCR_DMA_MODE_1 (0x1 << 14) -#define ADC_CCR_DMA_MODE_2 (0x2 << 14) -#define ADC_CCR_DMA_MODE_3 (0x3 << 14) -#define ADC_CCR_DDS (1U << ADC_CCR_DDS_BIT) -#define ADC_CCR_DELAY (0xF << 8) -#define ADC_CCR_DELAY_5 (0x0 << 8) -#define ADC_CCR_DELAY_6 (0x1 << 8) -#define ADC_CCR_DELAY_7 (0x2 << 8) -#define ADC_CCR_DELAY_8 (0x3 << 8) -#define ADC_CCR_DELAY_9 (0x4 << 8) -#define ADC_CCR_DELAY_10 (0x5 << 8) -#define ADC_CCR_DELAY_11 (0x6 << 8) -#define ADC_CCR_DELAY_12 (0x7 << 8) -#define ADC_CCR_DELAY_13 (0x8 << 8) -#define ADC_CCR_DELAY_14 (0x9 << 8) -#define ADC_CCR_DELAY_15 (0xA << 8) -#define ADC_CCR_DELAY_16 (0xB << 8) -#define ADC_CCR_DELAY_17 (0xC << 8) -#define ADC_CCR_DELAY_18 (0xD << 8) -#define ADC_CCR_DELAY_19 (0xE << 8) -#define ADC_CCR_DELAY_20 (0xF << 8) -/** Multi ADC mode selection. */ -#define ADC_CCR_MULTI 0x1F -/** All ADCs independent. */ -#define ADC_CCR_MULTI_INDEPENDENT 0x0 -/** Dual mode: combined regular simultaneous/injected simultaneous. */ -#define ADC_CCR_MULTI_DUAL_REG_SIM_INJ_SIM 0x1 -/** Dual mode: combined regular simultaneous/alternate trigger. */ -#define ADC_CCR_MULTI_DUAL_REG_SIM_ALT_TRIG 0x2 -/** Dual mode: injected simultaneous mode only. */ -#define ADC_CCR_MULTI_DUAL_INJ_SIM 0x5 -/** Dual mode: regular simultaneous mode only. */ -#define ADC_CCR_MULTI_DUAL_REG_SIM 0x6 -/** Dual mode: interleaved mode only. */ -#define ADC_CCR_MULTI_DUAL_INTER 0x7 -/** Dual mode: alternate trigger mode only. */ -#define ADC_CCR_MULTI_DUAL_ALT_TRIG 0x9 -/** Triple mode: combined regular simultaneous/injected simultaneous. */ -#define ADC_CCR_MULTI_TRIPLE_REG_SIM_INJ_SIM 0x10 -/** Triple mode: combined regular simultaneous/alternate trigger. */ -#define ADC_CCR_MULTI_TRIPLE_REG_SIM_ALT_TRIG 0x11 -/** Triple mode: injected simultaneous mode only. */ -#define ADC_CCR_MULTI_TRIPLE_INJ_SIM 0x12 -/** Triple mode: regular simultaneous mode only. */ -#define ADC_CCR_MULTI_TRIPLE_REG_SIM 0x15 -/** Triple mode: interleaved mode only. */ -#define ADC_CCR_MULTI_TRIPLE_INTER 0x17 -/** Triple mode: alternate trigger mode only. */ -#define ADC_CCR_MULTI_TRIPLE_ALT_TRIG 0x19 - -/* Common regular data register for dual and triple modes */ - -#define ADC_CDR_DATA2 0xFFFF0000 -#define ADC_CDR_DATA1 0xFFFF - -/* - * Other types - */ - -/** - * @brief STM32F2 external event selectors for regular group - * conversion. - * @see adc_set_extsel() - */ -typedef enum adc_extsel_event { - ADC_EXT_EV_TIM1_CC1 = ADC_CR2_EXTSEL_TIM1_CC1, - ADC_EXT_EV_TIM1_CC2 = ADC_CR2_EXTSEL_TIM1_CC2, - ADC_EXT_EV_TIM1_CC3 = ADC_CR2_EXTSEL_TIM1_CC3, - ADC_EXT_EV_TIM2_CC2 = ADC_CR2_EXTSEL_TIM2_CC2, - ADC_EXT_EV_TIM2_CC3 = ADC_CR2_EXTSEL_TIM2_CC3, - ADC_EXT_EV_TIM2_CC4 = ADC_CR2_EXTSEL_TIM2_CC4, - ADC_EXT_EV_TIM1_TRGO = ADC_CR2_EXTSEL_TIM1_TRGO, - ADC_EXT_EV_TIM3_CC1 = ADC_CR2_EXTSEL_TIM3_CC1, - ADC_EXT_EV_TIM3_TRGO = ADC_CR2_EXTSEL_TIM3_TRGO, - ADC_EXT_EV_TIM4_CC4 = ADC_CR2_EXTSEL_TIM4_CC4, - ADC_EXT_EV_TIM5_CC1 = ADC_CR2_EXTSEL_TIM5_CC1, - ADC_EXT_EV_TIM5_CC2 = ADC_CR2_EXTSEL_TIM5_CC2, - ADC_EXT_EV_TIM5_CC3 = ADC_CR2_EXTSEL_TIM5_CC3, - ADC_EXT_EV_TIM8_CC1 = ADC_CR2_EXTSEL_TIM8_CC1, - ADC_EXT_EV_TIM8_TRGO = ADC_CR2_EXTSEL_TIM8_TRGO, - ADC_EXT_EV_TIM1_EXTI11 = ADC_CR2_EXTSEL_TIM1_EXTI11, -} adc_extsel_event; - -/** - * @brief STM32F2 sample times, in ADC clock cycles. - */ -typedef enum adc_smp_rate { - ADC_SMPR_3, /**< 3 ADC cycles */ - ADC_SMPR_15, /**< 15 ADC cycles */ - ADC_SMPR_28, /**< 28 ADC cycles */ - ADC_SMPR_56, /**< 56 ADC cycles */ - ADC_SMPR_84, /**< 84 ADC cycles */ - ADC_SMPR_112, /**< 112 ADC cycles */ - ADC_SMPR_144, /**< 144 ADC cycles */ - ADC_SMPR_480, /**< 480 ADC cycles */ -} adc_smp_rate; - -/** - * @brief STM32F2 ADC prescalers, as divisors of PCLK2. - */ -typedef enum adc_prescaler { - /** PCLK2 divided by 2 */ - ADC_PRE_PCLK2_DIV_2 = ADC_CCR_ADCPRE_PCLK2_DIV_2, - /** PCLK2 divided by 4 */ - ADC_PRE_PCLK2_DIV_4 = ADC_CCR_ADCPRE_PCLK2_DIV_4, - /** PCLK2 divided by 6 */ - ADC_PRE_PCLK2_DIV_6 = ADC_CCR_ADCPRE_PCLK2_DIV_6, - /** PCLK2 divided by 8 */ - ADC_PRE_PCLK2_DIV_8 = ADC_CCR_ADCPRE_PCLK2_DIV_8, -} adc_prescaler; - -#endif diff --git a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/dac.h b/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/dac.h deleted file mode 100644 index 0a578ca..0000000 --- a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/dac.h +++ /dev/null @@ -1,94 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2012 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/stm32f2/include/series/dac.h - * @brief STM32F2 DAC support - */ - -#ifndef _LIBMAPLE_STM32F2_DAC_H_ -#define _LIBMAPLE_STM32F2_DAC_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -#include - -/* - * Register map type - */ - -/** STM32F2 DAC register map type. */ -typedef struct dac_reg_map { - __io uint32 CR; /**< Control register */ - __io uint32 SWTRIGR; /**< Software trigger register */ - __io uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data - holding register */ - __io uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data - holding register */ - __io uint32 DHR8R1; /**< Channel 1 8-bit left-aligned data - holding register */ - __io uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data - holding register */ - __io uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data - holding register */ - __io uint32 DHR8R2; /**< Channel 2 8-bit left-aligned data - holding register */ - __io uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data - holding register */ - __io uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data - holding register */ - __io uint32 DHR8RD; /**< Dual DAC 8-bit right-aligned data holding - register */ - __io uint32 DOR1; /**< Channel 1 data output register */ - __io uint32 DOR2; /**< Channel 2 data output register */ - __io uint32 SR; /**< Status register */ -} dac_reg_map; - -/* - * Register bit definitions - */ - -/* Control register */ - -#define DAC_CR_DMAUDRIE1 (1U << 13) /* Channel 1 DMA underrun - * interrupt enable */ -#define DAC_CR_DMAUDRIE2 (1U << 29) /* Channel 2 DMA underrun - * interrupt enable */ - -/* Status register */ - -#define DAC_SR_DMAUDR1 (1U << 13) /* Channel 1 DMA underrun - * occurred */ -#define DAC_SR_DMAUDR2 (1U << 29) /* Channel 2 DMA underrun - * ocurred */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/dma.h b/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/dma.h deleted file mode 100644 index 56725e5..0000000 --- a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/dma.h +++ /dev/null @@ -1,810 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2012 LeafLabs, LLC - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/stm32f2/include/series/dma.h - * @author Marti Bolivar - * @brief STM32F2 DMA series header - */ - -#ifndef _LIBMAPLE_STM32F2_DMA_H_ -#define _LIBMAPLE_STM32F2_DMA_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -#include -#include - -/* - * Register map and base pointers - */ - -/** - * @brief STM32F2 DMA register map type. - */ -typedef struct dma_reg_map { - /* Isn't it nice how on F1, it's CCR1, but on F2, it's S1CR? */ - - /* Global DMA registers */ - __io uint32 LISR; /**< Low interrupt status register */ - __io uint32 HISR; /**< High interrupt status register */ - __io uint32 LIFCR; /**< Low interrupt flag clear register */ - __io uint32 HIFCR; /**< High interrupt flag clear register */ - /* Stream 0 registers */ - __io uint32 S0CR; /**< Stream 0 control register */ - __io uint32 S0NDTR; /**< Stream 0 number of data register */ - __io uint32 S0PAR; /**< Stream 0 peripheral address register */ - __io uint32 S0M0AR; /**< Stream 0 memory 0 address register */ - __io uint32 S0M1AR; /**< Stream 0 memory 1 address register */ - __io uint32 S0FCR; /**< Stream 0 FIFO control register */ - /* Stream 1 registers */ - __io uint32 S1CR; /**< Stream 1 control register */ - __io uint32 S1NDTR; /**< Stream 1 number of data register */ - __io uint32 S1PAR; /**< Stream 1 peripheral address register */ - __io uint32 S1M0AR; /**< Stream 1 memory 0 address register */ - __io uint32 S1M1AR; /**< Stream 1 memory 1 address register */ - __io uint32 S1FCR; /**< Stream 1 FIFO control register */ - /* Stream 2 registers */ - __io uint32 S2CR; /**< Stream 2 control register */ - __io uint32 S2NDTR; /**< Stream 2 number of data register */ - __io uint32 S2PAR; /**< Stream 2 peripheral address register */ - __io uint32 S2M0AR; /**< Stream 2 memory 0 address register */ - __io uint32 S2M1AR; /**< Stream 2 memory 1 address register */ - __io uint32 S2FCR; /**< Stream 2 FIFO control register */ - /* Stream 3 registers */ - __io uint32 S3CR; /**< Stream 3 control register */ - __io uint32 S3NDTR; /**< Stream 3 number of data register */ - __io uint32 S3PAR; /**< Stream 3 peripheral address register */ - __io uint32 S3M0AR; /**< Stream 3 memory 0 address register */ - __io uint32 S3M1AR; /**< Stream 3 memory 1 address register */ - __io uint32 S3FCR; /**< Stream 3 FIFO control register */ - /* Stream 4 registers */ - __io uint32 S4CR; /**< Stream 4 control register */ - __io uint32 S4NDTR; /**< Stream 4 number of data register */ - __io uint32 S4PAR; /**< Stream 4 peripheral address register */ - __io uint32 S4M0AR; /**< Stream 4 memory 0 address register */ - __io uint32 S4M1AR; /**< Stream 4 memory 1 address register */ - __io uint32 S4FCR; /**< Stream 4 FIFO control register */ - /* Stream 5 registers */ - __io uint32 S5CR; /**< Stream 5 control register */ - __io uint32 S5NDTR; /**< Stream 5 number of data register */ - __io uint32 S5PAR; /**< Stream 5 peripheral address register */ - __io uint32 S5M0AR; /**< Stream 5 memory 0 address register */ - __io uint32 S5M1AR; /**< Stream 5 memory 1 address register */ - __io uint32 S5FCR; /**< Stream 5 FIFO control register */ - /* Stream 6 registers */ - __io uint32 S6CR; /**< Stream 6 control register */ - __io uint32 S6NDTR; /**< Stream 6 number of data register */ - __io uint32 S6PAR; /**< Stream 6 peripheral address register */ - __io uint32 S6M0AR; /**< Stream 6 memory 0 address register */ - __io uint32 S6M1AR; /**< Stream 6 memory 1 address register */ - __io uint32 S6FCR; /**< Stream 6 FIFO control register */ - /* Stream 7 registers */ - __io uint32 S7CR; /**< Stream 7 control register */ - __io uint32 S7NDTR; /**< Stream 7 number of data register */ - __io uint32 S7PAR; /**< Stream 7 peripheral address register */ - __io uint32 S7M0AR; /**< Stream 7 memory 0 address register */ - __io uint32 S7M1AR; /**< Stream 7 memory 1 address register */ - __io uint32 S7FCR; /**< Stream 7 FIFO control register */ -} dma_reg_map; - -/** DMA controller 1 register map base pointer */ -#define DMA1_BASE ((struct dma_reg_map*)0x40026000) -/** DMA controller 2 register map base pointer */ -#define DMA2_BASE ((struct dma_reg_map*)0x40026400) - -/** - * @brief STM32F2 DMA stream (i.e. tube) register map type. - * Provides access to an individual stream's registers. - * @see dma_tube_regs() - */ -typedef struct dma_tube_reg_map { - __io uint32 SCR; /**< Stream configuration register */ - __io uint32 SNDTR; /**< Stream number of data register */ - __io uint32 SPAR; /**< Stream peripheral address register */ - __io uint32 SM0AR; /**< Stream memory 0 address register */ - __io uint32 SM1AR; /**< Stream memory 1 address register */ - __io uint32 SFCR; /**< Stream FIFO control register */ -} dma_tube_reg_map; - -/** DMA1 stream 0 register map base pointer */ -#define DMA1S0_BASE ((struct dma_tube_reg_map*)0x40026010) -/** DMA1 stream 1 register map base pointer */ -#define DMA1S1_BASE ((struct dma_tube_reg_map*)0x40026028) -/** DMA1 stream 2 register map base pointer */ -#define DMA1S2_BASE ((struct dma_tube_reg_map*)0x40026040) -/** DMA1 stream 3 register map base pointer */ -#define DMA1S3_BASE ((struct dma_tube_reg_map*)0x40026058) -/** DMA1 stream 4 register map base pointer */ -#define DMA1S4_BASE ((struct dma_tube_reg_map*)0x40026070) -/** DMA1 stream 5 register map base pointer */ -#define DMA1S5_BASE ((struct dma_tube_reg_map*)0x40026088) -/** DMA1 stream 6 register map base pointer */ -#define DMA1S6_BASE ((struct dma_tube_reg_map*)0x400260A0) -/** DMA1 stream 7 register map base pointer */ -#define DMA1S7_BASE ((struct dma_tube_reg_map*)0x400260B8) - -/** DMA2 stream 0 register map base pointer */ -#define DMA2S0_BASE ((struct dma_tube_reg_map*)0x40026410) -/** DMA2 stream 1 register map base pointer */ -#define DMA2S1_BASE ((struct dma_tube_reg_map*)0x40026028) -/** DMA2 stream 2 register map base pointer */ -#define DMA2S2_BASE ((struct dma_tube_reg_map*)0x40026040) -/** DMA2 stream 3 register map base pointer */ -#define DMA2S3_BASE ((struct dma_tube_reg_map*)0x40026058) -/** DMA2 stream 4 register map base pointer */ -#define DMA2S4_BASE ((struct dma_tube_reg_map*)0x40026070) -/** DMA2 stream 5 register map base pointer */ -#define DMA2S5_BASE ((struct dma_tube_reg_map*)0x40026088) -/** DMA2 stream 6 register map base pointer */ -#define DMA2S6_BASE ((struct dma_tube_reg_map*)0x400260A0) -/** DMA2 stream 7 register map base pointer */ -#define DMA2S7_BASE ((struct dma_tube_reg_map*)0x400260B8) - -/* - * Register bit definitions - */ - -/* Low interrupt status register */ - -#define DMA_LISR_TCIF3_BIT 27 -#define DMA_LISR_HTIF3_BIT 26 -#define DMA_LISR_TEIF3_BIT 25 -#define DMA_LISR_DMEIF3_BIT 24 -#define DMA_LISR_FEIF3_BIT 22 -#define DMA_LISR_TCIF2_BIT 21 -#define DMA_LISR_HTIF2_BIT 20 -#define DMA_LISR_TEIF2_BIT 19 -#define DMA_LISR_DMEIF2_BIT 18 -#define DMA_LISR_FEIF2_BIT 16 -#define DMA_LISR_TCIF1_BIT 11 -#define DMA_LISR_HTIF1_BIT 10 -#define DMA_LISR_TEIF1_BIT 9 -#define DMA_LISR_DMEIF1_BIT 8 -#define DMA_LISR_FEIF1_BIT 6 -#define DMA_LISR_TCIF0_BIT 5 -#define DMA_LISR_HTIF0_BIT 4 -#define DMA_LISR_TEIF0_BIT 3 -#define DMA_LISR_DMEIF0_BIT 2 -#define DMA_LISR_FEIF0_BIT 0 - -#define DMA_LISR_TCIF3 (1U << DMA_LISR_TCIF3_BIT) -#define DMA_LISR_HTIF3 (1U << DMA_LISR_HTIF3_BIT) -#define DMA_LISR_TEIF3 (1U << DMA_LISR_TEIF3_BIT) -#define DMA_LISR_DMEIF3 (1U << DMA_LISR_DMEIF3_BIT) -#define DMA_LISR_FEIF3 (1U << DMA_LISR_FEIF3_BIT) -#define DMA_LISR_TCIF2 (1U << DMA_LISR_TCIF2_BIT) -#define DMA_LISR_HTIF2 (1U << DMA_LISR_HTIF2_BIT) -#define DMA_LISR_TEIF2 (1U << DMA_LISR_TEIF2_BIT) -#define DMA_LISR_DMEIF2 (1U << DMA_LISR_DMEIF2_BIT) -#define DMA_LISR_FEIF2 (1U << DMA_LISR_FEIF2_BIT) -#define DMA_LISR_TCIF1 (1U << DMA_LISR_TCIF1_BIT) -#define DMA_LISR_HTIF1 (1U << DMA_LISR_HTIF1_BIT) -#define DMA_LISR_TEIF1 (1U << DMA_LISR_TEIF1_BIT) -#define DMA_LISR_DMEIF1 (1U << DMA_LISR_DMEIF1_BIT) -#define DMA_LISR_FEIF1 (1U << DMA_LISR_FEIF1_BIT) -#define DMA_LISR_TCIF0 (1U << DMA_LISR_TCIF0_BIT) -#define DMA_LISR_HTIF0 (1U << DMA_LISR_HTIF0_BIT) -#define DMA_LISR_TEIF0 (1U << DMA_LISR_TEIF0_BIT) -#define DMA_LISR_DMEIF0 (1U << DMA_LISR_DMEIF0_BIT) -#define DMA_LISR_FEIF0 (1U << DMA_LISR_FEIF0_BIT) - -/* High interrupt status register */ - -#define DMA_HISR_TCIF7_BIT 27 -#define DMA_HISR_HTIF7_BIT 26 -#define DMA_HISR_TEIF7_BIT 25 -#define DMA_HISR_DMEIF7_BIT 24 -#define DMA_HISR_FEIF7_BIT 22 -#define DMA_HISR_TCIF6_BIT 21 -#define DMA_HISR_HTIF6_BIT 20 -#define DMA_HISR_TEIF6_BIT 19 -#define DMA_HISR_DMEIF6_BIT 18 -#define DMA_HISR_FEIF6_BIT 16 -#define DMA_HISR_TCIF5_BIT 11 -#define DMA_HISR_HTIF5_BIT 10 -#define DMA_HISR_TEIF5_BIT 9 -#define DMA_HISR_DMEIF5_BIT 8 -#define DMA_HISR_FEIF5_BIT 6 -#define DMA_HISR_TCIF4_BIT 5 -#define DMA_HISR_HTIF4_BIT 4 -#define DMA_HISR_TEIF4_BIT 3 -#define DMA_HISR_DMEIF4_BIT 2 -#define DMA_HISR_FEIF4_BIT 0 - -#define DMA_HISR_TCIF7 (1U << DMA_HISR_TCIF7_BIT) -#define DMA_HISR_HTIF7 (1U << DMA_HISR_HTIF7_BIT) -#define DMA_HISR_TEIF7 (1U << DMA_HISR_TEIF7_BIT) -#define DMA_HISR_DMEIF7 (1U << DMA_HISR_DMEIF7_BIT) -#define DMA_HISR_FEIF7 (1U << DMA_HISR_FEIF7_BIT) -#define DMA_HISR_TCIF6 (1U << DMA_HISR_TCIF6_BIT) -#define DMA_HISR_HTIF6 (1U << DMA_HISR_HTIF6_BIT) -#define DMA_HISR_TEIF6 (1U << DMA_HISR_TEIF6_BIT) -#define DMA_HISR_DMEIF6 (1U << DMA_HISR_DMEIF6_BIT) -#define DMA_HISR_FEIF6 (1U << DMA_HISR_FEIF6_BIT) -#define DMA_HISR_TCIF5 (1U << DMA_HISR_TCIF5_BIT) -#define DMA_HISR_HTIF5 (1U << DMA_HISR_HTIF5_BIT) -#define DMA_HISR_TEIF5 (1U << DMA_HISR_TEIF5_BIT) -#define DMA_HISR_DMEIF5 (1U << DMA_HISR_DMEIF5_BIT) -#define DMA_HISR_FEIF5 (1U << DMA_HISR_FEIF5_BIT) -#define DMA_HISR_TCIF4 (1U << DMA_HISR_TCIF4_BIT) -#define DMA_HISR_HTIF4 (1U << DMA_HISR_HTIF4_BIT) -#define DMA_HISR_TEIF4 (1U << DMA_HISR_TEIF4_BIT) -#define DMA_HISR_DMEIF4 (1U << DMA_HISR_DMEIF4_BIT) -#define DMA_HISR_FEIF4 (1U << DMA_HISR_FEIF4_BIT) - -/* Low interrupt flag clear register */ - -#define DMA_LIFCR_CTCIF3_BIT 27 -#define DMA_LIFCR_CHTIF3_BIT 26 -#define DMA_LIFCR_CTEIF3_BIT 25 -#define DMA_LIFCR_CDMEIF3_BIT 24 -#define DMA_LIFCR_CFEIF3_BIT 22 -#define DMA_LIFCR_CTCIF2_BIT 21 -#define DMA_LIFCR_CHTIF2_BIT 20 -#define DMA_LIFCR_CTEIF2_BIT 19 -#define DMA_LIFCR_CDMEIF2_BIT 18 -#define DMA_LIFCR_CFEIF2_BIT 16 -#define DMA_LIFCR_CTCIF1_BIT 11 -#define DMA_LIFCR_CHTIF1_BIT 10 -#define DMA_LIFCR_CTEIF1_BIT 9 -#define DMA_LIFCR_CDMEIF1_BIT 8 -#define DMA_LIFCR_CFEIF1_BIT 6 -#define DMA_LIFCR_CTCIF0_BIT 5 -#define DMA_LIFCR_CHTIF0_BIT 4 -#define DMA_LIFCR_CTEIF0_BIT 3 -#define DMA_LIFCR_CDMEIF0_BIT 2 -#define DMA_LIFCR_CFEIF0_BIT 0 - -#define DMA_LIFCR_CTCIF3 (1U << DMA_LIFCR_CTCIF3_BIT) -#define DMA_LIFCR_CHTIF3 (1U << DMA_LIFCR_CHTIF3_BIT) -#define DMA_LIFCR_CTEIF3 (1U << DMA_LIFCR_CTEIF3_BIT) -#define DMA_LIFCR_CDMEIF3 (1U << DMA_LIFCR_CDMEIF3_BIT) -#define DMA_LIFCR_CFEIF3 (1U << DMA_LIFCR_CFEIF3_BIT) -#define DMA_LIFCR_CTCIF2 (1U << DMA_LIFCR_CTCIF2_BIT) -#define DMA_LIFCR_CHTIF2 (1U << DMA_LIFCR_CHTIF2_BIT) -#define DMA_LIFCR_CTEIF2 (1U << DMA_LIFCR_CTEIF2_BIT) -#define DMA_LIFCR_CDMEIF2 (1U << DMA_LIFCR_CDMEIF2_BIT) -#define DMA_LIFCR_CFEIF2 (1U << DMA_LIFCR_CFEIF2_BIT) -#define DMA_LIFCR_CTCIF1 (1U << DMA_LIFCR_CTCIF1_BIT) -#define DMA_LIFCR_CHTIF1 (1U << DMA_LIFCR_CHTIF1_BIT) -#define DMA_LIFCR_CTEIF1 (1U << DMA_LIFCR_CTEIF1_BIT) -#define DMA_LIFCR_CDMEIF1 (1U << DMA_LIFCR_CDMEIF1_BIT) -#define DMA_LIFCR_CFEIF1 (1U << DMA_LIFCR_CFEIF1_BIT) -#define DMA_LIFCR_CTCIF0 (1U << DMA_LIFCR_CTCIF0_BIT) -#define DMA_LIFCR_CHTIF0 (1U << DMA_LIFCR_CHTIF0_BIT) -#define DMA_LIFCR_CTEIF0 (1U << DMA_LIFCR_CTEIF0_BIT) -#define DMA_LIFCR_CDMEIF0 (1U << DMA_LIFCR_CDMEIF0_BIT) -#define DMA_LIFCR_CFEIF0 (1U << DMA_LIFCR_CFEIF0_BIT) - -/* High interrupt flag clear regsister */ - -#define DMA_HIFCR_CTCIF7_BIT 27 -#define DMA_HIFCR_CHTIF7_BIT 26 -#define DMA_HIFCR_CTEIF7_BIT 25 -#define DMA_HIFCR_CDMEIF7_BIT 24 -#define DMA_HIFCR_CFEIF7_BIT 22 -#define DMA_HIFCR_CTCIF6_BIT 21 -#define DMA_HIFCR_CHTIF6_BIT 20 -#define DMA_HIFCR_CTEIF6_BIT 19 -#define DMA_HIFCR_CDMEIF6_BIT 18 -#define DMA_HIFCR_CFEIF6_BIT 16 -#define DMA_HIFCR_CTCIF5_BIT 11 -#define DMA_HIFCR_CHTIF5_BIT 10 -#define DMA_HIFCR_CTEIF5_BIT 9 -#define DMA_HIFCR_CDMEIF5_BIT 8 -#define DMA_HIFCR_CFEIF5_BIT 6 -#define DMA_HIFCR_CTCIF4_BIT 5 -#define DMA_HIFCR_CHTIF4_BIT 4 -#define DMA_HIFCR_CTEIF4_BIT 3 -#define DMA_HIFCR_CDMEIF4_BIT 2 -#define DMA_HIFCR_CFEIF4_BIT 0 - -#define DMA_HIFCR_CTCIF7 (1U << DMA_HIFCR_CTCIF7_BIT) -#define DMA_HIFCR_CHTIF7 (1U << DMA_HIFCR_CHTIF7_BIT) -#define DMA_HIFCR_CTEIF7 (1U << DMA_HIFCR_CTEIF7_BIT) -#define DMA_HIFCR_CDMEIF7 (1U << DMA_HIFCR_CDMEIF7_BIT) -#define DMA_HIFCR_CFEIF7 (1U << DMA_HIFCR_CFEIF7_BIT) -#define DMA_HIFCR_CTCIF6 (1U << DMA_HIFCR_CTCIF6_BIT) -#define DMA_HIFCR_CHTIF6 (1U << DMA_HIFCR_CHTIF6_BIT) -#define DMA_HIFCR_CTEIF6 (1U << DMA_HIFCR_CTEIF6_BIT) -#define DMA_HIFCR_CDMEIF6 (1U << DMA_HIFCR_CDMEIF6_BIT) -#define DMA_HIFCR_CFEIF6 (1U << DMA_HIFCR_CFEIF6_BIT) -#define DMA_HIFCR_CTCIF5 (1U << DMA_HIFCR_CTCIF5_BIT) -#define DMA_HIFCR_CHTIF5 (1U << DMA_HIFCR_CHTIF5_BIT) -#define DMA_HIFCR_CTEIF5 (1U << DMA_HIFCR_CTEIF5_BIT) -#define DMA_HIFCR_CDMEIF5 (1U << DMA_HIFCR_CDMEIF5_BIT) -#define DMA_HIFCR_CFEIF5 (1U << DMA_HIFCR_CFEIF5_BIT) -#define DMA_HIFCR_CTCIF4 (1U << DMA_HIFCR_CTCIF4_BIT) -#define DMA_HIFCR_CHTIF4 (1U << DMA_HIFCR_CHTIF4_BIT) -#define DMA_HIFCR_CTEIF4 (1U << DMA_HIFCR_CTEIF4_BIT) -#define DMA_HIFCR_CDMEIF4 (1U << DMA_HIFCR_CDMEIF4_BIT) -#define DMA_HIFCR_CFEIF4 (1U << DMA_HIFCR_CFEIF4_BIT) - -/* Stream configuration register */ - -#define DMA_SCR_CT_BIT 19 -#define DMA_SCR_DBM_BIT 18 -#define DMA_SCR_PINCOS_BIT 15 -#define DMA_SCR_MINC_BIT 10 -#define DMA_SCR_PINC_BIT 9 -#define DMA_SCR_CIRC_BIT 8 -#define DMA_SCR_PFCTRL_BIT 5 -#define DMA_SCR_TCIE_BIT 4 -#define DMA_SCR_HTIE_BIT 3 -#define DMA_SCR_TEIE_BIT 2 -#define DMA_SCR_DMEIE_BIT 1 -#define DMA_SCR_EN_BIT 0 - -#define DMA_SCR_CHSEL (0x7 << 25) -#define DMA_SCR_CHSEL_CH_0 (0x0 << 25) -#define DMA_SCR_CHSEL_CH_1 (0x1 << 25) -#define DMA_SCR_CHSEL_CH_2 (0x2 << 25) -#define DMA_SCR_CHSEL_CH_3 (0x3 << 25) -#define DMA_SCR_CHSEL_CH_4 (0x4 << 25) -#define DMA_SCR_CHSEL_CH_5 (0x5 << 25) -#define DMA_SCR_CHSEL_CH_6 (0x6 << 25) -#define DMA_SCR_CHSEL_CH_7 (0x7 << 25) -#define DMA_SCR_MBURST (0x3 << 23) -#define DMA_SCR_MBURST_SINGLE (0x0 << 23) -#define DMA_SCR_MBURST_INCR4 (0x1 << 23) -#define DMA_SCR_MBURST_INCR8 (0x2 << 23) -#define DMA_SCR_MBURST_INCR16 (0x3 << 23) -#define DMA_SCR_PBURST (0x3 << 21) -#define DMA_SCR_PBURST_SINGLE (0x0 << 21) -#define DMA_SCR_PBURST_INCR4 (0x1 << 21) -#define DMA_SCR_PBURST_INCR8 (0x2 << 21) -#define DMA_SCR_PBURST_INCR16 (0x3 << 21) -#define DMA_SCR_CT (1U << DMA_SCR_CT_BIT) -#define DMA_SCR_DBM (1U << DMA_SCR_DBM_BIT) -#define DMA_SCR_PL (0x3 << 16) -#define DMA_SCR_PL_LOW (0x0 << 16) -#define DMA_SCR_PL_MEDIUM (0x1 << 16) -#define DMA_SCR_PL_HIGH (0x2 << 16) -#define DMA_SCR_VERY_HIGH (0x3 << 16) -#define DMA_SCR_PINCOS (1U << DMA_SCR_PINCOS_BIT) -#define DMA_SCR_MSIZE (0x3 << 13) -#define DMA_SCR_MSIZE_8BITS (0x0 << 13) -#define DMA_SCR_MSIZE_16BITS (0x1 << 13) -#define DMA_SCR_MSIZE_32BITS (0x2 << 13) -#define DMA_SCR_PSIZE (0x3 << 11) -#define DMA_SCR_PSIZE_8BITS (0x0 << 11) -#define DMA_SCR_PSIZE_16BITS (0x1 << 11) -#define DMA_SCR_PSIZE_32BITS (0x2 << 11) -#define DMA_SCR_MINC (1U << DMA_SCR_MINC_BIT) -#define DMA_SCR_PINC (1U << DMA_SCR_PINC_BIT) -#define DMA_SCR_CIRC (1U << DMA_SCR_CIRC_BIT) -#define DMA_SCR_DIR (0x3 << 6) -#define DMA_SCR_DIR_PER_TO_MEM (0x0 << 6) -#define DMA_SCR_DIR_MEM_TO_PER (0x1 << 6) -#define DMA_SCR_DIR_MEM_TO_MEM (0x2 << 6) -#define DMA_SCR_PFCTRL (1U << DMA_SCR_PFCTRL_BIT) -#define DMA_SCR_TCIE (1U << DMA_SCR_TCIE_BIT) -#define DMA_SCR_HTIE (1U << DMA_SCR_HTIE_BIT) -#define DMA_SCR_TEIE (1U << DMA_SCR_TEIE_BIT) -#define DMA_SCR_DMEIE (1U << DMA_SCR_DMEIE_BIT) -#define DMA_SCR_EN (1U << DMA_SCR_EN_BIT) - -/* Stream FIFO control register */ - -#define DMA_SFCR_FEIE_BIT 7 -#define DMA_SFCR_DMDIS_BIT 2 - -#define DMA_SFCR_FEIE (1U << DMA_SFCR_FEIE_BIT) -#define DMA_SFCR_FS (0x7 << 3) -#define DMA_SFCR_FS_ZERO_TO_QUARTER (0x0 << 3) -#define DMA_SFCR_FS_QUARTER_TO_HALF (0x1 << 3) -#define DMA_SFCR_FS_HALF_TO_THREE_QUARTERS (0x2 << 3) -#define DMA_SFCR_FS_THREE_QUARTERS_TO_FULL (0x3 << 3) -#define DMA_SFCR_FS_EMPTY (0x4 << 3) -#define DMA_SFCR_FS_FULL (0x5 << 3) -#define DMA_SFCR_DMDIS (1U << DMA_SFCR_DMDIS_BIT) -#define DMA_SFCR_FTH (0x3 << 0) -#define DMA_SFCR_FTH_QUARTER_FULL (0x0 << 3) -#define DMA_SFCR_FTH_HALF_FULL (0x1 << 3) -#define DMA_SFCR_FTH_THREE_QUARTERS_FULL (0x2 << 3) -#define DMA_SFCR_FTH_FULL (0x3 << 3) - -/* - * Devices - */ - -extern dma_dev *DMA1; -extern dma_dev *DMA2; - -/* - * Other types needed by, or useful for, - */ - -/** - * @brief DMA streams - * This is also the dma_tube type for STM32F2. - * @see dma_tube - */ -typedef enum dma_stream { - DMA_S0 = 0, - DMA_S1 = 1, - DMA_S2 = 2, - DMA_S3 = 3, - DMA_S4 = 4, - DMA_S5 = 5, - DMA_S6 = 6, - DMA_S7 = 7, -} dma_stream; - -/** STM32F2 dma_tube (=dma_stream) */ -#define dma_tube dma_stream - -/** - * @brief STM32F2 configuration flags for dma_tube_config. - * @see struct dma_tube_config - */ -typedef enum dma_cfg_flags { - /* NB: flags that aren't SCR bits are treated specially. */ - - /** - * Source address increment mode - * - * If this flag is set, the source address is incremented (by the - * source size) after each DMA transfer. - */ - DMA_CFG_SRC_INC = 1U << 31, - - /** - * Destination address increment mode - * - * If this flag is set, the destination address is incremented (by - * the destination size) after each DMA transfer. - */ - DMA_CFG_DST_INC = 1U << 30, - - /** - * Circular mode - * - * This mode is not available for memory-to-memory transfers. - */ - DMA_CFG_CIRC = DMA_SCR_CIRC, - - /** Transfer complete interrupt enable */ - DMA_CFG_CMPLT_IE = DMA_SCR_TCIE, - /** Transfer half-complete interrupt enable */ - DMA_CFG_HALF_CMPLT_IE = DMA_SCR_HTIE, - /** Transfer error interrupt enable */ - DMA_CFG_ERR_IE = DMA_SCR_TEIE, - /** Direct mode error interrupt enable */ - DMA_CFG_DM_ERR_IE = DMA_SCR_DMEIE, - /** FIFO error interrupt enable */ - DMA_CFG_FIFO_ERR_IE = (1U << 29), -} dma_cfg_flags; - -/** - * @brief STM32F2 DMA request sources. - * - * IMPORTANT: - * - * 1. On STM32F2, a particular dma_request_src is always tied to a - * single DMA controller, but often can be supported by multiple - * streams. For example, DMA requests from ADC1 (DMA_REQ_SRC_ADC1) can - * only be handled by DMA2, but they can go to either stream 0 or - * stream 4 (though not any other stream). If you try to use a request - * source with the wrong DMA controller or the wrong stream on - * STM32F2, dma_tube_cfg() will fail. - * - * 2. A single stream can only handle a single request source at a - * time. If you change a stream's request source later, it will stop - * serving requests from the old source. However, for some streams, - * some sources conflict with one another (when they correspond to the - * same channel on that stream), and on STM32F2, Terrible Super-Bad - * Things will happen if two conflicting request sources are active at - * the same time. - * - * @see struct dma_tube_config - * @see dma_tube_cfg() - */ -typedef enum dma_request_src { - /* These are constructed like so (though this may change, so user - * code shouldn't depend on it): - * - * Bits 0--2: Channel associated with request source - * - * Bits 3--9: rcc_clk_id of DMA controller associated with request source - * - * Bits 10--17: Bit mask of streams which can handle that request - * source. (E.g., bit 10 set means stream 0 can - * handle the source, bit 11 set means stream 1 can, - * etc.) - * - * Among other things, this is used for error checking in - * dma_tube_cfg(). If you change this bit encoding, you need to - * update the helper functions in stm32f2/dma.c. - */ -#define _DMA_STM32F2_REQ_SRC(stream_mask, clk_id, channel) \ - (((stream_mask) << 10) | ((clk_id) << 3) | (channel)) -#define _DMA_S(n) (1U << (n)) - - /* DMA1 request sources */ -#define _DMA_1_REQ_SRC(stream_mask, channel) \ - _DMA_STM32F2_REQ_SRC(stream_mask, RCC_DMA1, channel) - - /* Channel 0 */ - DMA_REQ_SRC_SPI3_RX = _DMA_1_REQ_SRC(_DMA_S(0) | _DMA_S(2), 0), - DMA_REQ_SRC_SPI2_RX = _DMA_1_REQ_SRC(_DMA_S(3), 0), - DMA_REQ_SRC_SPI2_TX = _DMA_1_REQ_SRC(_DMA_S(4), 0), - DMA_REQ_SRC_SPI3_TX = _DMA_1_REQ_SRC(_DMA_S(5) | _DMA_S(7), 0), - - /* Channel 1 */ - DMA_REQ_SRC_I2C1_RX = _DMA_1_REQ_SRC(_DMA_S(0) | _DMA_S(5), 1), - DMA_REQ_SRC_TIM7_UP = _DMA_1_REQ_SRC(_DMA_S(2) | _DMA_S(4), 1), - DMA_REQ_SRC_I2C1_TX = _DMA_1_REQ_SRC(_DMA_S(6) | _DMA_S(7), 1), - - /* Channel 2 */ - DMA_REQ_SRC_TIM4_CH1 = _DMA_1_REQ_SRC(_DMA_S(0), 2), - DMA_REQ_SRC_TIM4_CH2 = _DMA_1_REQ_SRC(_DMA_S(3), 2), - DMA_REQ_SRC_TIM4_UP = _DMA_1_REQ_SRC(_DMA_S(6), 2), - DMA_REQ_SRC_TIM4_CH3 = _DMA_1_REQ_SRC(_DMA_S(7), 2), - - /* Channel 3 */ - DMA_REQ_SRC_TIM2_UP = _DMA_1_REQ_SRC(_DMA_S(1) | _DMA_S(7), 3), - DMA_REQ_SRC_TIM2_CH3 = _DMA_1_REQ_SRC(_DMA_S(1), 3), - DMA_REQ_SRC_I2C3_RX = _DMA_1_REQ_SRC(_DMA_S(2), 3), - DMA_REQ_SRC_I2C3_TX = _DMA_1_REQ_SRC(_DMA_S(4), 3), - DMA_REQ_SRC_TIM2_CH1 = _DMA_1_REQ_SRC(_DMA_S(5), 3), - DMA_REQ_SRC_TIM2_CH2 = _DMA_1_REQ_SRC(_DMA_S(6), 3), - DMA_REQ_SRC_TIM2_CH4 = _DMA_1_REQ_SRC(_DMA_S(6) | _DMA_S(7), 3), - - /* Channel 4 */ - DMA_REQ_SRC_UART5_RX = _DMA_1_REQ_SRC(_DMA_S(0), 4), - DMA_REQ_SRC_USART3_RX = _DMA_1_REQ_SRC(_DMA_S(1), 4), - DMA_REQ_SRC_UART4_RX = _DMA_1_REQ_SRC(_DMA_S(2), 4), - DMA_REQ_SRC_USART3_TX = _DMA_1_REQ_SRC(_DMA_S(3), 4), - DMA_REQ_SRC_UART4_TX = _DMA_1_REQ_SRC(_DMA_S(4), 4), - DMA_REQ_SRC_USART2_RX = _DMA_1_REQ_SRC(_DMA_S(5), 4), - DMA_REQ_SRC_USART2_TX = _DMA_1_REQ_SRC(_DMA_S(6), 4), - DMA_REQ_SRC_UART5_TX = _DMA_1_REQ_SRC(_DMA_S(7), 4), - - /* Channel 5 */ - DMA_REQ_SRC_TIM3_CH4 = _DMA_1_REQ_SRC(_DMA_S(2), 5), - DMA_REQ_SRC_TIM3_UP = _DMA_1_REQ_SRC(_DMA_S(2), 5), - DMA_REQ_SRC_TIM3_CH1 = _DMA_1_REQ_SRC(_DMA_S(4), 5), - DMA_REQ_SRC_TIM3_TRIG = _DMA_1_REQ_SRC(_DMA_S(4), 5), - DMA_REQ_SRC_TIM3_CH2 = _DMA_1_REQ_SRC(_DMA_S(5), 5), - DMA_REQ_SRC_TIM3_CH3 = _DMA_1_REQ_SRC(_DMA_S(7), 5), - - /* Channel 6 */ - DMA_REQ_SRC_TIM5_CH3 = _DMA_1_REQ_SRC(_DMA_S(0), 6), - DMA_REQ_SRC_TIM5_UP = _DMA_1_REQ_SRC(_DMA_S(0) | _DMA_S(6), 6), - DMA_REQ_SRC_TIM5_CH4 = _DMA_1_REQ_SRC(_DMA_S(1) | _DMA_S(3), 6), - DMA_REQ_SRC_TIM5_TRIG = _DMA_1_REQ_SRC(_DMA_S(1) | _DMA_S(3), 6), - DMA_REQ_SRC_TIM5_CH1 = _DMA_1_REQ_SRC(_DMA_S(2), 6), - DMA_REQ_SRC_TIM5_CH2 = _DMA_1_REQ_SRC(_DMA_S(4), 6), - - /* Channel 7 */ - DMA_REQ_SRC_TIM6_UP = _DMA_1_REQ_SRC(_DMA_S(1), 7), - DMA_REQ_SRC_I2C2_RX = _DMA_1_REQ_SRC(_DMA_S(2) | _DMA_S(3), 7), - DMA_REQ_SRC_USART3_TX_ALTERNATE = _DMA_1_REQ_SRC(_DMA_S(4), 7), - DMA_REQ_SRC_DAC1 = _DMA_1_REQ_SRC(_DMA_S(5), 7), - DMA_REQ_SRC_DAC2 = _DMA_1_REQ_SRC(_DMA_S(6), 7), - DMA_REQ_SRC_I2C2_TX = _DMA_1_REQ_SRC(_DMA_S(7), 7), -#undef _DMA_1_REQ_SRC - - /* DMA2 request sources */ -#define _DMA_2_REQ_SRC(stream_mask, channel) \ - _DMA_STM32F2_REQ_SRC(stream_mask, RCC_DMA2, channel) - - /* Channel 0 */ - DMA_REQ_SRC_ADC1 = _DMA_2_REQ_SRC(_DMA_S(0) | _DMA_S(4), 0), - /* You can use these "DMA_REQ_SRC_TIMx_CHx_ALTERNATE" if you know - * what you're doing, but the other ones (for channels 6 and 7), - * are better, in that they don't conflict with one another. */ - DMA_REQ_SRC_TIM8_CH1_ALTERNATE = _DMA_2_REQ_SRC(_DMA_S(2), 0), - DMA_REQ_SRC_TIM8_CH2_ALTERNATE = _DMA_2_REQ_SRC(_DMA_S(2), 0), - DMA_REQ_SRC_TIM8_CH3_ALTERNATE = _DMA_2_REQ_SRC(_DMA_S(2), 0), - DMA_REQ_SRC_TIM1_CH1_ALTERNATE = _DMA_2_REQ_SRC(_DMA_S(6), 0), - DMA_REQ_SRC_TIM1_CH2_ALTERNATE = _DMA_2_REQ_SRC(_DMA_S(6), 0), - DMA_REQ_SRC_TIM1_CH3_ALTENRATE = _DMA_2_REQ_SRC(_DMA_S(6), 0), - - /* Channel 1 */ - DMA_REQ_SRC_DCMI = _DMA_2_REQ_SRC(_DMA_S(1) | _DMA_S(7), 1), - DMA_REQ_SRC_ADC2 = _DMA_2_REQ_SRC(_DMA_S(2) | _DMA_S(3), 1), - - /* Channel 2 */ - DMA_REQ_SRC_ADC3 = _DMA_2_REQ_SRC(_DMA_S(0) | _DMA_S(1), 2), - DMA_REQ_SRC_CRYP_OUT = _DMA_2_REQ_SRC(_DMA_S(5), 2), - DMA_REQ_SRC_CRYP_IN = _DMA_2_REQ_SRC(_DMA_S(6), 2), - DMA_REQ_SRC_HASH_IN = _DMA_2_REQ_SRC(_DMA_S(7), 2), - - /* Channel 3 */ - DMA_REQ_SRC_SPI1_RX = _DMA_2_REQ_SRC(_DMA_S(0) | _DMA_S(2), 3), - DMA_REQ_SRC_SPI1_TX = _DMA_2_REQ_SRC(_DMA_S(3) | _DMA_S(5), 3), - - /* Channel 4 */ - DMA_REQ_SRC_USART1_RX = _DMA_2_REQ_SRC(_DMA_S(2) | _DMA_S(5), 4), - DMA_REQ_SRC_SDIO = _DMA_2_REQ_SRC(_DMA_S(3) | _DMA_S(6), 4), - DMA_REQ_SRC_USART1_TX = _DMA_2_REQ_SRC(_DMA_S(7), 4), - - /* Channel 5 */ - DMA_REQ_SRC_USART6_RX = _DMA_2_REQ_SRC(_DMA_S(1) | _DMA_S(2), 5), - DMA_REQ_SRC_USART6_TX = _DMA_2_REQ_SRC(_DMA_S(6) | _DMA_S(7), 5), - - /* Channel 6 */ - DMA_REQ_SRC_TIM1_TRIG = _DMA_2_REQ_SRC(_DMA_S(0) | _DMA_S(4), 6), - DMA_REQ_SRC_TIM1_CH1 = _DMA_2_REQ_SRC(_DMA_S(1) | _DMA_S(3), 6), - DMA_REQ_SRC_TIM1_CH2 = _DMA_2_REQ_SRC(_DMA_S(3), 6), - DMA_REQ_SRC_TIM1_CH4 = _DMA_2_REQ_SRC(_DMA_S(4), 6), - DMA_REQ_SRC_TIM1_COM = _DMA_2_REQ_SRC(_DMA_S(4), 6), - DMA_REQ_SRC_TIM1_UP = _DMA_2_REQ_SRC(_DMA_S(5), 6), - DMA_REQ_SRC_TIM1_CH3 = _DMA_2_REQ_SRC(_DMA_S(6), 6), - - /* Channel 7 */ - DMA_REQ_SRC_TIM8_UP = _DMA_2_REQ_SRC(_DMA_S(1), 7), - DMA_REQ_SRC_TIM8_CH1 = _DMA_2_REQ_SRC(_DMA_S(2), 7), - DMA_REQ_SRC_TIM8_CH2 = _DMA_2_REQ_SRC(_DMA_S(3), 7), - DMA_REQ_SRC_TIM8_CH3 = _DMA_2_REQ_SRC(_DMA_S(4), 7), - DMA_REQ_SRC_TIM8_CH4 = _DMA_2_REQ_SRC(_DMA_S(7), 7), - DMA_REQ_SRC_TIM8_TRIG = _DMA_2_REQ_SRC(_DMA_S(7), 7), - DMA_REQ_SRC_TIM8_COM = _DMA_2_REQ_SRC(_DMA_S(7), 7), -#undef _DMA_2_REQ_SRC -#undef _DMA_S -} dma_request_src; - -/* - * Tube conveniences - */ - -static inline dma_tube_reg_map* dma_tube_regs(dma_dev *dev, - dma_tube tube) { - ASSERT(DMA_S0 <= tube && tube <= DMA_S7); - switch (dev->clk_id) { - case RCC_DMA1: - return DMA1S0_BASE + (int)tube; - case RCC_DMA2: - return DMA2S0_BASE + (int)tube; - default: - /* Can't happen */ - ASSERT(0); - return 0; - } -} - -static inline uint8 dma_is_enabled(dma_dev *dev, dma_tube tube) { - return dma_tube_regs(dev, tube)->SCR & DMA_SCR_EN; -} - -/* F2-only; available because of double-buffering. */ -void dma_set_mem_n_addr(dma_dev *dev, dma_tube tube, int n, - __io void *address); - -/** - * @brief Set memory 0 address. - * Availability: STM32F2. - * - * @param dev DMA device - * @param tube Tube whose memory 0 address to set - * @param addr Address to use as memory 0 - */ -static inline __always_inline void -dma_set_mem0_addr(dma_dev *dev, dma_tube tube, __io void *addr) { - dma_set_mem_n_addr(dev, tube, 0, addr); -} - -/** - * @brief Set memory 1 address. - * Availability: STM32F2. - * - * @param dev DMA device - * @param tube Tube whose memory 1 address to set - * @param addr Address to use as memory 1 - */ -static inline __always_inline void -dma_set_mem1_addr(dma_dev *dev, dma_tube tube, __io void *addr) { - dma_set_mem_n_addr(dev, tube, 1, addr); -} - -/* Assume the user means SM0AR in a non-double-buffered configuration. */ -static inline __always_inline void -dma_set_mem_addr(dma_dev *dev, dma_tube tube, __io void *addr) { - dma_set_mem0_addr(dev, tube, addr); -} - -/* SM0AR and SM1AR are treated as though they have the same size */ -static inline dma_xfer_size dma_get_mem_size(dma_dev *dev, dma_tube tube) { - return (dma_xfer_size)(dma_tube_regs(dev, tube)->SCR >> 13); -} - -static inline dma_xfer_size dma_get_per_size(dma_dev *dev, dma_tube tube) { - return (dma_xfer_size)(dma_tube_regs(dev, tube)->SCR >> 11); -} - -void dma_enable_fifo(dma_dev *dev, dma_tube tube); -void dma_disable_fifo(dma_dev *dev, dma_tube tube); - -static inline __always_inline int dma_is_fifo_enabled(dma_dev *dev, dma_tube tube) { - return dma_tube_regs(dev, tube)->SFCR & DMA_SFCR_DMDIS; -} - -/* - * TODO: - * - Double-buffer configuration function - * - FIFO configuration function - * - MBURST/PBURST configuration function - */ - -/* - * ISR/IFCR conveniences. - */ - -/* (undocumented) helper for reading LISR/HISR and writing - * LIFCR/HIFCR. For these registers, - * - * S0, S4: bits start at bit 0 - * S1, S5: 6 - * S2, S6: 16 - * S3, S7: 22 - * - * I can't imagine why ST didn't just use a byte for each group. The - * bits fit, and it would have made functions like these simpler and - * faster. Oh well. */ -static inline __always_inline uint32 _dma_sr_fcr_shift(dma_tube tube) { - switch (tube) { - case DMA_S0: /* fall through */ - case DMA_S4: - return 0; - case DMA_S1: /* fall through */ - case DMA_S5: - return 6; - case DMA_S2: /* fall through */ - case DMA_S6: - return 16; - case DMA_S3: /* fall through */ - case DMA_S7: - return 22; - } - /* Can't happen */ - ASSERT(0); - return 0; -} - -static inline uint8 dma_get_isr_bits(dma_dev *dev, dma_tube tube) { - dma_reg_map *regs = dev->regs; - __io uint32 *isr = tube > DMA_S3 ? ®s->HISR : ®s->LISR; - return (*isr >> _dma_sr_fcr_shift(tube)) & 0x3D; -} - -static inline void dma_clear_isr_bits(dma_dev *dev, dma_tube tube) { - dma_reg_map *regs = dev->regs; - __io uint32 *ifcr = tube > DMA_S3 ? ®s->HIFCR : ®s->LIFCR; - *ifcr = (0x3D << _dma_sr_fcr_shift(tube)); -} - -#undef _DMA_IRQ_BIT_SHIFT - -#ifdef __cplusplus -} // extern "C" -#endif - -#endif diff --git a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/exti.h b/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/exti.h deleted file mode 100644 index 4643fcf..0000000 --- a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/exti.h +++ /dev/null @@ -1,46 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2012 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/stm32f1/include/series/exti.h - * @brief STM32F2 external interrupts - */ - -#ifndef _LIBMAPLE_STM32F2_EXTI_H_ -#define _LIBMAPLE_STM32F2_EXTI_H_ - -#ifdef __cpluspus -extern "C" { -#endif - -struct exti_reg_map; -#define EXTI_BASE ((struct exti_reg_map*)0x40013C00) - -#ifdef __cpluspus -} -#endif - -#endif diff --git a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/flash.h b/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/flash.h deleted file mode 100644 index a3c3933..0000000 --- a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/flash.h +++ /dev/null @@ -1,202 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/stm32f2/include/series/flash.h - * @brief STM32F2 Flash header. - * - * Provides register map, base pointer, and register bit definitions - * for the Flash controller on the STM32F2 series, along with - * series-specific configuration values. - */ - -#ifndef _LIBMAPLE_STM32F2_FLASH_H_ -#define _LIBMAPLE_STM32F2_FLASH_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -#include - -/* - * Register map - */ - -/** @brief STM32F2 Flash register map type */ -typedef struct flash_reg_map { - __io uint32 ACR; /**< Access control register */ - __io uint32 KEYR; /**< Key register */ - __io uint32 OPTKEYR; /**< Option key register */ - __io uint32 SR; /**< Status register */ - __io uint32 CR; /**< Control register */ - __io uint32 OPTCR; /**< Option control register */ -} flash_reg_map; - -#define FLASH_BASE ((struct flash_reg_map*)0x40023C00) - -/* - * Register bit definitions - */ - -/* Access control register */ - -#define FLASH_ACR_DCRST_BIT 12 -#define FLASH_ACR_ICRST_BIT 11 -#define FLASH_ACR_DCEN_BIT 10 -#define FLASH_ACR_ICEN_BIT 9 -#define FLASH_ACR_PRFTEN_BIT 8 - -#define FLASH_ACR_DCRST (1U << FLASH_ACR_DCRST_BIT) -#define FLASH_ACR_ICRST (1U << FLASH_ACR_ICRST_BIT) -#define FLASH_ACR_DCEN (1U << FLASH_ACR_DCEN_BIT) -#define FLASH_ACR_ICEN (1U << FLASH_ACR_ICEN_BIT) -#define FLASH_ACR_PRFTEN (1U << FLASH_ACR_PRFTEN_BIT) -#define FLASH_ACR_LATENCY 0x7 -#define FLASH_ACR_LATENCY_0WS 0x0 -#define FLASH_ACR_LATENCY_1WS 0x1 -#define FLASH_ACR_LATENCY_2WS 0x2 -#define FLASH_ACR_LATENCY_3WS 0x3 -#define FLASH_ACR_LATENCY_4WS 0x4 -#define FLASH_ACR_LATENCY_5WS 0x5 -#define FLASH_ACR_LATENCY_6WS 0x6 -#define FLASH_ACR_LATENCY_7WS 0x7 - -/* Key register */ - -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB - -/* Option key register */ - -#define FLASH_OPTKEYR_OPTKEY1 0x08192A3B -#define FLASH_OPTKEYR_OPTKEY2 0x4C5D6E7F - -/* Status register */ - -#define FLASH_SR_BSY_BIT 16 -#define FLASH_SR_PGSERR_BIT 7 -#define FLASH_SR_PGPERR_BIT 6 -#define FLASH_SR_PGAERR_BIT 5 -#define FLASH_SR_WRPERR_BIT 4 -#define FLASH_SR_OPERR_BIT 1 -#define FLASH_SR_EOP_BIT 0 - -#define FLASH_SR_BSY (1U << FLASH_SR_BSY_BIT) -#define FLASH_SR_PGSERR (1U << FLASH_SR_PGSERR_BIT) -#define FLASH_SR_PGPERR (1U << FLASH_SR_PGPERR_BIT) -#define FLASH_SR_PGAERR (1U << FLASH_SR_PGAERR_BIT) -#define FLASH_SR_WRPERR (1U << FLASH_SR_WRPERR_BIT) -#define FLASH_SR_OPERR (1U << FLASH_SR_OPERR_BIT) -#define FLASH_SR_EOP (1U << FLASH_SR_EOP_BIT) - -/* Control register */ - -#define FLASH_CR_LOCK_BIT 31 -#define FLASH_CR_ERRIE_BIT 25 -#define FLASH_CR_EOPIE_BIT 24 -#define FLASH_CR_STRT_BIT 16 -#define FLASH_CR_MER_BIT 2 -#define FLASH_CR_SER_BIT 1 -#define FLASH_CR_PG_BIT 0 - -#define FLASH_CR_LOCK (1U << FLASH_CR_LOCK_BIT) -#define FLASH_CR_ERRIE (1U << FLASH_CR_ERRIE_BIT) -#define FLASH_CR_EOPIE (1U << FLASH_CR_EOPIE_BIT) -#define FLASH_CR_STRT (1U << FLASH_CR_STRT_BIT) - -#define FLASH_CR_PSIZE (0x3 << 8) -#define FLASH_CR_PSIZE_MUL8 (0x0 << 8) -#define FLASH_CR_PSIZE_MUL16 (0x1 << 8) -#define FLASH_CR_PSIZE_MUL32 (0x2 << 8) -#define FLASH_CR_PSIZE_MUL64 (0x3 << 8) - -#define FLASH_CR_SNB (0xF << 3) -#define FLASH_CR_SNB_0 (0x0 << 3) -#define FLASH_CR_SNB_1 (0x1 << 3) -#define FLASH_CR_SNB_2 (0x2 << 3) -#define FLASH_CR_SNB_3 (0x3 << 3) -#define FLASH_CR_SNB_4 (0x4 << 3) -#define FLASH_CR_SNB_5 (0x5 << 3) -#define FLASH_CR_SNB_6 (0x6 << 3) -#define FLASH_CR_SNB_7 (0x7 << 3) -#define FLASH_CR_SNB_8 (0x8 << 3) -#define FLASH_CR_SNB_9 (0x9 << 3) -#define FLASH_CR_SNB_10 (0xA << 3) -#define FLASH_CR_SNB_11 (0xB << 3) - -#define FLASH_CR_MER (1U << FLASH_CR_MER_BIT) -#define FLASH_CR_SER (1U << FLASH_CR_SER_BIT) -#define FLASH_CR_PG (1U << FLASH_CR_PG_BIT) - -/* Option control register */ - -#define FLASH_OPTCR_NRST_STDBY_BIT 7 -#define FLASH_OPTCR_NRST_STOP_BIT 6 -#define FLASH_OPTCR_WDG_SW_BIT 5 -#define FLASH_OPTCR_OPTSTRT_BIT 1 -#define FLASH_OPTCR_OPTLOCK_BIT 0 - -#define FLASH_OPTCR_NWRP (0x3FF << 16) - -/* Excluded: The many level 1 values */ -#define FLASH_OPTCR_RDP (0xFF << 8) -#define FLASH_OPTCR_RDP_LEVEL0 (0xAA << 8) -#define FLASH_OPTCR_RDP_LEVEL2 (0xCC << 8) - -#define FLASH_OPTCR_USER (0x7 << 5) -#define FLASH_OPTCR_nRST_STDBY (1U << FLASH_OPTCR_nRST_STDBY_BIT) -#define FLASH_OPTCR_nRST_STOP (1U << FLASH_OPTCR_nRST_STOP_BIT) -#define FLASH_OPTCR_WDG_SW (1U << FLASH_OPTCR_WDG_SW_BIT) - -#define FLASH_OPTCR_BOR_LEV (0x3 << 2) -#define FLASH_OPTCR_BOR_LEVEL3 (0x0 << 2) -#define FLASH_OPTCR_BOR_LEVEL2 (0x1 << 2) -#define FLASH_OPTCR_BOR_LEVEL1 (0x2 << 2) -#define FLASH_OPTCR_BOR_OFF (0x3 << 2) - -#define FLASH_OPTCR_OPTSTRT (1U << FLASH_OPTCR_OPTSTRT_BIT) -#define FLASH_OPTCR_OPTLOCK (1U << FLASH_OPTCR_OPTLOCK_BIT) - -/* - * Series-specific configuration values - */ - -/* Note that this value depends on a 2.7V--3.6V supply voltage */ -#define FLASH_SAFE_WAIT_STATES FLASH_WAIT_STATE_3 - -/* Flash memory features available via ACR. */ -enum { - FLASH_PREFETCH = 0x100, - FLASH_ICACHE = 0x200, - FLASH_DCACHE = 0x400, -}; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/gpio.h b/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/gpio.h deleted file mode 100644 index 4d0d98c..0000000 --- a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/gpio.h +++ /dev/null @@ -1,264 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011, 2012 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. -*****************************************************************************/ - -/** - * @file libmaple/stm32f2/include/series/gpio.h - * @brief STM32F2 GPIO support. - */ - -#ifndef _LIBMAPLE_STM32F2_GPIO_H_ -#define _LIBMAPLE_STM32F2_GPIO_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -#include - -/* - * GPIO register maps and devices - */ - -/** GPIO register map type */ -typedef struct gpio_reg_map { - __io uint32 MODER; /**< Mode register */ - __io uint32 OTYPER; /**< Output type register */ - __io uint32 OSPEEDR; /**< Output speed register */ - __io uint32 PUPDR; /**< Pull-up/pull-down register */ - __io uint32 IDR; /**< Input data register */ - __io uint32 ODR; /**< Output data register */ - __io uint32 BSRR; /**< Bit set/reset register */ - __io uint32 LCKR; /**< Configuration lock register */ - __io uint32 AFRL; /**< Alternate function low register */ - __io uint32 AFRH; /**< Alternate function high register */ -} gpio_reg_map; - -/** GPIO port A register map base pointer */ -#define GPIOA_BASE ((struct gpio_reg_map*)0x40020000) -/** GPIO port B register map base pointer */ -#define GPIOB_BASE ((struct gpio_reg_map*)0x40020400) -/** GPIO port C register map base pointer */ -#define GPIOC_BASE ((struct gpio_reg_map*)0x40020800) -/** GPIO port D register map base pointer */ -#define GPIOD_BASE ((struct gpio_reg_map*)0x40020C00) -/** GPIO port E register map base pointer */ -#define GPIOE_BASE ((struct gpio_reg_map*)0x40021000) -/** GPIO port F register map base pointer */ -#define GPIOF_BASE ((struct gpio_reg_map*)0x40021400) -/** GPIO port G register map base pointer */ -#define GPIOG_BASE ((struct gpio_reg_map*)0x40021800) -/** GPIO port H register map base pointer */ -#define GPIOH_BASE ((struct gpio_reg_map*)0x40021C00) -/** GPIO port I register map base pointer */ -#define GPIOI_BASE ((struct gpio_reg_map*)0x40022000) - -struct gpio_dev; -extern struct gpio_dev* const GPIOA; -extern struct gpio_dev gpioa; -extern struct gpio_dev* const GPIOB; -extern struct gpio_dev gpiob; -extern struct gpio_dev* const GPIOC; -extern struct gpio_dev gpioc; -extern struct gpio_dev* const GPIOD; -extern struct gpio_dev gpiod; -extern struct gpio_dev* const GPIOE; -extern struct gpio_dev gpioe; -extern struct gpio_dev* const GPIOF; -extern struct gpio_dev gpiof; -extern struct gpio_dev* const GPIOG; -extern struct gpio_dev gpiog; -extern struct gpio_dev* const GPIOH; -extern struct gpio_dev gpioh; -extern struct gpio_dev* const GPIOI; -extern struct gpio_dev gpioi; - -/* - * Register bit definitions - * - * Currently, we only provide masks to be used for shifting for some - * registers, rather than repeating the same values 16 times. - */ - -/* Mode register */ - -#define GPIO_MODER_INPUT 0x0 -#define GPIO_MODER_OUTPUT 0x1 -#define GPIO_MODER_AF 0x2 -#define GPIO_MODER_ANALOG 0x3 - -/* Output type register */ - -#define GPIO_OTYPER_PP 0x0 -#define GPIO_OTYPER_OD 0x1 - -/* Output speed register */ - -#define GPIO_OSPEEDR_LOW 0x0 -#define GPIO_OSPEEDR_MED 0x1 -#define GPIO_OSPEEDR_FAST 0x2 -#define GPIO_OSPEEDR_HIGH 0x3 - -/* Pull-up/pull-down register */ - -#define GPIO_PUPDR_NOPUPD 0x0 -#define GPIO_PUPDR_PU 0x1 -#define GPIO_PUPDR_PD 0x2 - -/* Alternate function register low */ - -#define GPIO_AFRL_AF0 (0xFU << 0) -#define GPIO_AFRL_AF1 (0xFU << 4) -#define GPIO_AFRL_AF2 (0xFU << 8) -#define GPIO_AFRL_AF3 (0xFU << 12) -#define GPIO_AFRL_AF4 (0xFU << 16) -#define GPIO_AFRL_AF5 (0xFU << 20) -#define GPIO_AFRL_AF6 (0xFU << 24) -#define GPIO_AFRL_AF7 (0xFU << 28) - -/* Alternate function register high */ - -#define GPIO_AFRH_AF8 (0xFU << 0) -#define GPIO_AFRH_AF9 (0xFU << 4) -#define GPIO_AFRH_AF10 (0xFU << 8) -#define GPIO_AFRH_AF11 (0xFU << 12) -#define GPIO_AFRH_AF12 (0xFU << 16) -#define GPIO_AFRH_AF13 (0xFU << 20) -#define GPIO_AFRH_AF14 (0xFU << 24) -#define GPIO_AFRH_AF15 (0xFU << 28) - -/* - * GPIO routines - */ - -/** - * @brief GPIO pin modes - */ -typedef enum gpio_pin_mode { - GPIO_MODE_INPUT = GPIO_MODER_INPUT, /**< Input mode */ - GPIO_MODE_OUTPUT = GPIO_MODER_OUTPUT, /**< Output mode */ - GPIO_MODE_AF = GPIO_MODER_AF, /**< Alternate function mode */ - GPIO_MODE_ANALOG = GPIO_MODER_ANALOG, /**< Analog mode */ -} gpio_pin_mode; - -/** - * @brief Additional flags to be used when setting a pin's mode. - * - * Beyond the basic modes (input, general purpose output, alternate - * function, and analog), there are three parameters that can affect a - * pin's mode: - * - * 1. Output type: push/pull or open-drain. This only has an effect - * for output modes. Choices are: GPIO_MODEF_TYPE_PP (the default) - * and GPIO_MODEF_TYPE_OD. - * - * 2. Output speed: specifies the frequency at which a pin changes - * state. This only has an effect for output modes. Choices are: - * GPIO_MODEF_SPEED_LOW (default), GPIO_MODEF_SPEED_MED, - * GPIO_MODEF_SPEED_FAST, and GPIO_MODEF_SPEED_HIGH. - * - * 3. Push/pull setting: All GPIO pins have weak pull-up and pull-down - * resistors that can be enabled when the pin's mode is - * set. Choices are: GPIO_MODEF_PUPD_NONE (default), - * GPIO_MODEF_PUPD_PU, and GPIO_MODEF_PUPD_PD. - */ -typedef enum gpio_mode_flags { - /* Output type in bit 0 */ - GPIO_MODEF_TYPE_PP = GPIO_OTYPER_PP, /**< Output push/pull (default). - Applies only when the mode - specifies output. */ - GPIO_MODEF_TYPE_OD = GPIO_OTYPER_OD, /**< Output open drain. - Applies only when the mode - specifies output. */ - - /* Speed in bits 2:1 */ - GPIO_MODEF_SPEED_LOW = GPIO_OSPEEDR_LOW << 1, /**< Low speed (default): - 2 MHz. */ - GPIO_MODEF_SPEED_MED = GPIO_OSPEEDR_MED << 1, /**< Medium speed: 25 MHz. */ - GPIO_MODEF_SPEED_FAST = GPIO_OSPEEDR_FAST << 1, /**< Fast speed: 50 MHz. */ - GPIO_MODEF_SPEED_HIGH = GPIO_OSPEEDR_HIGH << 1, /**< High speed: - 100 MHz on 30 pF, - 80 MHz on 15 pF. */ - - /* Pull-up/pull-down in bits 4:3 */ - GPIO_MODEF_PUPD_NONE = GPIO_PUPDR_NOPUPD << 3, /**< No pull-up/pull-down - (default). */ - GPIO_MODEF_PUPD_PU = GPIO_PUPDR_PU << 3, /**< Pull-up */ - GPIO_MODEF_PUPD_PD = GPIO_PUPDR_PD << 3, /**< Pull-down */ -} gpio_mode_flags; - -void gpio_set_modef(struct gpio_dev *dev, - uint8 bit, - gpio_pin_mode mode, - unsigned flags); - -/** - * @brief Set the mode of a GPIO pin. - * - * Calling this function is equivalent to calling gpio_set_modef(dev, - * pin, mode, GPIO_MODE_SPEED_HIGH). Note that this overrides the - * default speed. - * - * @param dev GPIO device. - * @param bit Bit on the device whose mode to set, 0--15. - * @param mode Mode to set the pin to. - */ -static inline void gpio_set_mode(struct gpio_dev *dev, - uint8 bit, - gpio_pin_mode mode) { - gpio_set_modef(dev, bit, mode, GPIO_MODEF_SPEED_HIGH); -} - -/** - * @brief GPIO alternate functions. - * Use these to select an alternate function for a pin. - * @see gpio_set_af() - */ -typedef enum gpio_af { - GPIO_AF_SYS = 0, /**< System. */ - GPIO_AF_TIM_1_2 = 1, /**< Timers 1 and 2. */ - GPIO_AF_TIM_3_4_5 = 2, /**< Timers 3, 4, and 5. */ - GPIO_AF_TIM_8_9_10_11 = 3, /**< Timers 8 through 11. */ - GPIO_AF_I2C = 4, /**< I2C 1, 2, and 3. */ - GPIO_AF_SPI_1_2 = 5, /**< SPI1, SPI2/I2S2. */ - GPIO_AF_SPI3 = 6, /**< SPI3/I2S3. */ - GPIO_AF_USART_1_2_3 = 7, /**< USART 1, 2, and 3. */ - GPIO_AF_USART_4_5_6 = 8, /**< UART 4 and 5, USART 6. */ - GPIO_AF_CAN_1_2_TIM_12_13_14 = 9, /**< - * CAN 1 and 2, timers 12, 13, and 14. */ - GPIO_AF_USB_OTG_FS_HS = 10, /**< USB OTG HS and FS. */ - GPIO_AF_ETH = 11, /**< Ethernet MII and RMII. */ - GPIO_AF_FSMC_SDIO_OTG_FS = 12, /**< FSMC, SDIO, and USB OTG FS. */ - GPIO_AF_DCMI = 13, /**< DCMI. */ - GPIO_AF_EVENTOUT = 15, /**< EVENTOUT. */ -} gpio_af; - -void gpio_set_af(struct gpio_dev *dev, uint8 bit, gpio_af af); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/nvic.h b/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/nvic.h deleted file mode 100644 index dc03806..0000000 --- a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/nvic.h +++ /dev/null @@ -1,160 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/stm32f2/include/series/nvic.h - * @brief STM32F2 nested vectored interrupt controller (NVIC) header. - */ - -#ifndef _LIBMAPLE_STM32F2_NVIC_H_ -#define _LIBMAPLE_STM32F2_NVIC_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -/** - * @brief STM32F2 interrupt vector table interrupt numbers. - */ -typedef enum nvic_irq_num { - NVIC_NMI = -14, /**< Non-maskable interrupt */ - NVIC_HARDFAULT = -13, /**< Hard fault (all class of fault) */ - NVIC_MEM_MANAGE = -12, /**< Memory management */ - NVIC_BUS_FAULT = -11, /**< Bus fault: prefetch fault, memory - access fault. */ - NVIC_USAGE_FAULT = -10, /**< Usage fault: Undefined instruction - or illegal state. */ - NVIC_SVC = -5, /**< System service call via SWI - instruction */ - NVIC_DEBUG_MON = -4, /**< Debug monitor */ - NVIC_PEND_SVC = -2, /**< Pendable request for system - service */ - NVIC_SYSTICK = -1, /**< System tick timer */ - NVIC_WWDG = 0, /**< Window watchdog interrupt */ - NVIC_PVD = 1, /**< PVD through EXTI line detection */ - NVIC_TAMP_STAMP = 2, /**< Tamper and TimeStamp */ - NVIC_RTC_WKUP = 3, /**< Real-time clock wakeup */ - NVIC_FLASH = 4, /**< Flash */ - NVIC_RCC = 5, /**< Reset and clock control */ - NVIC_EXTI0 = 6, /**< EXTI line 0 */ - NVIC_EXTI1 = 7, /**< EXTI line 1 */ - NVIC_EXTI2 = 8, /**< EXTI line 2 */ - NVIC_EXTI3 = 9, /**< EXTI line 3 */ - NVIC_EXTI4 = 10, /**< EXTI line 4 */ - NVIC_DMA1_STREAM0 = 11, /**< DMA1 stream 0 */ - NVIC_DMA1_STREAM1 = 12, /**< DMA1 stream 1 */ - NVIC_DMA1_STREAM2 = 13, /**< DMA1 stream 2 */ - NVIC_DMA1_STREAM3 = 14, /**< DMA1 stream 3 */ - NVIC_DMA1_STREAM4 = 15, /**< DMA1 stream 4 */ - NVIC_DMA1_STREAM5 = 16, /**< DMA1 stream 5 */ - NVIC_DMA1_STREAM6 = 17, /**< DMA1 stream 6 */ - NVIC_ADC = 18, /**< ADC */ - NVIC_CAN1_TX = 19, /**< CAN1 TX */ - NVIC_CAN1_RX0 = 20, /**< CAN1 RX0 */ - NVIC_CAN1_RX1 = 21, /**< CAN1 RX1 */ - NVIC_CAN1_SCE = 22, /**< CAN1 SCE */ - NVIC_EXTI_9_5 = 23, /**< EXTI lines [9:5] */ - NVIC_TIMER1_BRK_TIMER9 = 24, /**< Timer 1 break and timer 9 */ - NVIC_TIMER1_UP_TIMER10 = 25, /**< Timer 1 update and timer 10 */ - NVIC_TIMER1_TRG_COM_TIMER11 = 26, /**< Timer 1 trigger and commutation and - timer 11.*/ - NVIC_TIMER1_CC = 27, /**< Timer 1 capture and compare */ - NVIC_TIMER2 = 28, /**< Timer 2 */ - NVIC_TIMER3 = 29, /**< Timer 3 */ - NVIC_TIMER4 = 30, /**< Timer 4 */ - NVIC_I2C1_EV = 31, /**< I2C1 event */ - NVIC_I2C1_ER = 32, /**< I2C2 error */ - NVIC_I2C2_EV = 33, /**< I2C2 event */ - NVIC_I2C2_ER = 34, /**< I2C2 error */ - NVIC_SPI1 = 35, /**< SPI1 */ - NVIC_SPI2 = 36, /**< SPI2 */ - NVIC_USART1 = 37, /**< USART1 */ - NVIC_USART2 = 38, /**< USART2 */ - NVIC_USART3 = 39, /**< USART3 */ - NVIC_EXTI_15_10 = 40, /**< EXTI lines [15:10] */ - NVIC_RTCALARM = 41, /**< RTC alarms A and B through EXTI */ - NVIC_OTG_FS_WKUP = 42, /**< USB on-the-go full-speed wakeup - through EXTI*/ - NVIC_TIMER8_BRK_TIMER12 = 43, /**< Timer 8 break and timer 12 */ - NVIC_TIMER8_UP_TIMER13 = 44, /**< Timer 8 update and timer 13 */ - NVIC_TIMER8_TRG_COM_TIMER14 = 45, /**< Timer 8 trigger and commutation and - timer 14 */ - NVIC_TIMER8_CC = 46, /**< Timer 8 capture and compare */ - NVIC_DMA1_STREAM7 = 47, /**< DMA1 stream 7 */ - NVIC_FSMC = 48, /**< FSMC */ - NVIC_SDIO = 49, /**< SDIO */ - NVIC_TIMER5 = 50, /**< Timer 5 */ - NVIC_SPI3 = 51, /**< SPI3 */ - NVIC_UART4 = 52, /**< UART4 */ - NVIC_UART5 = 53, /**< UART5 */ - NVIC_TIMER6_DAC = 54, /**< Timer 6 and DAC underrun */ - NVIC_TIMER7 = 55, /**< Timer 7 */ - NVIC_DMA2_STREAM0 = 56, /**< DMA2 stream 0 */ - NVIC_DMA2_STREAM1 = 57, /**< DMA2 stream 1 */ - NVIC_DMA2_STREAM2 = 58, /**< DMA2 stream 2 */ - NVIC_DMA2_STREAM3 = 59, /**< DMA2 stream 3 */ - NVIC_DMA2_STREAM4 = 60, /**< DMA2 stream 4 */ - NVIC_ETH = 61, /**< Ethernet */ - NVIC_ETH_WKUP = 62, /**< Ethernet wakeup through EXTI */ - NVIC_CAN2_TX = 63, /**< CAN2 TX */ - NVIC_CAN2_RX0 = 64, /**< CAN2 RX0 */ - NVIC_CAN2_RX1 = 65, /**< CAN2 RX1 */ - NVIC_CAN2_SCE = 66, /**< CAN2 SCE */ - NVIC_OTG_FS = 67, /**< USB on-the-go full-speed */ - NVIC_DMA2_STREAM5 = 68, /**< DMA2 stream 5 */ - NVIC_DMA2_STREAM6 = 69, /**< DMA2 stream 6 */ - NVIC_DMA2_STREAM7 = 70, /**< DMA2 stream 7 */ - NVIC_USART6 = 71, /**< USART6 */ - NVIC_I2C3_EV = 72, /**< I2C3 event */ - NVIC_I2C3_ER = 73, /**< I2C3 error */ - NVIC_OTG_HS_EP1_OUT = 74, /**< USB on-the-go high-speed - endpoint 1 OUT */ - NVIC_OTG_HS_EP1_IN = 75, /**< USB on-the-go high-speed - endpoint 1 IN */ - NVIC_OTG_HS_WKUP = 76, /**< USB on-the-go high-speed wakeup - through EXTI*/ - NVIC_OTG_HS = 77, /**< USB on-the-go high-speed */ - NVIC_DCMI = 78, /**< DCMI */ - NVIC_CRYP = 79, /**< Cryptographic processor */ - NVIC_HASH_RNG = 80, /**< Hash and random number - generation */ - - /* Fake enumerator values, for compatiblity with F1. - * TODO decide if this is actually a good idea. */ - NVIC_TIMER6 = NVIC_TIMER6_DAC, /**< For compatibility with STM32F1. */ -} nvic_irq_num; - -static inline void nvic_irq_disable_all(void) { - NVIC_BASE->ICER[0] = 0xFFFFFFFF; - NVIC_BASE->ICER[1] = 0xFFFFFFFF; - NVIC_BASE->ICER[2] = 0xFFFFFFFF; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/pwr.h b/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/pwr.h deleted file mode 100644 index 96353a4..0000000 --- a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/pwr.h +++ /dev/null @@ -1,73 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2012 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/stm32f2/include/series/pwr.h - * @author Marti Bolivar - * @brief STM32F2 Power control (PWR) support. - */ - -#ifndef _LIBMAPLE_STM32F2_PWR_H_ -#define _LIBMAPLE_STM32F2_PWR_H_ - -/* - * Additional register bits - */ - -/* Control register */ - -/** - * @brief Flash power down in stop mode bit. - * Availability: STM32F2 */ -#define PWR_CR_FPDS_BIT 9 -/** - * @brief Flash power down in stop mode. - * Availability: STM32F2 */ -#define PWR_CR_FPDS (1U << PWR_CR_FPDS_BIT) - -/* PVD level selection */ -#define PWR_CR_PLS_2_0V (0x0 << 5) -#define PWR_CR_PLS_2_1V (0x1 << 5) -#define PWR_CR_PLS_2_3V (0x2 << 5) -#define PWR_CR_PLS_2_5V (0x3 << 5) -#define PWR_CR_PLS_2_6V (0x4 << 5) -#define PWR_CR_PLS_2_7V (0x5 << 5) -#define PWR_CR_PLS_2_8V (0x6 << 5) -#define PWR_CR_PLS_2_9V (0x7 << 5) - -/* Control/Status register */ - -/** Backup regulator enable bit. */ -#define PWR_CSR_BRE_BIT 9 -/** Backup regulator ready bit. */ -#define PWR_CSR_BRR_BIT 3 - -/** Backup regulator enable. */ -#define PWR_CSR_BRE (1U << PWR_CSR_BRE_BIT) -/** Backup regulator ready. */ -#define PWR_CSR_BRR (1U << PWR_CSR_BRR_BIT) - -#endif diff --git a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/rcc.h b/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/rcc.h deleted file mode 100644 index 441a5a8..0000000 --- a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/rcc.h +++ /dev/null @@ -1,951 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/stm32f2/include/series/rcc.h - * @brief STM32F2 reset and clock control (RCC) support. - */ - -#ifndef _LIBMAPLE_STM32F2_RCC_H_ -#define _LIBMAPLE_STM32F2_RCC_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -#include - -/* - * Register map - */ - -/** STM32F2 RCC register map type */ -typedef struct rcc_reg_map { - __io uint32 CR; /**< Clock control register */ - __io uint32 PLLCFGR; /**< PLL configuration register */ - __io uint32 CFGR; /**< Clock configuration register */ - __io uint32 CIR; /**< Clock interrupt register */ - __io uint32 AHB1RSTR; /**< AHB1 peripheral reset register */ - __io uint32 AHB2RSTR; /**< AHB2 peripheral reset register */ - __io uint32 AHB3RSTR; /**< AHB3 peripheral reset register */ - const uint32 RESERVED1; /**< Reserved */ - __io uint32 APB1RSTR; /**< APB1 peripheral reset register */ - __io uint32 APB2RSTR; /**< APB2 peripheral reset register */ - const uint32 RESERVED2; /**< Reserved */ - const uint32 RESERVED3; /**< Reserved */ - __io uint32 AHB1ENR; /**< AHB1 peripheral clock enable register */ - __io uint32 AHB2ENR; /**< AHB2 peripheral clock enable register */ - __io uint32 AHB3ENR; /**< AHB3 peripheral clock enable register */ - const uint32 RESERVED4; /**< Reserved */ - __io uint32 APB1ENR; /**< APB1 peripheral clock enable register */ - __io uint32 APB2ENR; /**< APB2 peripheral clock enable register */ - const uint32 RESERVED5; /**< Reserved */ - const uint32 RESERVED6; /**< Reserved */ - __io uint32 AHB1LPENR; /**< AHB1 peripheral clock enable in - low power mode register */ - __io uint32 AHB2LPENR; /**< AHB2 peripheral clock enable in - low power mode register */ - __io uint32 AHB3LPENR; /**< AHB3 peripheral clock enable in - low power mode register */ - const uint32 RESERVED7; /**< Reserved */ - __io uint32 APB1LPENR; /**< APB1 peripheral clock enable in - low power mode register */ - __io uint32 APB2LPENR; /**< APB2 peripheral clock enable in - low power mode register */ - const uint32 RESERVED8; /**< Reserved */ - const uint32 RESERVED9; /**< Reserved */ - __io uint32 BDCR; /**< Backup domain control register */ - __io uint32 CSR; /**< Clock control and status register */ - const uint32 RESERVED10; /**< Reserved */ - const uint32 RESERVED11; /**< Reserved */ - __io uint32 SSCGR; /**< Spread spectrum clock generation - register */ - __io uint32 PLLI2SCFGR; /**< PLLI2S configuration register */ -} rcc_reg_map; - -#define RCC_BASE ((struct rcc_reg_map*)0x40023800) - -/* - * Register bit definitions - */ - -/* Clock control register */ - -#define RCC_CR_PLLI2SRDY_BIT 27 -#define RCC_CR_PLLI2SON_BIT 26 -#define RCC_CR_PLLRDY_BIT 25 -#define RCC_CR_PLLON_BIT 24 -#define RCC_CR_CSSON_BIT 19 -#define RCC_CR_HSEBYP_BIT 18 -#define RCC_CR_HSERDY_BIT 17 -#define RCC_CR_HSEON_BIT 16 -#define RCC_CR_HSIRDY_BIT 1 -#define RCC_CR_HSION_BIT 0 - -#define RCC_CR_PLLI2SRDY (1U << RCC_CR_PLLI2SRDY_BIT) -#define RCC_CR_PLLI2SON (1U << RCC_CR_PLLI2SON_BIT) -#define RCC_CR_PLLRDY (1U << RCC_CR_PLLRDY_BIT) -#define RCC_CR_PLLON (1U << RCC_CR_PLLON_BIT) -#define RCC_CR_CSSON (1U << RCC_CR_CSSON_BIT) -#define RCC_CR_HSEBYP (1U << RCC_CR_HSEBYP_BIT) -#define RCC_CR_HSERDY (1U << RCC_CR_HSERDY_BIT) -#define RCC_CR_HSEON (1U << RCC_CR_HSEON_BIT) -#define RCC_CR_HSICAL (0xFF << 8) -#define RCC_CR_HSITRIM (0x1F << 3) -#define RCC_CR_HSIRDY (1U << RCC_CR_HSIRDY_BIT) -#define RCC_CR_HSION (1U << RCC_CR_HSION_BIT) - -/* PLL configuration register */ - -#define RCC_PLLCFGR_PLLSRC_BIT 22 - -#define RCC_PLLCFGR_PLLQ (0xF << 24) -#define RCC_PLLCFGR_PLLSRC (1U << RCC_PLLCFGR_PLLSRC_BIT) -#define RCC_PLLCFGR_PLLSRC_HSI (0x0 << RCC_PLLCFGR_PLLSRC_BIT) -#define RCC_PLLCFGR_PLLSRC_HSE (0x1 << RCC_PLLCFGR_PLLSRC_BIT) -#define RCC_PLLCFGR_PLLP (0x3 << 16) -#define RCC_PLLCFGR_PLLN (0x1FF << 6) -#define RCC_PLLCFGR_PLLM 0x1F - -/* Clock configuration register */ - -#define RCC_CFGR_I2SSRC_BIT 23 - -#define RCC_CFGR_MCO2 (0x3 << 30) -#define RCC_CFGR_MCO2_SYSCLK (0x0 << 30) -#define RCC_CFGR_MCO2_PLLI2S (0x1 << 30) -#define RCC_CFGR_MCO2_HSE (0x2 << 30) -#define RCC_CFGR_MCO2_PLL (0x3 << 30) - -#define RCC_CFGR_MCO2PRE (0x7 << 27) -#define RCC_CFGR_MCO2PRE_DIV_1 (0x0 << 27) -#define RCC_CFGR_MCO2PRE_DIV_2 (0x4 << 27) -#define RCC_CFGR_MCO2PRE_DIV_3 (0x5 << 27) -#define RCC_CFGR_MCO2PRE_DIV_4 (0x6 << 27) -#define RCC_CFGR_MCO2PRE_DIV_5 (0x7 << 27) - -#define RCC_CFGR_MCO1PRE (0x7 << 24) -#define RCC_CFGR_MCO1PRE_DIV_1 (0x0 << 24) -#define RCC_CFGR_MCO1PRE_DIV_2 (0x4 << 24) -#define RCC_CFGR_MCO1PRE_DIV_3 (0x5 << 24) -#define RCC_CFGR_MCO1PRE_DIV_4 (0x6 << 24) -#define RCC_CFGR_MCO1PRE_DIV_5 (0x7 << 24) - -#define RCC_CFGR_I2SSRC (1U << RCC_CFGR_I2SSRC_BIT) -#define RCC_CFGR_I2SSRC_PLLI2S (0 << RCC_CFGR_I2SSRC_BIT) -#define RCC_CFGR_I2SSRC_I2S_CKIN (1 << RCC_CFGR_I2SSRC_BIT) - -#define RCC_CFGR_MCO1 (0x3 << 21) -#define RCC_CFGR_MCO1_HSI (0x0 << 21) -#define RCC_CFGR_MCO1_LSE (0x1 << 21) -#define RCC_CFGR_MCO1_HSE (0x2 << 21) -#define RCC_CFGR_MCO1_PLL (0x3 << 21) - -#define RCC_CFGR_RTCPRE (0x1F << 16) - -/* Skipped: all the 0b0xx values meaning "not divided" */ -#define RCC_CFGR_PPRE2 (0x7 << 13) -#define RCC_CFGR_PPRE2_AHB_DIV_2 (0x4 << 13) -#define RCC_CFGR_PPRE2_AHB_DIV_4 (0x5 << 13) -#define RCC_CFGR_PPRE2_AHB_DIV_8 (0x6 << 13) -#define RCC_CFGR_PPRE2_AHB_DIV_16 (0x7 << 13) - -/* Skipped: all the 0b0xx values meaning "not divided" */ -#define RCC_CFGR_PPRE1 (0x7 << 10) -#define RCC_CFGR_PPRE1_AHB_DIV_2 (0x4 << 10) -#define RCC_CFGR_PPRE1_AHB_DIV_4 (0x5 << 10) -#define RCC_CFGR_PPRE1_AHB_DIV_8 (0x6 << 10) -#define RCC_CFGR_PPRE1_AHB_DIV_16 (0x7 << 10) - -/* Skipped: all the 0b0xxx values meaning "not divided" */ -#define RCC_CFGR_HPRE (0xF << 4) -#define RCC_CFGR_HPRE_SYSCLK_DIV_2 (0x8 << 4) -#define RCC_CFGR_HPRE_SYSCLK_DIV_4 (0x9 << 4) -#define RCC_CFGR_HPRE_SYSCLK_DIV_8 (0xA << 4) -#define RCC_CFGR_HPRE_SYSCLK_DIV_16 (0xB << 4) -#define RCC_CFGR_HPRE_SYSCLK_DIV_64 (0xC << 4) -#define RCC_CFGR_HPRE_SYSCLK_DIV_128 (0xD << 4) -#define RCC_CFGR_HPRE_SYSCLK_DIV_256 (0xE << 4) -#define RCC_CFGR_HPRE_SYSCLK_DIV_512 (0xF << 4) - -#define RCC_CFGR_SWS (0x3 << 2) -#define RCC_CFGR_SWS_HSI (0x0 << 2) -#define RCC_CFGR_SWS_HSE (0x1 << 2) -#define RCC_CFGR_SWS_PLL (0x2 << 2) - -#define RCC_CFGR_SW 0x3 -#define RCC_CFGR_SW_HSI 0x0 -#define RCC_CFGR_SW_HSE 0x1 -#define RCC_CFGR_SW_PLL 0x2 - -/* Clock interrupt register */ - -#define RCC_CIR_CSSC_BIT 23 - -#define RCC_CIR_PLLI2SRDYC_BIT 21 -#define RCC_CIR_PLLRDYC_BIT 20 -#define RCC_CIR_HSERDYC_BIT 19 -#define RCC_CIR_HSIRDYC_BIT 18 -#define RCC_CIR_LSERDYC_BIT 17 -#define RCC_CIR_LSIRDYC_BIT 16 - -#define RCC_CIR_PLLI2SRDYIE_BIT 13 -#define RCC_CIR_PLLRDYIE_BIT 12 -#define RCC_CIR_HSERDYIE_BIT 11 -#define RCC_CIR_HSIRDYIE_BIT 10 -#define RCC_CIR_LSERDYIE_BIT 9 -#define RCC_CIR_LSIRDYIE_BIT 8 - -#define RCC_CIR_CSSF_BIT 7 - -#define RCC_CIR_PLLI2SRDYF_BIT 5 -#define RCC_CIR_PLLRDYF_BIT 4 -#define RCC_CIR_HSERDYF_BIT 3 -#define RCC_CIR_HSIRDYF_BIT 2 -#define RCC_CIR_LSERDYF_BIT 1 -#define RCC_CIR_LSIRDYF_BIT 0 - -#define RCC_CIR_CSSC (1U << RCC_CIR_CSSC_BIT) - -#define RCC_CIR_PLLI2SRDYC (1U << RCC_CIR_PLLI2SRDYC_BIT) -#define RCC_CIR_PLLRDYC (1U << RCC_CIR_PLLRDYC_BIT) -#define RCC_CIR_HSERDYC (1U << RCC_CIR_HSERDYC_BIT) -#define RCC_CIR_HSIRDYC (1U << RCC_CIR_HSIRDYC_BIT) -#define RCC_CIR_LSERDYC (1U << RCC_CIR_LSERDYC_BIT) -#define RCC_CIR_LSIRDYC (1U << RCC_CIR_LSIRDYC_BIT) - -#define RCC_CIR_PLLI2SRDYIE (1U << RCC_CIR_PLLI2SRDYIE_BIT) -#define RCC_CIR_PLLRDYIE (1U << RCC_CIR_PLLRDYIE_BIT) -#define RCC_CIR_HSERDYIE (1U << RCC_CIR_HSERDYIE_BIT) -#define RCC_CIR_HSIRDYIE (1U << RCC_CIR_HSIRDYIE_BIT) -#define RCC_CIR_LSERDYIE (1U << RCC_CIR_LSERDYIE_BIT) -#define RCC_CIR_LSIRDYIE (1U << RCC_CIR_LSIRDYIE_BIT) - -#define RCC_CIR_CSSF (1U << RCC_CIR_CSSF_BIT) - -#define RCC_CIR_PLLI2SRDYF (1U << RCC_CIR_PLLI2SRDYF_BIT) -#define RCC_CIR_PLLRDYF (1U << RCC_CIR_PLLRDYF_BIT) -#define RCC_CIR_HSERDYF (1U << RCC_CIR_HSERDYF_BIT) -#define RCC_CIR_HSIRDYF (1U << RCC_CIR_HSIRDYF_BIT) -#define RCC_CIR_LSERDYF (1U << RCC_CIR_LSERDYF_BIT) -#define RCC_CIR_LSIRDYF (1U << RCC_CIR_LSIRDYF_BIT) - -/* AHB1 peripheral reset register */ - -#define RCC_AHB1RSTR_OTGHSRST_BIT 29 -#define RCC_AHB1RSTR_ETHMACRST_BIT 25 -#define RCC_AHB1RSTR_DMA2RST_BIT 22 -#define RCC_AHB1RSTR_DMA1RST_BIT 21 -#define RCC_AHB1RSTR_CRCRST_BIT 12 -#define RCC_AHB1RSTR_GPIOIRST_BIT 8 -#define RCC_AHB1RSTR_GPIOHRST_BIT 7 -#define RCC_AHB1RSTR_GPIOGRST_BIT 6 -#define RCC_AHB1RSTR_GPIOFRST_BIT 5 -#define RCC_AHB1RSTR_GPIOERST_BIT 4 -#define RCC_AHB1RSTR_GPIODRST_BIT 3 -#define RCC_AHB1RSTR_GPIOCRST_BIT 2 -#define RCC_AHB1RSTR_GPIOBRST_BIT 1 -#define RCC_AHB1RSTR_GPIOARST_BIT 0 - -#define RCC_AHB1RSTR_OTGHSRST (1U << RCC_AHB1RSTR_OTGHSRST_BIT) -#define RCC_AHB1RSTR_ETHMACRST (1U << RCC_AHB1RSTR_ETHMACRST_BIT) -#define RCC_AHB1RSTR_DMA2RST (1U << RCC_AHB1RSTR_DMA2RST_BIT) -#define RCC_AHB1RSTR_DMA1RST (1U << RCC_AHB1RSTR_DMA1RST_BIT) -#define RCC_AHB1RSTR_CRCRST (1U << RCC_AHB1RSTR_CRCRST_BIT) -#define RCC_AHB1RSTR_GPIOIRST (1U << RCC_AHB1RSTR_GPIOIRST_BIT) -#define RCC_AHB1RSTR_GPIOHRST (1U << RCC_AHB1RSTR_GPIOHRST_BIT) -#define RCC_AHB1RSTR_GPIOGRST (1U << RCC_AHB1RSTR_GPIOGRST_BIT) -#define RCC_AHB1RSTR_GPIOFRST (1U << RCC_AHB1RSTR_GPIOFRST_BIT) -#define RCC_AHB1RSTR_GPIOERST (1U << RCC_AHB1RSTR_GPIOERST_BIT) -#define RCC_AHB1RSTR_GPIODRST (1U << RCC_AHB1RSTR_GPIODRST_BIT) -#define RCC_AHB1RSTR_GPIOCRST (1U << RCC_AHB1RSTR_GPIOCRST_BIT) -#define RCC_AHB1RSTR_GPIOBRST (1U << RCC_AHB1RSTR_GPIOBRST_BIT) -#define RCC_AHB1RSTR_GPIOARST (1U << RCC_AHB1RSTR_GPIOARST_BIT) - -/* AHB2 peripheral reset register */ - -#define RCC_AHB2RSTR_OTGFSRST_BIT 7 -#define RCC_AHB2RSTR_RNGRST_BIT 6 -#define RCC_AHB2RSTR_HASHRST_BIT 5 -#define RCC_AHB2RSTR_CRYPRST_BIT 4 -#define RCC_AHB2RSTR_DCMIRST_BIT 0 - -#define RCC_AHB2RSTR_OTGFSRST (1U << RCC_AHB2RSTR_OTGFSRST_BIT) -#define RCC_AHB2RSTR_RNGRST (1U << RCC_AHB2RSTR_RNGRST_BIT) -#define RCC_AHB2RSTR_HASHRST (1U << RCC_AHB2RSTR_HASHRST_BIT) -#define RCC_AHB2RSTR_CRYPRST (1U << RCC_AHB2RSTR_CRYPRST_BIT) -#define RCC_AHB2RSTR_DCMIRST (1U << RCC_AHB2RSTR_DCMIRST_BIT) - -/* AHB3 peripheral reset register */ - -#define RCC_AHB3RSTR_FSMCRST_BIT 0 - -#define RCC_AHB3RSTR_FSMCRST (1U << RCC_AHB3RSTR_FSMCRST_BIT) - -/* APB1 peripheral reset register */ - -#define RCC_APB1RSTR_DACRST_BIT 29 -#define RCC_APB1RSTR_PWRRST_BIT 28 -#define RCC_APB1RSTR_CAN2RST_BIT 26 -#define RCC_APB1RSTR_CAN1RST_BIT 25 -#define RCC_APB1RSTR_I2C3RST_BIT 23 -#define RCC_APB1RSTR_I2C2RST_BIT 22 -#define RCC_APB1RSTR_I2C1RST_BIT 21 -#define RCC_APB1RSTR_UART5RST_BIT 20 -#define RCC_APB1RSTR_UART4RST_BIT 19 -#define RCC_APB1RSTR_UART3RST_BIT 18 -#define RCC_APB1RSTR_UART2RST_BIT 17 -#define RCC_APB1RSTR_SPI3RST_BIT 15 -#define RCC_APB1RSTR_SPI2RST_BIT 14 -#define RCC_APB1RSTR_WWDGRST_BIT 11 -#define RCC_APB1RSTR_TIM14RST_BIT 8 -#define RCC_APB1RSTR_TIM13RST_BIT 7 -#define RCC_APB1RSTR_TIM12RST_BIT 6 -#define RCC_APB1RSTR_TIM7RST_BIT 5 -#define RCC_APB1RSTR_TIM6RST_BIT 4 -#define RCC_APB1RSTR_TIM5RST_BIT 3 -#define RCC_APB1RSTR_TIM4RST_BIT 2 -#define RCC_APB1RSTR_TIM3RST_BIT 1 -#define RCC_APB1RSTR_TIM2RST_BIT 0 - -#define RCC_APB1RSTR_DACRST (1U << RCC_APB1RSTR_DACRST_BIT) -#define RCC_APB1RSTR_PWRRST (1U << RCC_APB1RSTR_PWRRST_BIT) -#define RCC_APB1RSTR_CAN2RST (1U << RCC_APB1RSTR_CAN2RST_BIT) -#define RCC_APB1RSTR_CAN1RST (1U << RCC_APB1RSTR_CAN1RST_BIT) -#define RCC_APB1RSTR_I2C3RST (1U << RCC_APB1RSTR_I2C3RST_BIT) -#define RCC_APB1RSTR_I2C2RST (1U << RCC_APB1RSTR_I2C2RST_BIT) -#define RCC_APB1RSTR_I2C1RST (1U << RCC_APB1RSTR_I2C1RST_BIT) -#define RCC_APB1RSTR_UART5RST (1U << RCC_APB1RSTR_UART5RST_BIT) -#define RCC_APB1RSTR_UART4RST (1U << RCC_APB1RSTR_UART4RST_BIT) -#define RCC_APB1RSTR_UART3RST (1U << RCC_APB1RSTR_UART3RST_BIT) -#define RCC_APB1RSTR_UART2RST (1U << RCC_APB1RSTR_UART2RST_BIT) -#define RCC_APB1RSTR_SPI3RST (1U << RCC_APB1RSTR_SPI3RST_BIT) -#define RCC_APB1RSTR_SPI2RST (1U << RCC_APB1RSTR_SPI2RST_BIT) -#define RCC_APB1RSTR_WWDGRST (1U << RCC_APB1RSTR_WWDGRST_BIT) -#define RCC_APB1RSTR_TIM14RST (1U << RCC_APB1RSTR_TIM14RST_BIT) -#define RCC_APB1RSTR_TIM13RST (1U << RCC_APB1RSTR_TIM13RST_BIT) -#define RCC_APB1RSTR_TIM12RST (1U << RCC_APB1RSTR_TIM12RST_BIT) -#define RCC_APB1RSTR_TIM7RST (1U << RCC_APB1RSTR_TIM7RST_BIT) -#define RCC_APB1RSTR_TIM6RST (1U << RCC_APB1RSTR_TIM6RST_BIT) -#define RCC_APB1RSTR_TIM5RST (1U << RCC_APB1RSTR_TIM5RST_BIT) -#define RCC_APB1RSTR_TIM4RST (1U << RCC_APB1RSTR_TIM4RST_BIT) -#define RCC_APB1RSTR_TIM3RST (1U << RCC_APB1RSTR_TIM3RST_BIT) -#define RCC_APB1RSTR_TIM2RST (1U << RCC_APB1RSTR_TIM2RST_BIT) - -/* APB2 peripheral reset register */ - -#define RCC_APB2RSTR_TIM11RST_BIT 18 -#define RCC_APB2RSTR_TIM10RST_BIT 17 -#define RCC_APB2RSTR_TIM9RST_BIT 16 -#define RCC_APB2RSTR_SYSCFGRST_BIT 14 -#define RCC_APB2RSTR_SPI1RST_BIT 12 -#define RCC_APB2RSTR_SDIORST_BIT 11 -#define RCC_APB2RSTR_ADCRST_BIT 8 -#define RCC_APB2RSTR_USART6RST_BIT 5 -#define RCC_APB2RSTR_USART1RST_BIT 4 -#define RCC_APB2RSTR_TIM8RST_BIT 1 -#define RCC_APB2RSTR_TIM1RST_BIT 0 - -#define RCC_APB2RSTR_TIM11RST (1U << RCC_APB2RSTR_TIM11RST_BIT) -#define RCC_APB2RSTR_TIM10RST (1U << RCC_APB2RSTR_TIM10RST_BIT) -#define RCC_APB2RSTR_TIM9RST (1U << RCC_APB2RSTR_TIM9RST_BIT) -#define RCC_APB2RSTR_SYSCFGRST (1U << RCC_APB2RSTR_SYSCFGRST_BIT) -#define RCC_APB2RSTR_SPI1RST (1U << RCC_APB2RSTR_SPI1RST_BIT) -#define RCC_APB2RSTR_SDIORST (1U << RCC_APB2RSTR_SDIORST_BIT) -#define RCC_APB2RSTR_ADCRST (1U << RCC_APB2RSTR_ADCRST_BIT) -#define RCC_APB2RSTR_USART6RST (1U << RCC_APB2RSTR_USART6RST_BIT) -#define RCC_APB2RSTR_USART1RST (1U << RCC_APB2RSTR_USART1RST_BIT) -#define RCC_APB2RSTR_TIM8RST (1U << RCC_APB2RSTR_TIM8RST_BIT) -#define RCC_APB2RSTR_TIM1RST (1U << RCC_APB2RSTR_TIM1RST_BIT) - -/* AHB1 peripheral clock enable register */ - -#define RCC_AHB1ENR_OTGHSULPIEN_BIT 30 -#define RCC_AHB1ENR_OTGHSEN_BIT 29 -#define RCC_AHB1ENR_ETHMACPTPEN_BIT 28 -#define RCC_AHB1ENR_ETHMACRXEN_BIT 27 -#define RCC_AHB1ENR_ETHMACTXEN_BIT 26 -#define RCC_AHB1ENR_ETHMACEN_BIT 25 -#define RCC_AHB1ENR_DMA2EN_BIT 22 -#define RCC_AHB1ENR_DMA1EN_BIT 21 -#define RCC_AHB1ENR_BKPSRAMEN_BIT 18 -#define RCC_AHB1ENR_CRCEN_BIT 12 -#define RCC_AHB1ENR_GPIOIEN_BIT 8 -#define RCC_AHB1ENR_GPIOHEN_BIT 7 -#define RCC_AHB1ENR_GPIOGEN_BIT 6 -#define RCC_AHB1ENR_GPIOFEN_BIT 5 -#define RCC_AHB1ENR_GPIOEEN_BIT 4 -#define RCC_AHB1ENR_GPIODEN_BIT 3 -#define RCC_AHB1ENR_GPIOCEN_BIT 2 -#define RCC_AHB1ENR_GPIOBEN_BIT 1 -#define RCC_AHB1ENR_GPIOAEN_BIT 0 - -#define RCC_AHB1ENR_OTGHSULPIEN (1U << RCC_AHB1ENR_OTGHSULPIEN_BIT) -#define RCC_AHB1ENR_OTGHSEN (1U << RCC_AHB1ENR_OTGHSEN_BIT) -#define RCC_AHB1ENR_ETHMACPTPEN (1U << RCC_AHB1ENR_ETHMACPTPEN_BIT) -#define RCC_AHB1ENR_ETHMACRXEN (1U << RCC_AHB1ENR_ETHMACRXEN_BIT) -#define RCC_AHB1ENR_ETHMACTXEN (1U << RCC_AHB1ENR_ETHMACTXEN_BIT) -#define RCC_AHB1ENR_ETHMACEN (1U << RCC_AHB1ENR_ETHMACEN_BIT) -#define RCC_AHB1ENR_DMA2EN (1U << RCC_AHB1ENR_DMA2EN_BIT) -#define RCC_AHB1ENR_DMA1EN (1U << RCC_AHB1ENR_DMA1EN_BIT) -#define RCC_AHB1ENR_BKPSRAMEN (1U << RCC_AHB1ENR_BKPSRAMEN_BIT) -#define RCC_AHB1ENR_CRCEN (1U << RCC_AHB1ENR_CRCEN_BIT) -#define RCC_AHB1ENR_GPIOIEN (1U << RCC_AHB1ENR_GPIOIEN_BIT) -#define RCC_AHB1ENR_GPIOHEN (1U << RCC_AHB1ENR_GPIOHEN_BIT) -#define RCC_AHB1ENR_GPIOGEN (1U << RCC_AHB1ENR_GPIOGEN_BIT) -#define RCC_AHB1ENR_GPIOFEN (1U << RCC_AHB1ENR_GPIOFEN_BIT) -#define RCC_AHB1ENR_GPIOEEN (1U << RCC_AHB1ENR_GPIOEEN_BIT) -#define RCC_AHB1ENR_GPIODEN (1U << RCC_AHB1ENR_GPIODEN_BIT) -#define RCC_AHB1ENR_GPIOCEN (1U << RCC_AHB1ENR_GPIOCEN_BIT) -#define RCC_AHB1ENR_GPIOBEN (1U << RCC_AHB1ENR_GPIOBEN_BIT) -#define RCC_AHB1ENR_GPIOAEN (1U << RCC_AHB1ENR_GPIOAEN_BIT) - -/* AHB2 peripheral clock enable register */ - -#define RCC_AHB2ENR_OTGFSEN_BIT 7 -#define RCC_AHB2ENR_RNGEN_BIT 6 -#define RCC_AHB2ENR_HASHEN_BIT 5 -#define RCC_AHB2ENR_CRYPEN_BIT 4 -#define RCC_AHB2ENR_DCMIEN_BIT 0 - -#define RCC_AHB2ENR_OTGFSEN (1U << RCC_AHB2ENR_OTGFSEN_BIT) -#define RCC_AHB2ENR_RNGEN (1U << RCC_AHB2ENR_RNGEN_BIT) -#define RCC_AHB2ENR_HASHEN (1U << RCC_AHB2ENR_HASHEN_BIT) -#define RCC_AHB2ENR_CRYPEN (1U << RCC_AHB2ENR_CRYPEN_BIT) -#define RCC_AHB2ENR_DCMIEN (1U << RCC_AHB2ENR_DCMIEN_BIT) - -/* AHB3 peripheral clock enable register */ - -#define RCC_AHB3ENR_FSMCEN_BIT 0 - -#define RCC_AHB3ENR_FSMCEN (1U << RCC_AHB3ENR_FSMCEN_BIT) - -/* APB1 peripheral clock enable register */ - -#define RCC_APB1ENR_DACEN_BIT 29 -#define RCC_APB1ENR_PWREN_BIT 28 -#define RCC_APB1ENR_CAN2EN_BIT 26 -#define RCC_APB1ENR_CAN1EN_BIT 25 -#define RCC_APB1ENR_I2C3EN_BIT 23 -#define RCC_APB1ENR_I2C2EN_BIT 22 -#define RCC_APB1ENR_I2C1EN_BIT 21 -#define RCC_APB1ENR_UART5EN_BIT 20 -#define RCC_APB1ENR_UART4EN_BIT 19 -#define RCC_APB1ENR_USART3EN_BIT 18 -#define RCC_APB1ENR_USART2EN_BIT 17 -#define RCC_APB1ENR_SPI3EN_BIT 15 -#define RCC_APB1ENR_SPI2EN_BIT 14 -#define RCC_APB1ENR_WWDGEN_BIT 11 -#define RCC_APB1ENR_TIM14EN_BIT 8 -#define RCC_APB1ENR_TIM13EN_BIT 7 -#define RCC_APB1ENR_TIM12EN_BIT 6 -#define RCC_APB1ENR_TIM7EN_BIT 5 -#define RCC_APB1ENR_TIM6EN_BIT 4 -#define RCC_APB1ENR_TIM5EN_BIT 3 -#define RCC_APB1ENR_TIM4EN_BIT 2 -#define RCC_APB1ENR_TIM3EN_BIT 1 -#define RCC_APB1ENR_TIM2EN_BIT 0 - -#define RCC_APB1ENR_DACEN (1U << RCC_APB1ENR_DACEN_BIT) -#define RCC_APB1ENR_PWREN (1U << RCC_APB1ENR_PWREN_BIT) -#define RCC_APB1ENR_CAN2EN (1U << RCC_APB1ENR_CAN2EN_BIT) -#define RCC_APB1ENR_CAN1EN (1U << RCC_APB1ENR_CAN1EN_BIT) -#define RCC_APB1ENR_I2C3EN (1U << RCC_APB1ENR_I2C3EN_BIT) -#define RCC_APB1ENR_I2C2EN (1U << RCC_APB1ENR_I2C2EN_BIT) -#define RCC_APB1ENR_I2C1EN (1U << RCC_APB1ENR_I2C1EN_BIT) -#define RCC_APB1ENR_UART5EN (1U << RCC_APB1ENR_UART5EN_BIT) -#define RCC_APB1ENR_UART4EN (1U << RCC_APB1ENR_UART4EN_BIT) -#define RCC_APB1ENR_USART3EN (1U << RCC_APB1ENR_USART3EN_BIT) -#define RCC_APB1ENR_USART2EN (1U << RCC_APB1ENR_USART2EN_BIT) -#define RCC_APB1ENR_SPI3EN (1U << RCC_APB1ENR_SPI3EN_BIT) -#define RCC_APB1ENR_SPI2EN (1U << RCC_APB1ENR_SPI2EN_BIT) -#define RCC_APB1ENR_WWDGEN (1U << RCC_APB1ENR_WWDGEN_BIT) -#define RCC_APB1ENR_TIM14EN (1U << RCC_APB1ENR_TIM14EN_BIT) -#define RCC_APB1ENR_TIM13EN (1U << RCC_APB1ENR_TIM13EN_BIT) -#define RCC_APB1ENR_TIM12EN (1U << RCC_APB1ENR_TIM12EN_BIT) -#define RCC_APB1ENR_TIM7EN (1U << RCC_APB1ENR_TIM7EN_BIT) -#define RCC_APB1ENR_TIM6EN (1U << RCC_APB1ENR_TIM6EN_BIT) -#define RCC_APB1ENR_TIM5EN (1U << RCC_APB1ENR_TIM5EN_BIT) -#define RCC_APB1ENR_TIM4EN (1U << RCC_APB1ENR_TIM4EN_BIT) -#define RCC_APB1ENR_TIM3EN (1U << RCC_APB1ENR_TIM3EN_BIT) -#define RCC_APB1ENR_TIM2EN (1U << RCC_APB1ENR_TIM2EN_BIT) - -/* APB2 peripheral clock enable register */ - -#define RCC_APB2ENR_TIM11EN_BIT 18 -#define RCC_APB2ENR_TIM10EN_BIT 17 -#define RCC_APB2ENR_TIM9EN_BIT 16 -#define RCC_APB2ENR_SYSCFGEN_BIT 14 -#define RCC_APB2ENR_SPI1EN_BIT 12 -#define RCC_APB2ENR_SDIOEN_BIT 11 -#define RCC_APB2ENR_ADC3EN_BIT 10 -#define RCC_APB2ENR_ADC2EN_BIT 9 -#define RCC_APB2ENR_ADC1EN_BIT 8 -#define RCC_APB2ENR_USART6EN_BIT 5 -#define RCC_APB2ENR_USART1EN_BIT 4 -#define RCC_APB2ENR_TIM8EN_BIT 1 -#define RCC_APB2ENR_TIM1EN_BIT 0 - -#define RCC_APB2ENR_TIM11EN (1U << RCC_APB2ENR_TIM11EN_BIT) -#define RCC_APB2ENR_TIM10EN (1U << RCC_APB2ENR_TIM10EN_BIT) -#define RCC_APB2ENR_TIM9EN (1U << RCC_APB2ENR_TIM9EN_BIT) -#define RCC_APB2ENR_SYSCFGEN (1U << RCC_APB2ENR_SYSCFGEN_BIT) -#define RCC_APB2ENR_SPI1EN (1U << RCC_APB2ENR_SPI1EN_BIT) -#define RCC_APB2ENR_SDIOEN (1U << RCC_APB2ENR_SDIOEN_BIT) -#define RCC_APB2ENR_ADC3EN (1U << RCC_APB2ENR_ADC3EN_BIT) -#define RCC_APB2ENR_ADC2EN (1U << RCC_APB2ENR_ADC2EN_BIT) -#define RCC_APB2ENR_ADC1EN (1U << RCC_APB2ENR_ADC1EN_BIT) -#define RCC_APB2ENR_USART6EN (1U << RCC_APB2ENR_USART6EN_BIT) -#define RCC_APB2ENR_USART1EN (1U << RCC_APB2ENR_USART1EN_BIT) -#define RCC_APB2ENR_TIM8EN (1U << RCC_APB2ENR_TIM8EN_BIT) -#define RCC_APB2ENR_TIM1EN (1U << RCC_APB2ENR_TIM1EN_BIT) - -/* AHB1 peripheral clock enable in low power mode register */ - -#define RCC_AHB1LPENR_OTGHSULPILPEN_BIT 30 -#define RCC_AHB1LPENR_OTGHSLPEN_BIT 29 -#define RCC_AHB1LPENR_ETHMACPTPLPEN_BIT 28 -#define RCC_AHB1LPENR_ETHMACRXLPEN_BIT 27 -#define RCC_AHB1LPENR_ETHMACTXLPEN_BIT 26 -#define RCC_AHB1LPENR_ETHMACLPEN_BIT 25 -#define RCC_AHB1LPENR_DMA2LPEN_BIT 22 -#define RCC_AHB1LPENR_DMA1LPEN_BIT 21 -#define RCC_AHB1LPENR_BKPSRAMLPEN_BIT 18 -#define RCC_AHB1LPENR_SRAM2LPEN_BIT 17 -#define RCC_AHB1LPENR_SRAM1LPEN_BIT 16 -#define RCC_AHB1LPENR_FLITFLPEN_BIT 15 -#define RCC_AHB1LPENR_CRCLPEN_BIT 12 -#define RCC_AHB1LPENR_GPIOILPEN_BIT 8 -#define RCC_AHB1LPENR_GPIOGLPEN_BIT 6 -#define RCC_AHB1LPENR_GPIOFLPEN_BIT 5 -#define RCC_AHB1LPENR_GPIOELPEN_BIT 4 -#define RCC_AHB1LPENR_GPIODLPEN_BIT 3 -#define RCC_AHB1LPENR_GPIOCLPEN_BIT 2 -#define RCC_AHB1LPENR_GPIOBLPEN_BIT 1 -#define RCC_AHB1LPENR_GPIOALPEN_BIT 0 - -#define RCC_AHB1LPENR_OTGHSULPILPEN (1U << RCC_AHB1LPENR_OTGHSULPILPEN_BIT) -#define RCC_AHB1LPENR_OTGHSLPEN (1U << RCC_AHB1LPENR_OTGHSLPEN_BIT) -#define RCC_AHB1LPENR_ETHMACPTPLPEN (1U << RCC_AHB1LPENR_ETHMACPTPLPEN_BIT) -#define RCC_AHB1LPENR_ETHMACRXLPEN (1U << RCC_AHB1LPENR_ETHMACRXLPEN_BIT) -#define RCC_AHB1LPENR_ETHMACTXLPEN (1U << RCC_AHB1LPENR_ETHMACTXLPEN_BIT) -#define RCC_AHB1LPENR_ETHMACLPEN (1U << RCC_AHB1LPENR_ETHMACLPEN_BIT) -#define RCC_AHB1LPENR_DMA2LPEN (1U << RCC_AHB1LPENR_DMA2LPEN_BIT) -#define RCC_AHB1LPENR_DMA1LPEN (1U << RCC_AHB1LPENR_DMA1LPEN_BIT) -#define RCC_AHB1LPENR_BKPSRAMLPEN (1U << RCC_AHB1LPENR_BKPSRAMLPEN_BIT) -#define RCC_AHB1LPENR_SRAM2LPEN (1U << RCC_AHB1LPENR_SRAM2LPEN_BIT) -#define RCC_AHB1LPENR_SRAM1LPEN (1U << RCC_AHB1LPENR_SRAM1LPEN_BIT) -#define RCC_AHB1LPENR_FLITFLPEN (1U << RCC_AHB1LPENR_FLITFLPEN_BIT) -#define RCC_AHB1LPENR_CRCLPEN (1U << RCC_AHB1LPENR_CRCLPEN_BIT) -#define RCC_AHB1LPENR_GPIOILPEN (1U << RCC_AHB1LPENR_GPIOILPEN_BIT) -#define RCC_AHB1LPENR_GPIOGLPEN (1U << RCC_AHB1LPENR_GPIOGLPEN_BIT) -#define RCC_AHB1LPENR_GPIOFLPEN (1U << RCC_AHB1LPENR_GPIOFLPEN_BIT) -#define RCC_AHB1LPENR_GPIOELPEN (1U << RCC_AHB1LPENR_GPIOELPEN_BIT) -#define RCC_AHB1LPENR_GPIODLPEN (1U << RCC_AHB1LPENR_GPIODLPEN_BIT) -#define RCC_AHB1LPENR_GPIOCLPEN (1U << RCC_AHB1LPENR_GPIOCLPEN_BIT) -#define RCC_AHB1LPENR_GPIOBLPEN (1U << RCC_AHB1LPENR_GPIOBLPEN_BIT) -#define RCC_AHB1LPENR_GPIOALPEN (1U << RCC_AHB1LPENR_GPIOALPEN_BIT) - -/* AHB2 peripheral clock enable in low power mode register */ - -#define RCC_AHB2LPENR_OTGFSLPEN_BIT 7 -#define RCC_AHB2LPENR_RNGLPEN_BIT 6 -#define RCC_AHB2LPENR_HASHLPEN_BIT 5 -#define RCC_AHB2LPENR_CRYPLPEN_BIT 4 -#define RCC_AHB2LPENR_DCMILPEN_BIT 0 - -#define RCC_AHB2LPENR_OTGFSLPEN (1U << RCC_AHB2LPENR_OTGFSLPEN_BIT) -#define RCC_AHB2LPENR_RNGLPEN (1U << RCC_AHB2LPENR_RNGLPEN_BIT) -#define RCC_AHB2LPENR_HASHLPEN (1U << RCC_AHB2LPENR_HASHLPEN_BIT) -#define RCC_AHB2LPENR_CRYPLPEN (1U << RCC_AHB2LPENR_CRYPLPEN_BIT) -#define RCC_AHB2LPENR_DCMILPEN (1U << RCC_AHB2LPENR_DCMILPEN_BIT) - -/* AHB3 peripheral clock enable in low power mode register */ - -#define RCC_AHB3LPENR_FSMCLPEN_BIT 0 - -#define RCC_AHB3LPENR_FSMCLPEN (1U << RCC_AHB3LPENR_FSMCLPEN_BIT) - -/* APB1 peripheral clock enable in low power mode register */ - -#define RCC_APB1LPENR_DACLPEN_BIT 29 -#define RCC_APB1LPENR_PWRLPEN_BIT 28 -#define RCC_APB1LPENR_CAN2LPEN_BIT 26 -#define RCC_APB1LPENR_CAN1LPEN_BIT 25 -#define RCC_APB1LPENR_I2C3LPEN_BIT 23 -#define RCC_APB1LPENR_I2C2LPEN_BIT 22 -#define RCC_APB1LPENR_I2C1LPEN_BIT 21 -#define RCC_APB1LPENR_UART5LPEN_BIT 20 -#define RCC_APB1LPENR_UART4LPEN_BIT 19 -#define RCC_APB1LPENR_USART3LPEN_BIT 18 -#define RCC_APB1LPENR_USART2LPEN_BIT 17 -#define RCC_APB1LPENR_SPI3LPEN_BIT 15 -#define RCC_APB1LPENR_SPI2LPEN_BIT 14 -#define RCC_APB1LPENR_WWDGLPEN_BIT 11 -#define RCC_APB1LPENR_TIM14LPEN_BIT 8 -#define RCC_APB1LPENR_TIM13LPEN_BIT 7 -#define RCC_APB1LPENR_TIM12LPEN_BIT 6 -#define RCC_APB1LPENR_TIM7LPEN_BIT 5 -#define RCC_APB1LPENR_TIM6LPEN_BIT 4 -#define RCC_APB1LPENR_TIM5LPEN_BIT 3 -#define RCC_APB1LPENR_TIM4LPEN_BIT 2 -#define RCC_APB1LPENR_TIM3LPEN_BIT 1 -#define RCC_APB1LPENR_TIM2LPEN_BIT 0 - -#define RCC_APB1LPENR_DACLPEN (1U << RCC_APB1LPENR_DACLPEN_BIT) -#define RCC_APB1LPENR_PWRLPEN (1U << RCC_APB1LPENR_PWRLPEN_BIT) -#define RCC_APB1LPENR_CAN2LPEN (1U << RCC_APB1LPENR_CAN2LPEN_BIT) -#define RCC_APB1LPENR_CAN1LPEN (1U << RCC_APB1LPENR_CAN1LPEN_BIT) -#define RCC_APB1LPENR_I2C3LPEN (1U << RCC_APB1LPENR_I2C3LPEN_BIT) -#define RCC_APB1LPENR_I2C2LPEN (1U << RCC_APB1LPENR_I2C2LPEN_BIT) -#define RCC_APB1LPENR_I2C1LPEN (1U << RCC_APB1LPENR_I2C1LPEN_BIT) -#define RCC_APB1LPENR_UART5LPEN (1U << RCC_APB1LPENR_UART5LPEN_BIT) -#define RCC_APB1LPENR_UART4LPEN (1U << RCC_APB1LPENR_UART4LPEN_BIT) -#define RCC_APB1LPENR_USART3LPEN (1U << RCC_APB1LPENR_USART3LPEN_BIT) -#define RCC_APB1LPENR_USART2LPEN (1U << RCC_APB1LPENR_USART2LPEN_BIT) -#define RCC_APB1LPENR_SPI3LPEN (1U << RCC_APB1LPENR_SPI3LPEN_BIT) -#define RCC_APB1LPENR_SPI2LPEN (1U << RCC_APB1LPENR_SPI2LPEN_BIT) -#define RCC_APB1LPENR_WWDGLPEN (1U << RCC_APB1LPENR_WWDGLPEN_BIT) -#define RCC_APB1LPENR_TIM14LPEN (1U << RCC_APB1LPENR_TIM14LPEN_BIT) -#define RCC_APB1LPENR_TIM13LPEN (1U << RCC_APB1LPENR_TIM13LPEN_BIT) -#define RCC_APB1LPENR_TIM12LPEN (1U << RCC_APB1LPENR_TIM12LPEN_BIT) -#define RCC_APB1LPENR_TIM7LPEN (1U << RCC_APB1LPENR_TIM7LPEN_BIT) -#define RCC_APB1LPENR_TIM6LPEN (1U << RCC_APB1LPENR_TIM6LPEN_BIT) -#define RCC_APB1LPENR_TIM5LPEN (1U << RCC_APB1LPENR_TIM5LPEN_BIT) -#define RCC_APB1LPENR_TIM4LPEN (1U << RCC_APB1LPENR_TIM4LPEN_BIT) -#define RCC_APB1LPENR_TIM3LPEN (1U << RCC_APB1LPENR_TIM3LPEN_BIT) -#define RCC_APB1LPENR_TIM2LPEN (1U << RCC_APB1LPENR_TIM2LPEN_BIT) - -/* APB2 peripheral clock enable in low power mode register */ - -#define RCC_APB2LPENR_TIM11LPEN_BIT 18 -#define RCC_APB2LPENR_TIM10LPEN_BIT 17 -#define RCC_APB2LPENR_TIM9LPEN_BIT 16 -#define RCC_APB2LPENR_SYSCFGLPEN_BIT 14 -#define RCC_APB2LPENR_SPI1LPEN_BIT 12 -#define RCC_APB2LPENR_SDIOLPEN_BIT 11 -#define RCC_APB2LPENR_ADC3LPEN_BIT 10 -#define RCC_APB2LPENR_ADC2LPEN_BIT 9 -#define RCC_APB2LPENR_ADC1LPEN_BIT 8 -#define RCC_APB2LPENR_USART6LPEN_BIT 5 -#define RCC_APB2LPENR_USART1LPEN_BIT 4 -#define RCC_APB2LPENR_TIM8LPEN_BIT 1 -#define RCC_APB2LPENR_TIM1LPEN_BIT 0 - -#define RCC_APB2LPENR_TIM11LPEN (1U << RCC_APB2LPENR_TIM11LPEN_BIT) -#define RCC_APB2LPENR_TIM10LPEN (1U << RCC_APB2LPENR_TIM10LPEN_BIT) -#define RCC_APB2LPENR_TIM9LPEN (1U << RCC_APB2LPENR_TIM9LPEN_BIT) -#define RCC_APB2LPENR_SYSCFGLPEN (1U << RCC_APB2LPENR_SYSCFGLPEN_BIT) -#define RCC_APB2LPENR_SPI1LPEN (1U << RCC_APB2LPENR_SPI1LPEN_BIT) -#define RCC_APB2LPENR_SDIOLPEN (1U << RCC_APB2LPENR_SDIOLPEN_BIT) -#define RCC_APB2LPENR_ADC3LPEN (1U << RCC_APB2LPENR_ADC3LPEN_BIT) -#define RCC_APB2LPENR_ADC2LPEN (1U << RCC_APB2LPENR_ADC2LPEN_BIT) -#define RCC_APB2LPENR_ADC1LPEN (1U << RCC_APB2LPENR_ADC1LPEN_BIT) -#define RCC_APB2LPENR_USART6LPEN (1U << RCC_APB2LPENR_USART6LPEN_BIT) -#define RCC_APB2LPENR_USART1LPEN (1U << RCC_APB2LPENR_USART1LPEN_BIT) -#define RCC_APB2LPENR_TIM8LPEN (1U << RCC_APB2LPENR_TIM8LPEN_BIT) -#define RCC_APB2LPENR_TIM1LPEN (1U << RCC_APB2LPENR_TIM1LPEN_BIT) - -/* Backup domain control register */ - -#define RCC_BDCR_BDRST_BIT 16 -#define RCC_BDCR_RTCEN_BIT 15 -#define RCC_BDCR_LSEBYP_BIT 2 -#define RCC_BDCR_LSERDY_BIT 1 -#define RCC_BDCR_LSEON_BIT 0 - -#define RCC_BDCR_BDRST (1U << RCC_BDCR_BDRST_BIT) -#define RCC_BDCR_RTCEN (1U << RCC_BDCR_RTCEN_BIT) -#define RCC_BDCR_RTCSEL (0x3 << 8) -#define RCC_BDCR_RTCSEL_NOCLOCK (0x0 << 8) -#define RCC_BDCR_RTCSEL_LSE (0x1 << 8) -#define RCC_BDCR_RTCSEL_LSI (0x2 << 8) -#define RCC_BDCR_RTCSEL_HSE_DIV (0x3 << 8) -#define RCC_BDCR_LSEBYP (1U << RCC_BDCR_LSEBYP_BIT) -#define RCC_BDCR_LSERDY (1U << RCC_BDCR_LSERDY_BIT) -#define RCC_BDCR_LSEON (1U << RCC_BDCR_LSEON_BIT) - -/* Clock control and status register */ - -#define RCC_CSR_LPWRRSTF_BIT 31 -#define RCC_CSR_WWDGRSTF_BIT 30 -#define RCC_CSR_IWDGRSTF_BIT 29 -#define RCC_CSR_SFTRSTF_BIT 28 -#define RCC_CSR_PORRSTF_BIT 27 -#define RCC_CSR_PINRSTF_BIT 26 -#define RCC_CSR_BORRSTF_BIT 25 -#define RCC_CSR_RMVF_BIT 24 -#define RCC_CSR_LSIRDY_BIT 1 -#define RCC_CSR_LSION_BIT 0 - -#define RCC_CSR_LPWRRSTF (1U << RCC_CSR_LPWRRSTF_BIT) -#define RCC_CSR_WWDGRSTF (1U << RCC_CSR_WWDGRSTF_BIT) -#define RCC_CSR_IWDGRSTF (1U << RCC_CSR_IWDGRSTF_BIT) -#define RCC_CSR_SFTRSTF (1U << RCC_CSR_SFTRSTF_BIT) -#define RCC_CSR_PORRSTF (1U << RCC_CSR_PORRSTF_BIT) -#define RCC_CSR_PINRSTF (1U << RCC_CSR_PINRSTF_BIT) -#define RCC_CSR_BORRSTF (1U << RCC_CSR_BORRSTF_BIT) -#define RCC_CSR_RMVF (1U << RCC_CSR_RMVF_BIT) -#define RCC_CSR_LSIRDY (1U << RCC_CSR_LSIRDY_BIT) -#define RCC_CSR_LSION (1U << RCC_CSR_LSION_BIT) - -/* Spread spectrum clock generation register */ - -#define RCC_SSCGR_SSCGEN_BIT 31 -#define RCC_SSCGR_SPREADSEL_BIT 30 - -#define RCC_SSCGR_SSCGEN (1U << RCC_SSCGR_SSCGEN_BIT) -#define RCC_SSCGR_SPREADSEL (1U << RCC_SSCGR_SPREADSEL_BIT) -#define RCC_SSCGR_SPREADSEL_CENTER (0x0 << RCC_SSCGR_SPREADSEL_BIT) -#define RCC_SSCGR_SPREADSEL_DOWN (0x1 << RCC_SSCGR_SPREADSEL_BIT) -#define RCC_SSCGR_INCSTEP (0xFFF << 16) -#define RCC_SSCGR_MODPER 0xFFFF - -/* PLLI2S configuration register */ - -#define RCC_PLLI2SCFGR_PLLI2SR (0x7 << 28) -#define RCC_PLLI2SCFGR_PLLI2SN (0x1FF << 6) - -/* - * Clock sources, domains, and peripheral clock IDs. - */ - -/** - * @brief STM32F2 clock sources. - */ -typedef enum rcc_clk { - RCC_CLK_PLLI2S = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | - RCC_CR_PLLI2SON_BIT), /**< Dedicated PLL - for I2S. */ - RCC_CLK_PLL = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | - RCC_CR_PLLON_BIT), /**< Main PLL, clocked by - HSI or HSE. */ - RCC_CLK_HSE = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | - RCC_CR_HSEON_BIT), /**< High speed external. */ - RCC_CLK_HSI = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | - RCC_CR_HSION_BIT), /**< High speed internal. */ - RCC_CLK_LSE = (uint16)((offsetof(struct rcc_reg_map, BDCR) << 8) | - RCC_BDCR_LSEON_BIT), /**< Low-speed external - * (32.768 KHz). */ - RCC_CLK_LSI = (uint16)((offsetof(struct rcc_reg_map, CSR) << 8) | - RCC_CSR_LSION_BIT), /**< Low-speed internal - * (approximately 32 KHz). */ -} rcc_clk; - -/** - * @brief STM32F2 rcc_clk_id. - */ -typedef enum rcc_clk_id { - RCC_ADC1, - RCC_ADC2, - RCC_ADC3, - RCC_BKPSRAM, - RCC_CAN1, - RCC_CAN2, - RCC_CRC, - RCC_CRYP, - RCC_DAC, - RCC_DCMI, - RCC_DMA1, - RCC_DMA2, - RCC_ETHMAC, - RCC_ETHMACPTP, - RCC_ETHMACRX, - RCC_ETHMACTX, - RCC_FSMC, - RCC_GPIOA, - RCC_GPIOB, - RCC_GPIOC, - RCC_GPIOD, - RCC_GPIOE, - RCC_GPIOF, - RCC_GPIOG, - RCC_GPIOH, - RCC_GPIOI, - RCC_HASH, - RCC_I2C1, - RCC_I2C2, - RCC_I2C3, - RCC_OTGFS, - RCC_OTGHS, - RCC_OTGHSULPI, - RCC_PWR, - RCC_RNG, - RCC_SDIO, - RCC_SPI1, - RCC_SPI2, - RCC_SPI3, - RCC_SYSCFG, - RCC_TIMER1, - RCC_TIMER10, - RCC_TIMER11, - RCC_TIMER12, - RCC_TIMER13, - RCC_TIMER14, - RCC_TIMER2, - RCC_TIMER3, - RCC_TIMER4, - RCC_TIMER5, - RCC_TIMER6, - RCC_TIMER7, - RCC_TIMER8, - RCC_TIMER9, - RCC_USART1, - RCC_USART2, - RCC_USART3, - RCC_UART4, - RCC_UART5, - RCC_USART6, - RCC_WWDG, -} rcc_clk_id; - -/** - * @brief STM32F2 PLL entry clock source - * @see rcc_configure_pll() - */ -typedef enum rcc_pllsrc { - RCC_PLLSRC_HSI = 0, - RCC_PLLSRC_HSE = RCC_PLLCFGR_PLLSRC, -} rcc_pllsrc; - -/** - * @brief STM32F2 Peripheral clock domains. - */ -typedef enum rcc_clk_domain { - RCC_APB1, - RCC_APB2, - RCC_AHB1, - RCC_AHB2, - RCC_AHB3, -} rcc_clk_domain; - -/* - * Prescalers and dividers. - */ - -/** - * @brief STM32F2 Prescaler identifiers. - */ -typedef enum rcc_prescaler { - RCC_PRESCALER_MCO2, - RCC_PRESCALER_MCO1, - RCC_PRESCALER_RTC, - RCC_PRESCALER_APB2, - RCC_PRESCALER_APB1, - RCC_PRESCALER_AHB -} rcc_prescaler; - -/** - * @brief STM32F2 MCO2 prescaler dividers. - */ -typedef enum rcc_mco2_divider { - RCC_MCO2_DIV_1 = RCC_CFGR_MCO2PRE_DIV_1, - RCC_MCO2_DIV_2 = RCC_CFGR_MCO2PRE_DIV_2, - RCC_MCO2_DIV_3 = RCC_CFGR_MCO2PRE_DIV_3, - RCC_MCO2_DIV_4 = RCC_CFGR_MCO2PRE_DIV_4, - RCC_MCO2_DIV_5 = RCC_CFGR_MCO2PRE_DIV_5, -} rcc_mco2_divider; - -/** - * @brief STM32F2 MCO1 prescaler dividers. - */ -typedef enum rcc_mco1_divider { - RCC_MCO1_DIV_1 = RCC_CFGR_MCO1PRE_DIV_1, - RCC_MCO1_DIV_2 = RCC_CFGR_MCO1PRE_DIV_2, - RCC_MCO1_DIV_3 = RCC_CFGR_MCO1PRE_DIV_3, - RCC_MCO1_DIV_4 = RCC_CFGR_MCO1PRE_DIV_4, - RCC_MCO1_DIV_5 = RCC_CFGR_MCO1PRE_DIV_5, -} rcc_mco1_divider; - -/** - * @brief STM32F2 RTC prescaler dividers. - */ -typedef enum rcc_rtc_divider { /* FIXME [0.0.13] TODO */ - RCC_RTC_DIV_TODO = 0xFFFFFFFF, -} rcc_rtc_divider; - -/** - * @brief STM32F2 AP2 prescaler dividers. - */ -typedef enum rcc_apb2_divider { - RCC_APB2_HCLK_DIV_1 = 0, - RCC_APB2_HCLK_DIV_2 = RCC_CFGR_PPRE2_AHB_DIV_2, - RCC_APB2_HCLK_DIV_4 = RCC_CFGR_PPRE2_AHB_DIV_4, - RCC_APB2_HCLK_DIV_8 = RCC_CFGR_PPRE2_AHB_DIV_8, - RCC_APB2_HCLK_DIV_16 = RCC_CFGR_PPRE2_AHB_DIV_16, -} rcc_apb2_divider; - -/** - * @brief STM32F2 APB1 prescaler dividers. - */ -typedef enum rcc_apb1_divider { - RCC_APB1_HCLK_DIV_1 = 0, - RCC_APB1_HCLK_DIV_2 = RCC_CFGR_PPRE1_AHB_DIV_2, - RCC_APB1_HCLK_DIV_4 = RCC_CFGR_PPRE1_AHB_DIV_4, - RCC_APB1_HCLK_DIV_8 = RCC_CFGR_PPRE1_AHB_DIV_8, - RCC_APB1_HCLK_DIV_16 = RCC_CFGR_PPRE1_AHB_DIV_16, -} rcc_apb1_divider; - -/** - * @brief STM32F2 AHB prescaler dividers. - */ -typedef enum rcc_ahb_divider { - RCC_AHB_SYSCLK_DIV_1 = 0, - RCC_AHB_SYSCLK_DIV_2 = RCC_CFGR_HPRE_SYSCLK_DIV_2, - RCC_AHB_SYSCLK_DIV_4 = RCC_CFGR_HPRE_SYSCLK_DIV_4, - RCC_AHB_SYSCLK_DIV_8 = RCC_CFGR_HPRE_SYSCLK_DIV_8, - RCC_AHB_SYSCLK_DIV_16 = RCC_CFGR_HPRE_SYSCLK_DIV_16, - RCC_AHB_SYSCLK_DIV_64 = RCC_CFGR_HPRE_SYSCLK_DIV_64, - RCC_AHB_SYSCLK_DIV_128 = RCC_CFGR_HPRE_SYSCLK_DIV_128, - RCC_AHB_SYSCLK_DIV_256 = RCC_CFGR_HPRE_SYSCLK_DIV_256, - RCC_AHB_SYSCLK_DIV_512 = RCC_CFGR_HPRE_SYSCLK_DIV_512, -} rcc_ahb_divider; - -/** - * @brief STM32F2 PLL configuration values. - * Point to one of these with the "data" field in a struct rcc_pll_cfg. - * @see struct rcc_pll_cfg. - */ -typedef struct stm32f2_rcc_pll_data { - uint8 pllq; /**< - * @brief PLLQ value. - * Allowed values: 4, 5, ..., 15. */ - uint8 pllp; /**< - * @brief PLLP value. - * Allowed values: 2, 4, 6, 8. */ - uint16 plln; /**< - * @brief PLLN value. - * Allowed values: 192, 193, ..., 432. */ - uint8 pllm; /**< - * @brief PLLM value. - * Allowed values: 2, 3, ..., 63. */ -} stm32f2_rcc_pll_data; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/spi.h b/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/spi.h deleted file mode 100644 index 7b9f94a..0000000 --- a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/spi.h +++ /dev/null @@ -1,88 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2012 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/stm32f2/include/series/spi.h - * @author Marti Bolivar - * @brief STM32F2 SPI/I2S series header. - */ - -#ifndef _LIBMAPLE_STM32F2_SPI_H_ -#define _LIBMAPLE_STM32F2_SPI_H_ - -#include /* for gpio_af */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Register map base pointers - */ - -struct spi_reg_map; - -#define SPI1_BASE ((struct spi_reg_map*)0x40013000) -#define SPI2_BASE ((struct spi_reg_map*)0x40003800) -#define SPI3_BASE ((struct spi_reg_map*)0x40003C00) - -/* - * Register bit definitions - */ - -/* Control register 2 */ - -#define SPI_CR2_FRF_BIT 4 - -#define SPI_CR2_FRF (1U << SPI_CR2_FRF_BIT) - -/* Status register */ - -#define SPI_SR_TIFRFE_BIT 8 - -#define SPI_SR_TIFRFE (1U << SPI_SR_TIFRFE_BIT) - -/* - * Device pointers - */ - -struct spi_dev; - -extern struct spi_dev *SPI1; -extern struct spi_dev *SPI2; -extern struct spi_dev *SPI3; - -/* - * Routines - */ - -gpio_af spi_get_af(struct spi_dev *dev); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/stm32.h b/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/stm32.h deleted file mode 100644 index 180ab30..0000000 --- a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/stm32.h +++ /dev/null @@ -1,77 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/stm32f2/include/series/stm32.h - * @brief STM32F2 chip- and series-specific definitions. - */ - -#ifndef _LIBMAPLE_STM32F2_STM32_H_ -#define _LIBMAPLE_STM32F2_STM32_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Chip configuration - */ - -#ifndef STM32_PCLK1 -#define STM32_PCLK1 30000000U -#endif - -#ifndef STM32_PCLK2 -#define STM32_PCLK2 60000000U -#endif - -#ifndef STM32_DELAY_US_MULT -#define STM32_DELAY_US_MULT 20 /* FIXME: dummy value. */ -#endif - -/* - * Series- and MCU-specific values - */ - -#define STM32_MCU_SERIES STM32_SERIES_F2 -#define STM32_NR_INTERRUPTS 81 -#define STM32_HAVE_FSMC 1 -#define STM32_HAVE_USB 1 -#define STM32_HAVE_DAC 1 - -#if defined(MCU_STM32F207IC) || defined(MCU_STM32F207IG) -# define STM32_NR_GPIO_PORTS 9 -# define STM32_TIMER_MASK 0x7FFE /* TIMER1-TIMER14. */ -# define STM32_SRAM_END ((void*)0x20020000) -#else -#warning "Unsupported or unspecified STM32F2 MCU." -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/timer.h b/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/timer.h deleted file mode 100644 index a7ac276..0000000 --- a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/timer.h +++ /dev/null @@ -1,176 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011,2012 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/stm32f2/include/series/timer.h - * @author Marti Bolivar - * @brief STM32F2 timer support. - */ - -#ifndef _LIBMAPLE_STM32F2_TIMER_H_ -#define _LIBMAPLE_STM32F2_TIMER_H_ - -#include -#include /* for gpio_af */ - -/* - * Register maps and base pointers - */ - -/** - * @brief STM32F2 general purpose timer register map type - * - * Note that not all general purpose timers have all of these - * registers. Consult your chip's reference manual for the details. - */ -typedef struct timer_gen_reg_map { - __io uint32 CR1; /**< Control register 1 */ - __io uint32 CR2; /**< Control register 2 */ - __io uint32 SMCR; /**< Slave mode control register */ - __io uint32 DIER; /**< DMA/Interrupt enable register */ - __io uint32 SR; /**< Status register */ - __io uint32 EGR; /**< Event generation register */ - __io uint32 CCMR1; /**< Capture/compare mode register 1 */ - __io uint32 CCMR2; /**< Capture/compare mode register 2 */ - __io uint32 CCER; /**< Capture/compare enable register */ - __io uint32 CNT; /**< Counter */ - __io uint32 PSC; /**< Prescaler */ - __io uint32 ARR; /**< Auto-reload register */ - const uint32 RESERVED1; /**< Reserved */ - __io uint32 CCR1; /**< Capture/compare register 1 */ - __io uint32 CCR2; /**< Capture/compare register 2 */ - __io uint32 CCR3; /**< Capture/compare register 3 */ - __io uint32 CCR4; /**< Capture/compare register 4 */ - const uint32 RESERVED2; /**< Reserved */ - __io uint32 DCR; /**< DMA control register */ - __io uint32 DMAR; /**< DMA address for full transfer */ - __io uint32 OR; /**< Option register. */ -} timer_gen_reg_map; - -struct timer_adv_reg_map; -struct timer_bas_reg_map; - -/** Timer 1 register map base pointer */ -#define TIMER1_BASE ((struct timer_adv_reg_map*)0x40010000) -/** Timer 2 register map base pointer */ -#define TIMER2_BASE ((struct timer_gen_reg_map*)0x40000000) -/** Timer 3 register map base pointer */ -#define TIMER3_BASE ((struct timer_gen_reg_map*)0x40000400) -/** Timer 4 register map base pointer */ -#define TIMER4_BASE ((struct timer_gen_reg_map*)0x40000800) -/** Timer 5 register map base pointer */ -#define TIMER5_BASE ((struct timer_gen_reg_map*)0x40000C00) -/** Timer 6 register map base pointer */ -#define TIMER6_BASE ((struct timer_bas_reg_map*)0x40001000) -/** Timer 7 register map base pointer */ -#define TIMER7_BASE ((struct timer_bas_reg_map*)0x40001400) -/** Timer 8 register map base pointer */ -#define TIMER8_BASE ((struct timer_adv_reg_map*)0x40010400) -/** Timer 9 register map base pointer */ -#define TIMER9_BASE ((struct timer_gen_reg_map*)0x40014000) -/** Timer 10 register map base pointer */ -#define TIMER10_BASE ((struct timer_gen_reg_map*)0x40014400) -/** Timer 11 register map base pointer */ -#define TIMER11_BASE ((struct timer_gen_reg_map*)0x40014800) -/** Timer 12 register map base pointer */ -#define TIMER12_BASE ((struct timer_gen_reg_map*)0x40001800) -/** Timer 13 register map base pointer */ -#define TIMER13_BASE ((struct timer_gen_reg_map*)0x40001C00) -/** Timer 14 register map base pointer */ -#define TIMER14_BASE ((struct timer_gen_reg_map*)0x40002000) - -/* - * Register bit definitions - */ - -/* TIM2 option register */ - -/** Timer 2 option register internal trigger 1 remap */ -#define TIMER2_OR_ITR1_RMP (0x3 << 10) -/** Timer 2 OR internal trigger 1: TIM8_TRGOUT */ -#define TIMER2_OR_ITR1_RMP_TIM8_TRGOUT (0x0 << 10) -/** Timer 2 OR internal trigger 1: Ethernet PTP trigger output */ -#define TIMER2_OR_ITR1_RMP_PTP_TRGOUT (0x1 << 10) -/** Timer 2 OR internal trigger 1: USB OTG full speed start of frame */ -#define TIMER2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10) -/** Timer 2 OR internal trigger 1: USB OTG high speed start of frame */ -#define TIMER2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10) - -/* TIM5 option register */ - -/** - * Timer 5 option register input 4 remap. - * - * These bits control whether TIM5_CH4 is connected to a GPIO or a - * clock. Connecting to a GPIO is the normal mode, useful for e.g. PWM - * generation or input pulse duration measurement. Connecting to a - * clock is useful for calibrating that clock. - */ -#define TIMER5_OR_TI4_RMP (0x3 << 6) -/** - * Timer 5 OR input 4: Timer 5 channel 4 connected to GPIO. */ -#define TIMER5_OR_TI4_RMP_GPIO (0x0 << 6) -/** - * Timer 5 OR input 4: low speed internal clock (LSI) is connected to - * TIM5_CH4. */ -#define TIMER5_OR_TI4_RMP_LSI (0x1 << 6) -/** - * Timer 5 OR input 4: low speed external clock (LSE) is connected to - * TIM5_CH4. */ -#define TIMER5_OR_TI4_RMP_LSE (0x2 << 6) -/** - * Timer 5 OR input 4: real time clock (RTC) output is connected to - * TIM5_CH4. */ -#define TIMER5_OR_TI4_RMP_RTC (0x3 << 6) - -/* - * Device pointers - */ - -struct timer_dev; - -extern struct timer_dev *TIMER1; -extern struct timer_dev *TIMER2; -extern struct timer_dev *TIMER3; -extern struct timer_dev *TIMER4; -extern struct timer_dev *TIMER5; -extern struct timer_dev *TIMER6; -extern struct timer_dev *TIMER7; -extern struct timer_dev *TIMER8; -extern struct timer_dev *TIMER9; -extern struct timer_dev *TIMER10; -extern struct timer_dev *TIMER11; -extern struct timer_dev *TIMER12; -extern struct timer_dev *TIMER13; -extern struct timer_dev *TIMER14; - -/* - * Routines - */ - -gpio_af timer_get_af(struct timer_dev *dev); - -#endif diff --git a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/usart.h b/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/usart.h deleted file mode 100644 index 8936efa..0000000 --- a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/include/series/usart.h +++ /dev/null @@ -1,111 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2012 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/stm32f2/include/series/usart.h - * @author Marti Bolivar - * @brief STM32F2 USART support. - */ - -#ifndef _LIBMAPLE_STM32F2_USART_H_ -#define _LIBMAPLE_STM32F2_USART_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -#include /* for gpio_af */ - -/* - * Register map base pointers. - */ - -struct usart_reg_map; - -/** USART1 register map base pointer */ -#define USART1_BASE ((struct usart_reg_map*)0x40011000) -/** USART2 register map base pointer */ -#define USART2_BASE ((struct usart_reg_map*)0x40004400) -/** USART3 register map base pointer */ -#define USART3_BASE ((struct usart_reg_map*)0x40004800) -/** UART4 register map base pointer */ -#define UART4_BASE ((struct usart_reg_map*)0x40004C00) -/** UART5 register map base pointer */ -#define UART5_BASE ((struct usart_reg_map*)0x40005000) -/** USART6 register map base pointer */ -#define USART6_BASE ((struct usart_reg_map*)0x40011400) - -/* - * F2-only register bit definitions. - */ - -/* Control register 1 */ - -/** - * @brief Oversampling mode bit. - * Availability: STM32F2. */ -#define USART_CR1_OVER8_BIT 15 - -/** - * @brief Oversampling mode. - * Availability: STM32F2. */ -#define USART_CR1_OVER8 (1U << USART_CR1_OVER8_BIT) - -/* Control register 3 */ - -/** One sample bit method enable bit. */ -#define USART_CR3_ONEBIT_BIT 11 - -/** One bit sample method enable. */ -#define USART_CR3_ONEBIT (1 << USART_CR3_ONEBIT_BIT) -/** Sample method: Three sample bit method. */ -#define USART_CR3_ONEBIT_3SAMPLE (0 << USART_CR3_ONEBIT_BIT) -/** Sample method: One sample bit method. */ -#define USART_CR3_ONEBIT_1SAMPLE (1 << USART_CR3_ONEBIT_BIT) - -/* - * Devices - */ - -struct usart_dev; -extern struct usart_dev *USART1; -extern struct usart_dev *USART2; -extern struct usart_dev *USART3; -extern struct usart_dev *UART4; -extern struct usart_dev *UART5; -extern struct usart_dev *USART6; - -/* - * Routines - */ - -gpio_af usart_get_af(struct usart_dev *dev); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/rules.mk b/BootLoaders/Boards/stm32/system/libmaple/stm32f2/rules.mk deleted file mode 100644 index 4c62cc2..0000000 --- a/BootLoaders/Boards/stm32/system/libmaple/stm32f2/rules.mk +++ /dev/null @@ -1,40 +0,0 @@ -# Standard things -sp := $(sp).x -dirstack_$(sp) := $(d) -d := $(dir) -BUILDDIRS += $(BUILD_PATH)/$(d) - -# Local flags -CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) $(LIBMAPLE_PRIVATE_INCLUDES) -Wall -Werror - -# Local rules and targets -sSRCS_$(d) := isrs.S -sSRCS_$(d) += vector_table.S - -cSRCS_$(d) := adc.c -cSRCS_$(d) += dma.c -cSRCS_$(d) += exti.c -cSRCS_$(d) += fsmc.c -cSRCS_$(d) += gpio.c -cSRCS_$(d) += rcc.c -cSRCS_$(d) += spi.c -cSRCS_$(d) += syscfg.c -cSRCS_$(d) += timer.c -cSRCS_$(d) += usart.c - -sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) -cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) - -OBJS_$(d) := $(sFILES_$(d):%.S=$(BUILD_PATH)/%.o) \ - $(cFILES_$(d):%.c=$(BUILD_PATH)/%.o) -DEPS_$(d) := $(OBJS_$(d):%.o=%.d) - -$(OBJS_$(d)): TGT_ASFLAGS := -$(OBJS_$(d)): TGT_CFLAGS := $(CFLAGS_$(d)) - -TGT_BIN += $(OBJS_$(d)) - -# Standard things --include $(DEPS_$(d)) -d := $(dirstack_$(sp)) -sp := $(basename $(sp)) diff --git a/BootLoaders/Boards/stm32/system/libmaple/usb/stm32f1/usb_reg_map.h b/BootLoaders/Boards/stm32/system/libmaple/usb/stm32f1/usb_reg_map.h index 6683264..d0423fc 100644 --- a/BootLoaders/Boards/stm32/system/libmaple/usb/stm32f1/usb_reg_map.h +++ b/BootLoaders/Boards/stm32/system/libmaple/usb/stm32f1/usb_reg_map.h @@ -345,12 +345,12 @@ static inline void usb_clear_status_out(uint8 ep) { /* * PMA conveniences */ - +/* void usb_copy_to_pma(const uint8 *buf, uint16 len, uint16 pma_offset); void usb_copy_from_pma(uint8 *buf, uint16 len, uint16 pma_offset); - -static inline void* usb_pma_ptr(uint32 offset) { - return (void*)(USB_PMA_BASE + 2 * offset); +*/ +static inline uint32 * usb_pma_ptr(uint32 offset) { + return (uint32*)(USB_PMA_BASE + 2 * offset); } /* @@ -567,7 +567,7 @@ static inline uint16 usb_get_ep_rx_buf0_count(uint8 ep) { return usb_get_ep_tx_count(ep); } -void usb_set_ep_rx_buf0_count(uint8 ep, uint16 count); +//void usb_set_ep_rx_buf0_count(uint8 ep, uint16 count); static inline uint32* usb_ep_rx_buf1_count_ptr(uint8 ep) { return usb_ep_rx_count_ptr(ep); diff --git a/BootLoaders/Boards/stm32/tools/linux/do_version b/BootLoaders/Boards/stm32/tools/linux/do_version index b469a5c..6b47f49 100755 --- a/BootLoaders/Boards/stm32/tools/linux/do_version +++ b/BootLoaders/Boards/stm32/tools/linux/do_version @@ -6,7 +6,31 @@ SKETCH_PATH=$3 MULTI_BOARD=$4 EXPORT_FLAG=$5 -MULTI_TYPE=stm +IFS== read MULTI_BOARD BOARD_VERSION <<< "$MULTI_BOARD" + +case "$MULTI_BOARD" in + MULTI_NO_BOOT) + MULTI_TYPE=avr + ;; + MULTI_FLASH_FROM_TX) + MULTI_TYPE=avr + ;; + MULTI_STM32_NO_BOOT) + MULTI_TYPE=stm + ;; + MULTI_STM32_FLASH_FROM_TX) + MULTI_TYPE=stm + ;; + MULTI_ORANGERX) + MULTI_TYPE=orx + ;; +esac + +#echo "Build Path: $BUILD_PATH" +#echo "Sketch Path: $SKETCH_PATH" +#echo "Project Name: $PROJECT_NAME" +#echo "Multi Board: $MULTI_BOARD" +#echo "Multi Board Type: $MULTI_TYPE" if [ -e "$BUILD_PATH/sketch/Multiprotocol.h" ]; then MAJOR_VERSION=$(grep "VERSION_MAJOR" "$BUILD_PATH/sketch/Multiprotocol.h" | awk -v N=3 '{print $N}') diff --git a/BootLoaders/Boards/stm32/tools/linux64/do_version b/BootLoaders/Boards/stm32/tools/linux64/do_version index b469a5c..6b47f49 100755 --- a/BootLoaders/Boards/stm32/tools/linux64/do_version +++ b/BootLoaders/Boards/stm32/tools/linux64/do_version @@ -6,7 +6,31 @@ SKETCH_PATH=$3 MULTI_BOARD=$4 EXPORT_FLAG=$5 -MULTI_TYPE=stm +IFS== read MULTI_BOARD BOARD_VERSION <<< "$MULTI_BOARD" + +case "$MULTI_BOARD" in + MULTI_NO_BOOT) + MULTI_TYPE=avr + ;; + MULTI_FLASH_FROM_TX) + MULTI_TYPE=avr + ;; + MULTI_STM32_NO_BOOT) + MULTI_TYPE=stm + ;; + MULTI_STM32_FLASH_FROM_TX) + MULTI_TYPE=stm + ;; + MULTI_ORANGERX) + MULTI_TYPE=orx + ;; +esac + +#echo "Build Path: $BUILD_PATH" +#echo "Sketch Path: $SKETCH_PATH" +#echo "Project Name: $PROJECT_NAME" +#echo "Multi Board: $MULTI_BOARD" +#echo "Multi Board Type: $MULTI_TYPE" if [ -e "$BUILD_PATH/sketch/Multiprotocol.h" ]; then MAJOR_VERSION=$(grep "VERSION_MAJOR" "$BUILD_PATH/sketch/Multiprotocol.h" | awk -v N=3 '{print $N}') diff --git a/BootLoaders/Boards/stm32/tools/macosx/do_version b/BootLoaders/Boards/stm32/tools/macosx/do_version index b469a5c..6b47f49 100755 --- a/BootLoaders/Boards/stm32/tools/macosx/do_version +++ b/BootLoaders/Boards/stm32/tools/macosx/do_version @@ -6,7 +6,31 @@ SKETCH_PATH=$3 MULTI_BOARD=$4 EXPORT_FLAG=$5 -MULTI_TYPE=stm +IFS== read MULTI_BOARD BOARD_VERSION <<< "$MULTI_BOARD" + +case "$MULTI_BOARD" in + MULTI_NO_BOOT) + MULTI_TYPE=avr + ;; + MULTI_FLASH_FROM_TX) + MULTI_TYPE=avr + ;; + MULTI_STM32_NO_BOOT) + MULTI_TYPE=stm + ;; + MULTI_STM32_FLASH_FROM_TX) + MULTI_TYPE=stm + ;; + MULTI_ORANGERX) + MULTI_TYPE=orx + ;; +esac + +#echo "Build Path: $BUILD_PATH" +#echo "Sketch Path: $SKETCH_PATH" +#echo "Project Name: $PROJECT_NAME" +#echo "Multi Board: $MULTI_BOARD" +#echo "Multi Board Type: $MULTI_TYPE" if [ -e "$BUILD_PATH/sketch/Multiprotocol.h" ]; then MAJOR_VERSION=$(grep "VERSION_MAJOR" "$BUILD_PATH/sketch/Multiprotocol.h" | awk -v N=3 '{print $N}') diff --git a/BootLoaders/Boards/stm32/tools/win/do_version.bat b/BootLoaders/Boards/stm32/tools/win/do_version.bat index 958ba17..d855889 100644 --- a/BootLoaders/Boards/stm32/tools/win/do_version.bat +++ b/BootLoaders/Boards/stm32/tools/win/do_version.bat @@ -7,31 +7,43 @@ SET BUILD_PATH=%1 SET PROJECT_NAME=%2 SET SKETCH_PATH=%3 SET MULTI_BOARD=%4 -SET EXPORT_FLAG=%5 +SET BOARD_VERSION=%5 +SET EXPORT_FLAG=%6 REM Remove double-quotes from the paths SET BUILD_PATH=%BUILD_PATH:"=% SET SKETCH_PATH=%SKETCH_PATH:"=% +IF %MULTI_BOARD%==MULTI_NO_BOOT SET MULTI_TYPE=avr +IF %MULTI_BOARD%==MULTI_FLASH_FROM_TX SET MULTI_TYPE=avr +IF %MULTI_BOARD%==MULTI_STM32_NO_BOOT SET MULTI_TYPE=stm +IF %MULTI_BOARD%==MULTI_STM32_FLASH_FROM_TX SET MULTI_TYPE=stm +IF %MULTI_BOARD%==MULTI_ORANGERX SET MULTI_TYPE=orx + IF DEFINED DEBUG ( + ECHO. ECHO Sketch Path: %SKETCH_PATH% - ECHO Multi board: %MULTI_BOARD% + ECHO Multi Board: %MULTI_BOARD% + ECHO Multi Board Type: %MULTI_TYPE% + ECHO. ) -SET MULTI_TYPE=stm - -IF EXIST "%1\sketch\Multiprotocol.h" ( - REM ECHO Getting Multi-MODULE firmware version from "%1\sketch\Multiprotocol.h" - FOR /F "tokens=* usebackq skip=2" %%A in (`find "#define VERSION_MAJOR" "%1\sketch\Multiprotocol.h"`) DO FOR /F "tokens=3" %%i in ("%%A") do SET MAJOR_VERSION=%%i - FOR /F "tokens=* usebackq skip=2" %%B in (`find "#define VERSION_MINOR" "%1\sketch\Multiprotocol.h"`) DO FOR /F "tokens=3" %%i in ("%%B") do SET MINOR_VERSION=%%i - FOR /F "tokens=* usebackq skip=2" %%C in (`find "#define VERSION_REVISION" "%1\sketch\Multiprotocol.h"`) DO FOR /F "tokens=3" %%i in ("%%C") do SET REVISION_VERSION=%%i - FOR /F "tokens=* usebackq skip=2" %%D in (`find "#define VERSION_PATCH_LEVEL" "%1\sketch\Multiprotocol.h"`) DO FOR /F "tokens=3" %%i in ("%%D") do SET PATCH_VERSION=%%i +IF EXIST "%BUILD_PATH%\sketch\Multiprotocol.h" ( + IF DEFINED DEBUG ECHO Getting Multi firmware version from "%BUILD_PATH%\sketch\Multiprotocol.h" + FOR /F "tokens=* usebackq" %%A in (`%SystemRoot%\system32\findstr.exe /C:"#define VERSION_MAJOR" "%BUILD_PATH%\sketch\Multiprotocol.h"`) DO FOR /F "tokens=3" %%i in ("%%A") do SET MAJOR_VERSION=%%i + FOR /F "tokens=* usebackq" %%B in (`%SystemRoot%\system32\findstr.exe /C:"#define VERSION_MINOR" "%BUILD_PATH%\sketch\Multiprotocol.h"`) DO FOR /F "tokens=3" %%i in ("%%B") do SET MINOR_VERSION=%%i + FOR /F "tokens=* usebackq" %%C in (`%SystemRoot%\system32\findstr.exe /C:"#define VERSION_REVISION" "%BUILD_PATH%\sketch\Multiprotocol.h"`) DO FOR /F "tokens=3" %%i in ("%%C") do SET REVISION_VERSION=%%i + FOR /F "tokens=* usebackq" %%D in (`%SystemRoot%\system32\findstr.exe /C:"#define VERSION_PATCH_LEVEL" "%BUILD_PATH%\sketch\Multiprotocol.h"`) DO FOR /F "tokens=3" %%i in ("%%D") do SET PATCH_VERSION=%%i SET MULTI_VER=!MAJOR_VERSION!.!MINOR_VERSION!.!REVISION_VERSION!.!PATCH_VERSION! ) ELSE ( SET MULTI_VER= ) -IF DEFINED DEBUG ECHO Multi-MODULE firmware version: %MULTI_VER% +IF DEFINED DEBUG ( + ECHO. + ECHO Multi Firmware Version: %MULTI_VER% + ECHO. +) REM Copy the compiled file to the sketch folder with the version number in the file name IF EXIST "%BUILD_PATH%\%PROJECT_NAME%.hex" ( diff --git a/BootLoaders/Boards/stm32/variants/generic_stm32f103c/board/board.h b/BootLoaders/Boards/stm32/variants/generic_stm32f103c/board/board.h index 209bc36..c747399 100644 --- a/BootLoaders/Boards/stm32/variants/generic_stm32f103c/board/board.h +++ b/BootLoaders/Boards/stm32/variants/generic_stm32f103c/board/board.h @@ -36,7 +36,7 @@ #ifndef _BOARD_GENERIC_STM32F103C_H_ #define _BOARD_GENERIC_STM32F103C_H_ -#define CYCLES_PER_MICROSECOND 72 +#define CYCLES_PER_MICROSECOND (F_CPU / 1000000U) #define SYSTICK_RELOAD_VAL (F_CPU/1000) - 1 /* takes a cycle to reload */ #define BOARD_NR_USARTS 3 @@ -70,8 +70,10 @@ #define BOARD_JTDO_PIN 19 #define BOARD_NJTRST_PIN 18 -#define BOARD_USB_DISC_DEV GPIOB -#define BOARD_USB_DISC_BIT 10 +#define BOARD_USB_DISC_DEV NULL +#define BOARD_USB_DISC_BIT NULL + +#define LED_BUILTIN PC13 // Note this needs to match with the PIN_MAP array in board.cpp enum { diff --git a/BootLoaders/Boards/stm32/variants/generic_stm32f103c/variant.h b/BootLoaders/Boards/stm32/variants/generic_stm32f103c/variant.h index 8a88623..4c08d06 100644 --- a/BootLoaders/Boards/stm32/variants/generic_stm32f103c/variant.h +++ b/BootLoaders/Boards/stm32/variants/generic_stm32f103c/variant.h @@ -17,4 +17,6 @@ static const uint8_t MOSI = BOARD_SPI1_MOSI_PIN; static const uint8_t MISO = BOARD_SPI1_MISO_PIN; static const uint8_t SCK = BOARD_SPI1_SCK_PIN; -#endif /* _VARIANT_ARDUINO_STM32_ */ \ No newline at end of file +#define LED_BUILTIN PC13 + +#endif /* _VARIANT_ARDUINO_STM32_ */ diff --git a/BootLoaders/Boards/stm32/variants/generic_stm32f103c/wirish/boards_setup.cpp b/BootLoaders/Boards/stm32/variants/generic_stm32f103c/wirish/boards_setup.cpp index 0e5bc55..6ab16e8 100644 --- a/BootLoaders/Boards/stm32/variants/generic_stm32f103c/wirish/boards_setup.cpp +++ b/BootLoaders/Boards/stm32/variants/generic_stm32f103c/wirish/boards_setup.cpp @@ -48,7 +48,13 @@ // works for F103 performance line MCUs, which is all that LeafLabs // currently officially supports). #ifndef BOARD_RCC_PLLMUL -#define BOARD_RCC_PLLMUL RCC_PLLMUL_9 + #if F_CPU==128000000 + #define BOARD_RCC_PLLMUL RCC_PLLMUL_16 + #elif F_CPU==72000000 + #define BOARD_RCC_PLLMUL RCC_PLLMUL_9 + #elif F_CPU==48000000 + #define BOARD_RCC_PLLMUL RCC_PLLMUL_6 + #endif #endif namespace wirish { @@ -71,7 +77,7 @@ namespace wirish { #if F_CPU == 72000000 rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5); #elif F_CPU == 48000000 - rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5); + rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1); #endif } diff --git a/BootLoaders/Boards/stm32/variants/generic_stm32f103c/wirish/syscalls.c b/BootLoaders/Boards/stm32/variants/generic_stm32f103c/wirish/syscalls.c index d5f2d9f..ec1c34d 100644 --- a/BootLoaders/Boards/stm32/variants/generic_stm32f103c/wirish/syscalls.c +++ b/BootLoaders/Boards/stm32/variants/generic_stm32f103c/wirish/syscalls.c @@ -76,28 +76,28 @@ void *_sbrk(int incr) { return ret; } -__weak int _open(const char *path, int flags, ...) { +__weak int _open(const char *path __attribute__((unused)), int flags __attribute__((unused)), ...) { return 1; } -__weak int _close(int fd) { +__weak int _close(int fd __attribute__((unused))) { return 0; } -__weak int _fstat(int fd, struct stat *st) { +__weak int _fstat(int fd __attribute__((unused)), struct stat *st) { st->st_mode = S_IFCHR; return 0; } -__weak int _isatty(int fd) { +__weak int _isatty(int fd __attribute__((unused))) { return 1; } -__weak int isatty(int fd) { +__weak int isatty(int fd __attribute__((unused))) { return 1; } -__weak int _lseek(int fd, off_t pos, int whence) { +__weak int _lseek(int fd __attribute__((unused)), off_t pos __attribute__((unused)), int whence __attribute__((unused))) { return -1; } @@ -106,13 +106,13 @@ __weak unsigned char getch(void) { } -__weak int _read(int fd, char *buf, size_t cnt) { +__weak int _read(int fd __attribute__((unused)), char *buf, size_t cnt __attribute__((unused))) { *buf = getch(); return 1; } -__weak void putch(unsigned char c) { +__weak void putch(unsigned char c __attribute__((unused))) { } __weak void cgets(char *s, int bufsize) { @@ -155,7 +155,7 @@ __weak void cgets(char *s, int bufsize) { return; } -__weak int _write(int fd, const char *buf, size_t cnt) { +__weak int _write(int fd __attribute__((unused)), const char *buf, size_t cnt) { int i; for (i = 0; i < cnt; i++) @@ -165,12 +165,12 @@ __weak int _write(int fd, const char *buf, size_t cnt) { } /* Override fgets() in newlib with a version that does line editing */ -__weak char *fgets(char *s, int bufsize, void *f) { +__weak char *fgets(char *s, int bufsize, void *f __attribute__((unused))) { cgets(s, bufsize); return s; } -__weak void _exit(int exitcode) { +__weak void _exit(int exitcode __attribute__((unused))) { while (1) ; } diff --git a/BootLoaders/README.md b/BootLoaders/README.md index 272afc3..8a14bc6 100644 --- a/BootLoaders/README.md +++ b/BootLoaders/README.md @@ -1,6 +1,8 @@ # Arduino IDE board definitions for Multi 4-in-1 Board definitions are available for the Atmega328p, STM32, and OrangeRX modules. The board definitions make it easier to compile and install the multiprotocol module firmware. +**Note:** The Orange RX module is now included in the **Multi 4-in-1 AVR Boards** package, it no longer has a dedicated package. If you have the dedicated OrangeRX package installed you should remove it and install the most recent AVR package (v1.0.2 or newer). + ## Installing The board definitions are installed using the Arduino IDE Boards Manager. @@ -34,8 +36,8 @@ The board definitions are installed using the Arduino IDE Boards Manager. 2. Scroll down the list to the **Multi 4-in-1** board headings verify that the boards you installed are available: ![Image](/docs/images/boards-menu.jpg) - * **Multi 4-in-1 (Atmega328p, 3.3V, 16MHz)** for the Atmega module * **Multi 4-in-1 (STM32F103CB)** for the STM32 module + * **Multi 4-in-1 (Atmega328p, 3.3V, 16MHz)** for the Atmega module * **Multi 4-in-1 (OrangeRX)** for the OrangeRX module ## Compiling and Uploading diff --git a/BootLoaders/package_multi_4in1_board_index.json b/BootLoaders/package_multi_4in1_board_index.json index 3b4fd17..07c5689 100644 --- a/BootLoaders/package_multi_4in1_board_index.json +++ b/BootLoaders/package_multi_4in1_board_index.json @@ -8,14 +8,14 @@ "online": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module" }, "platforms": [{ - "name": "Multi 4-in-1 AVR Board", + "name": "Multi 4-in-1 AVR Boards", "architecture": "avr", "version": "1.0.0", "category": "Contributed", "help": { "online": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module" }, - "url": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module/raw/master/BootLoaders/package_multi_4in1_board_v1.0.0.zip", + "url": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module/raw/master/BootLoaders/Archives/package_multi_4in1_board_v1.0.0.zip", "archiveFileName": "package_multi_4in1_board_v1.0.0.zip", "checksum": "SHA-256:3DE301E9FC3C8A81CB2CEDE3458A68C626A9A5C37A73FA9C85BE9D841935684D", "size": "3205", @@ -25,14 +25,14 @@ "toolsDependencies": [] }, { - "name": "Multi 4-in-1 AVR Board", + "name": "Multi 4-in-1 AVR Boards", "architecture": "avr", "version": "1.0.1", "category": "Contributed", "help": { "online": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module" }, - "url": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module/raw/master/BootLoaders/package_multi_4in1_avr_board_v1.0.1.tar.gz", + "url": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module/raw/master/BootLoaders/Archives/package_multi_4in1_avr_board_v1.0.1.tar.gz", "archiveFileName": "package_multi_4in1_avr_board_v1.0.1.tar.gz", "checksum": "SHA-256:9bb29828476c141f5ef877e66b80ca969021d648acaf1ac5248676beb9ee3003", "size": "3201", @@ -41,6 +41,24 @@ }], "toolsDependencies": [] }, + { + "name": "Multi 4-in-1 AVR Boards", + "architecture": "avr", + "version": "1.0.2", + "category": "Contributed", + "help": { + "online": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module" + }, + "url": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module/raw/master/BootLoaders/Archives/package_multi_4in1_avr_board_v1.0.2.tar.gz", + "archiveFileName": "package_multi_4in1_avr_board_v1.0.2.tar.gz", + "checksum": "SHA-256:b7e2fda37186bf696b7a769b12317737d513181096b33d9ad321ec2fd47f3f80", + "size": "164467", + "boards": [ + {"name": "Multi 4-in-1 (Atmega328p, 3.3V, 16MHz)"}, + {"name": "Multi 4-in-1 (OrangeRX)"} + ], + "toolsDependencies": [] + }, { "name": "Multi 4-in-1 STM32 Board", "architecture": "STM32F1", @@ -49,7 +67,7 @@ "help": { "online": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module" }, - "url": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module/raw/master/BootLoaders/package_multi_4in1_stm32_board_v1.0.0.zip", + "url": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module/raw/master/BootLoaders/Archives/package_multi_4in1_stm32_board_v1.0.0.zip", "archiveFileName": "package_multi_4in1_stm32_board_v1.0.0.zip", "checksum": "SHA-256:7B661C6455F5AD7329E61EC297D4ADED9EF19F618E04E09A35A3C840977A56F5", "size": "10896168", @@ -70,7 +88,7 @@ "help": { "online": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module" }, - "url": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module/raw/master/BootLoaders/package_multi_4in1_stm32_board_v1.0.1.tar.gz", + "url": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module/raw/master/BootLoaders/Archives/package_multi_4in1_stm32_board_v1.0.1.tar.gz", "archiveFileName": "package_multi_4in1_stm32_board_v1.0.1.tar.gz", "checksum": "SHA-256:b522b5d3474308768c197a6897cad037fb54d6fac26c75678415a0908793bae3", "size": "10332106", @@ -91,10 +109,10 @@ "help": { "online": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module" }, - "url": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module/raw/master/BootLoaders/package_multi_4in1_stm32_board_v1.0.2.tar.gz", + "url": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module/raw/master/BootLoaders/Archives/package_multi_4in1_stm32_board_v1.0.2.tar.gz", "archiveFileName": "package_multi_4in1_stm32_board_v1.0.2.tar.gz", "checksum": "SHA-256:26D21DBD2FE80680AC523B8BCA24B3ECF2C2016BAC626826D20B651E11278287", - "size": "103318646", + "size": "10318646", "boards": [{ "name": "Multi 4-in-1 (STM32F103C)" }], @@ -105,14 +123,35 @@ }] }, { - "name": "Multi 4-in-1 OrangeRX Board", + "name": "Multi 4-in-1 STM32 Board", + "architecture": "STM32F1", + "version": "1.0.3", + "category": "Contributed", + "help": { + "online": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module" + }, + "url": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module/raw/master/BootLoaders/Archives/package_multi_4in1_stm32_board_v1.0.3.tar.gz", + "archiveFileName": "package_multi_4in1_stm32_board_v1.0.3.tar.gz", + "checksum": "SHA-256:e48f1f30948b3f7be83e8b1fe2bb5c6b41be7c4d5da02503a0b4827c60926541", + "size": "10309833", + "boards": [{ + "name": "Multi 4-in-1 (STM32F103C)" + }], + "toolsDependencies": [{ + "packager": "arduino", + "name": "arm-none-eabi-gcc", + "version": "4.8.3-2014q1" + }] + }, + { + "name": "Multi 4-in-1 OrangeRX Board - DEPRECATED, USE MULTI 4-IN-1 AVR BOARDS PACKAGE INSTEAD", "architecture": "orangerx", "version": "1.0.1", "category": "Contributed", "help": { "online": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module" }, - "url": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module/raw/master/BootLoaders/package_multi_4in1_orangerx_board_v1.0.1.tar.gz", + "url": "https://github.com/pascallanger/DIY-Multiprotocol-TX-Module/raw/master/BootLoaders/Archives/package_multi_4in1_orangerx_board_v1.0.1.tar.gz", "archiveFileName": "package_multi_4in1_orangerx_board_v1.0.1.tar.gz", "checksum": "SHA-256:7287ce61028b754bb8ff947317dd15773fc7eeecd752826c707fa356b9b36dc6", "size": "161615", diff --git a/Multiprotocol/Validate.h b/Multiprotocol/Validate.h index f149481..f350587 100644 --- a/Multiprotocol/Validate.h +++ b/Multiprotocol/Validate.h @@ -18,6 +18,23 @@ #endif #endif +// Check for minimum version of multi-module boards +#define MIN_AVR_BOARD 102 +#define MIN_ORX_BOARD 102 +#define MIN_STM32_BOARD 103 +//AVR +#if (defined(ARDUINO_MULTI_NO_BOOT) && ARDUINO_MULTI_NO_BOOT < MIN_AVR_BOARD) || (defined(ARDUINO_MULTI_FLASH_FROM_TX) && ARDUINO_MULTI_FLASH_FROM_TX < MIN_AVR_BOARD) + #error You need to update your Multi 4-in-1 board definition. Open Boards Manager and update to the latest version of the Multi 4-in-1 AVR Boards. +#endif +//OrangeRX +#if (defined(ARDUINO_MULTI_ORANGERX) && ARDUINO_MULTI_ORANGERX < MIN_ORX_BOARD) + #error You need to update your Multi 4-in-1 board definition. Open Boards Manager and update to the latest version of the Multi 4-in-1 AVR Boards. +#endif +//STM32 +#if (defined(ARDUINO_MULTI_STM32_NO_BOOT) && ARDUINO_MULTI_STM32_NO_BOOT < MIN_STM32_BOARD) || (defined(ARDUINO_MULTI_STM32_FLASH_FROM_TX) && ARDUINO_MULTI_STM32_FLASH_FROM_TX < MIN_STM32_BOARD) + #error You need to update your Multi 4-in-1 board definition. Open Boards Manager and update to the latest version of the Multi 4-in-1 STM32 Board. +#endif + // Error if CHECK_FOR_BOOTLOADER is not enabled but a FLASH_FROM_TX board is selected #if (defined(ARDUINO_MULTI_FLASH_FROM_TX) || defined(ARDUINO_MULTI_STM32_FLASH_FROM_TX)) &! defined(CHECK_FOR_BOOTLOADER) #if defined(STM32_BOARD) diff --git a/docs/Compiling_STM32.md b/docs/Compiling_STM32.md index c5a4bb4..2f5336d 100644 --- a/docs/Compiling_STM32.md +++ b/docs/Compiling_STM32.md @@ -1,4 +1,4 @@ -# Compliling and Programming (STM32) +# Compiling and Programming (STM32) Multiprotocol firmware is compiled using the Arduino IDE. The guide below will walk you through all the steps to compile and upload your customized firmware. diff --git a/docs/images/boards-menu.jpg b/docs/images/boards-menu.jpg index ff43f77..90a84a3 100644 Binary files a/docs/images/boards-menu.jpg and b/docs/images/boards-menu.jpg differ diff --git a/docs/images/multi-boards.jpg b/docs/images/multi-boards.jpg index a933424..3de0635 100644 Binary files a/docs/images/multi-boards.jpg and b/docs/images/multi-boards.jpg differ