DSM and DSM RX: fix bind

This commit is contained in:
Pascal Langer 2020-05-18 01:13:08 +02:00
parent ee080839b1
commit 987753ff73
5 changed files with 44 additions and 24 deletions

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@ -77,6 +77,7 @@ const uint8_t PROGMEM DSM_init_vals[][2] = {
{CYRF_28_CLK_EN, 0x02}, // Force receive clock enable {CYRF_28_CLK_EN, 0x02}, // Force receive clock enable
{CYRF_32_AUTO_CAL_TIME, 0x3c}, // Default init value {CYRF_32_AUTO_CAL_TIME, 0x3c}, // Default init value
{CYRF_35_AUTOCAL_OFFSET, 0x14}, // Default init value {CYRF_35_AUTOCAL_OFFSET, 0x14}, // Default init value
{CYRF_26_XTAL_CFG, 0x08}, // Start delay
{CYRF_06_RX_CFG, 0x4A}, // LNA enabled, RX override enabled, Fast turn mode enabled, RX is 1MHz below TX {CYRF_06_RX_CFG, 0x4A}, // LNA enabled, RX override enabled, Fast turn mode enabled, RX is 1MHz below TX
{CYRF_1B_TX_OFFSET_LSB, 0x55}, // Default init value {CYRF_1B_TX_OFFSET_LSB, 0x55}, // Default init value
{CYRF_1C_TX_OFFSET_MSB, 0x05}, // Default init value {CYRF_1C_TX_OFFSET_MSB, 0x05}, // Default init value

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@ -199,23 +199,25 @@ static void __attribute__((unused)) DSM_abort_channel_rx(uint8_t ch)
uint16_t DSM_Rx_callback() uint16_t DSM_Rx_callback()
{ {
uint8_t rx_status; uint8_t rx_status;
static uint8_t read_retry=10; static uint8_t read_retry=0;
static uint16_t pps_counter; static uint16_t pps_counter;
static uint32_t pps_timer = 0; static uint32_t pps_timer = 0;
switch (phase) switch (phase)
{ {
case DSM_RX_BIND1: case DSM_RX_BIND1:
if(packet_count==0)
read_retry=0;
//Check received data //Check received data
rx_status = CYRF_ReadRegister(CYRF_07_RX_IRQ_STATUS); rx_status = CYRF_ReadRegister(CYRF_07_RX_IRQ_STATUS);
if((rx_status & 0x03) == 0x02) // RXC=1, RXE=0 then 2nd check is required (debouncing) if((rx_status & 0x03) == 0x02) // RXC=1, RXE=0 then 2nd check is required (debouncing)
rx_status |= CYRF_ReadRegister(CYRF_07_RX_IRQ_STATUS); rx_status |= CYRF_ReadRegister(CYRF_07_RX_IRQ_STATUS);
if((rx_status & 0x07) == 0x02 && read_retry) if((rx_status & 0x07) == 0x02)
{ // data received with no errors { // data received with no errors
CYRF_WriteRegister(CYRF_07_RX_IRQ_STATUS, 0x80); // Need to set RXOW before data read CYRF_WriteRegister(CYRF_07_RX_IRQ_STATUS, 0x80); // Need to set RXOW before data read
rx_status=CYRF_ReadRegister(CYRF_09_RX_COUNT); len=CYRF_ReadRegister(CYRF_09_RX_COUNT);
debugln("RX:%d",rx_status); debugln("RX:%d, CH:%d",len,hopping_frequency_no);
if(rx_status==16) if(len==16)
{ {
CYRF_ReadDataPacketLen(packet_in, 16); CYRF_ReadDataPacketLen(packet_in, 16);
if(DSM_Rx_bind_check_validity()) if(DSM_Rx_bind_check_validity())
@ -263,29 +265,41 @@ uint16_t DSM_Rx_callback()
debugln(", num_ch=%d, type=%02X",num_ch, DSM_rx_type); debugln(", num_ch=%d, type=%02X",num_ch, DSM_rx_type);
CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x20); // Abort RX operation CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x20); // Abort RX operation
CYRF_SetTxRxMode(TX_EN); // Force end state TX CYRF_SetTxRxMode(TX_EN); // Force end state TX
CYRF_ConfigDataCode((const uint8_t *)"\x98\x88\x1B\xE4\x30\x79\x03\x84", 16);
CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x00); // Clear abort RX CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x00); // Clear abort RX
DSM_Rx_build_bind_packet(); DSM_Rx_build_bind_packet();
bind_counter=500; bind_counter=500;
phase++; // DSM_RX_BIND2; phase++; // DSM_RX_BIND2;
return 1000;
} }
} }
if(read_retry) DSM_abort_channel_rx(0); // Abort RX operation and receive
read_retry--; if(read_retry==0)
read_retry=4;
} }
else else
if(rx_status & 0x02) // RX error
DSM_abort_channel_rx(0); // Abort RX operation and receive
packet_count++;
if(packet_count>12)
{ {
packet_count=1;
if(read_retry)
read_retry--;
if(read_retry==0)
{
packet_count=0;
hopping_frequency_no++; // Change channel hopping_frequency_no++; // Change channel
hopping_frequency_no %= 0x50; hopping_frequency_no %= 0x50;
hopping_frequency_no |= 0x01; // Odd channels only hopping_frequency_no |= 0x01; // Odd channels only
CYRF_ConfigRFChannel(hopping_frequency_no); CYRF_ConfigRFChannel(hopping_frequency_no);
//debugln("ch:%d",hopping_frequency_no);
read_retry = 10;
DSM_abort_channel_rx(0); // Abort RX operation and receive DSM_abort_channel_rx(0); // Abort RX operation and receive
} }
return 12500; }
return 1000;
case DSM_RX_BIND2: case DSM_RX_BIND2:
//Transmit settings back //Transmit settings back
CYRF_WriteDataPacketLen(packet,10); // Does not work ?!?!? CYRF_WriteDataPacketLen(packet,10); // Send packet
if(bind_counter--==0) if(bind_counter--==0)
{ {
BIND_DONE; BIND_DONE;
@ -296,7 +310,6 @@ uint16_t DSM_Rx_callback()
hopping_frequency_no = 0; hopping_frequency_no = 0;
read_retry=0; read_retry=0;
rx_data_started = false; rx_data_started = false;
read_retry=0;
pps_counter = 0; pps_counter = 0;
RX_LQI = 100; RX_LQI = 100;
DSM_cyrf_configdata(); DSM_cyrf_configdata();
@ -457,7 +470,10 @@ uint16_t initDSM_Rx()
hopping_frequency_no = 0; hopping_frequency_no = 0;
if (IS_BIND_IN_PROGRESS) if (IS_BIND_IN_PROGRESS)
{
packet_count=0;
phase = DSM_RX_BIND1; phase = DSM_RX_BIND1;
}
else else
{ {
uint16_t temp = DSM_RX_EEPROM_OFFSET; uint16_t temp = DSM_RX_EEPROM_OFFSET;
@ -471,7 +487,7 @@ uint16_t initDSM_Rx()
debugln(", type=%02X", DSM_rx_type); debugln(", type=%02X", DSM_rx_type);
phase = DSM_RX_DATA_PREP; phase = DSM_RX_DATA_PREP;
} }
return 1000; return 15000;
} }
#endif #endif

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@ -230,7 +230,7 @@ uint16_t ReadDsm()
#if defined DSM_TELEMETRY #if defined DSM_TELEMETRY
case DSM_BIND_CHECK: case DSM_BIND_CHECK:
//64 SDR Mode is configured so only the 8 first values are needed but we need to write 16 values... //64 SDR Mode is configured so only the 8 first values are needed but we need to write 16 values...
CYRF_ConfigDataCode((const uint8_t *)"\x98\x88\x1B\xE4\x30\x79\x03\x84\xC9\x2C\x06\x93\x86\xB9\x9E\xD7", 16); CYRF_ConfigDataCode((const uint8_t *)"\x98\x88\x1B\xE4\x30\x79\x03\x84", 16);
CYRF_SetTxRxMode(RX_EN); //Receive mode CYRF_SetTxRxMode(RX_EN); //Receive mode
CYRF_WriteRegister(CYRF_05_RX_CTRL, 0x87); //Prepare to receive CYRF_WriteRegister(CYRF_05_RX_CTRL, 0x87); //Prepare to receive
bind_counter=2*DSM_BIND_COUNT; //Timeout of 4.2s if no packet received bind_counter=2*DSM_BIND_COUNT; //Timeout of 4.2s if no packet received
@ -255,6 +255,10 @@ uint16_t ReadDsm()
return 2000; return 2000;
} }
} }
CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x20); // Abort RX operation
CYRF_SetTxRxMode(RX_EN); // Force end state read
CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x00); // Clear abort RX operation
CYRF_WriteRegister(CYRF_05_RX_CTRL, 0x83); // Prepare to receive
} }
else else
if((rx_phase & 0x02) != 0x02) if((rx_phase & 0x02) != 0x02)

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@ -19,7 +19,7 @@
#define VERSION_MAJOR 1 #define VERSION_MAJOR 1
#define VERSION_MINOR 3 #define VERSION_MINOR 3
#define VERSION_REVISION 0 #define VERSION_REVISION 0
#define VERSION_PATCH_LEVEL 98 #define VERSION_PATCH_LEVEL 99
//****************** //******************
// Protocols // Protocols

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@ -674,10 +674,9 @@ Also on er9x you will need to be sure to match the polarity of the telemetry ser
The DSM receiver protocol enables master/slave trainning, separate access from 2 different radios to the same model,... The DSM receiver protocol enables master/slave trainning, separate access from 2 different radios to the same model,...
Notes: Notes:
- Automatically support DSM 2/X 11/22 1024/2048 - Automatically detect DSM 2/X 11/22ms 1024/2048res
- Currently the bind response does not work which means that the TX doesn't know what the DSM RX protocol has selected. **You must manually select the right protocol on the TX**. By default the RX will select DSMX/11ms. - Available in OpenTX 2.3.3+, Trainer Mode Master/Multi
- Available in OpenTX 2.3.3, Trainer Mode Master/Multi - Channels 1..4 are remapped to the module default channel order unless on OpenTX 2.3.3+ you use the "Disable channel mapping" feature on the GUI.
- Channels 1..4 are remapped to the module default
- Extended limits supported - Extended limits supported
CH1|CH2|CH3|CH4|CH5|CH6|CH7|CH8|CH9|CH10|CH11|CH12 CH1|CH2|CH3|CH4|CH5|CH6|CH7|CH8|CH9|CH10|CH11|CH12