mirror of
https://github.com/pascallanger/DIY-Multiprotocol-TX-Module.git
synced 2025-02-04 20:38:14 +00:00
FrSky 1way protocol + cosmetic
This commit is contained in:
pascallanger
parent
eabfd8b5c4
commit
7b65233699
@ -23,12 +23,12 @@
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void A7105_WriteData(uint8_t len, uint8_t channel)
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{
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uint8_t i;
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CS_off;
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A7105_CS_off;
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SPI_Write(A7105_RST_WRPTR);
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SPI_Write(0x05);
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for (i = 0; i < len; i++)
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SPI_Write(packet[i]);
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CS_on;
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A7105_CS_on;
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A7105_WriteReg(0x0F, channel);
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A7105_Strobe(A7105_TX);
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}
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@ -36,27 +36,27 @@ void A7105_WriteData(uint8_t len, uint8_t channel)
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void A7105_ReadData() {
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uint8_t i;
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A7105_Strobe(0xF0); //A7105_RST_RDPTR
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CS_off;
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A7105_CS_off;
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SPI_Write(0x45);
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for (i=0;i<16;i++)
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packet[i]=A7105_Read();
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CS_on;
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A7105_CS_on;
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}
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void A7105_WriteReg(uint8_t address, uint8_t data) {
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CS_off;
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A7105_CS_off;
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SPI_Write(address);
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NOP();
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SPI_Write(data);
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CS_on;
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A7105_CS_on;
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}
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uint8_t A7105_ReadReg(uint8_t address) {
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uint8_t result;
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CS_off;
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A7105_CS_off;
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SPI_Write(address |=0x40); //bit 6 =1 for reading
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result = A7105_Read();
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CS_on;
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A7105_CS_on;
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return(result);
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}
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@ -110,13 +110,13 @@ uint8_t A7105_Reset()
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}
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void A7105_WriteID(uint32_t ida) {
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CS_off;
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A7105_CS_off;
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SPI_Write(0x06);//ex id=0x5475c52a ;txid3txid2txid1txid0
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SPI_Write((ida>>24)&0xff);//53
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SPI_Write((ida>>16)&0xff);//75
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SPI_Write((ida>>8)&0xff);//c5
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SPI_Write((ida>>0)&0xff);//2a
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CS_on;
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A7105_CS_on;
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}
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/*
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@ -162,9 +162,9 @@ void A7105_SetPower()
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}
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void A7105_Strobe(uint8_t address) {
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CS_off;
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A7105_CS_off;
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SPI_Write(address);
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CS_on;
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A7105_CS_on;
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}
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const uint8_t PROGMEM HUBSAN_A7105_regs[] = {
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185
Multiprotocol/FrSky1_cc2500.ino
Normal file
185
Multiprotocol/FrSky1_cc2500.ino
Normal file
@ -0,0 +1,185 @@
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/*
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This project is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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Multiprotocol is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Multiprotocol. If not, see <http://www.gnu.org/licenses/>.
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*/
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#if defined(FRSKY1_CC2500_INO)
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#include "iface_cc2500.h"
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static void __attribute__((unused)) FRSKY1_init()
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{
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CC2500_WriteReg(CC2500_17_MCSM1, 0x0c);
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CC2500_WriteReg(CC2500_18_MCSM0, 0x18);
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CC2500_WriteReg(CC2500_06_PKTLEN, 0xff);
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CC2500_WriteReg(CC2500_07_PKTCTRL1, 0x04);
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CC2500_WriteReg(CC2500_08_PKTCTRL0, 0x05);
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CC2500_WriteReg(CC2500_3E_PATABLE, 0xfe);
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CC2500_WriteReg(CC2500_0B_FSCTRL1, 0x08);
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CC2500_WriteReg(CC2500_0C_FSCTRL0, option);
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CC2500_WriteReg(CC2500_0D_FREQ2, 0x5c);
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CC2500_WriteReg(CC2500_0E_FREQ1, 0x58);
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CC2500_WriteReg(CC2500_0F_FREQ0, 0x9d);
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CC2500_WriteReg(CC2500_10_MDMCFG4, 0xaa);
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CC2500_WriteReg(CC2500_11_MDMCFG3, 0x10);
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CC2500_WriteReg(CC2500_12_MDMCFG2, 0x93);
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CC2500_WriteReg(CC2500_13_MDMCFG1, 0x23);
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CC2500_WriteReg(CC2500_14_MDMCFG0, 0x7a);
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CC2500_WriteReg(CC2500_15_DEVIATN, 0x41);
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for(uint8_t i=19;i<36;i++)
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{
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uint8_t reg=pgm_read_byte_near(&cc2500_conf[i][0]);
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uint8_t val=pgm_read_byte_near(&cc2500_conf[i][1]);
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CC2500_WriteReg(reg,val);
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}
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CC2500_SetTxRxMode(TX_EN);
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CC2500_SetPower();
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CC2500_Strobe(CC2500_SIDLE); // Go to idle...
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prev_option = option ;
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}
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static uint8_t __attribute__((unused)) FRSKY1_crc8(uint8_t result, uint8_t *data, uint8_t len, uint8_t polynomial)
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{
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for(uint8_t i = 0; i < len; i++)
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{
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result = result ^ data[i];
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for(uint8_t j = 0; j < 8; j++)
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if(result & 0x80)
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result = (result << 1) ^ polynomial;
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else
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result = result << 1;
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}
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return result;
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}
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static uint8_t __attribute__((unused)) FRSKY1_crc8_le(uint8_t init, u8 *data, uint8_t len)
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{
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uint8_t result = 0;
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for(uint8_t i = 0; i < 8; i++)
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{
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result = (result << 1) | (init & 0x01);
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init >>= 1;
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}
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return FRSKY1_crc8(result,data,len,0x83);
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}
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static void __attribute__((unused)) FRSKY1_build_bind_packet()
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{
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//0e 03 01 57 12 00 06 0b 10 15 1a 00 00 00 61
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packet[0] = 0x0e; //Length
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packet[1] = 0x03; //Packet type
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packet[2] = 0x01; //Packet type
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packet[3] = rx_tx_addr[3];
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packet[4] = rx_tx_addr[2];
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packet[5] = ((state - FRSKY_BIND) % 10) * 5;
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packet[6] = packet[5] * 5 + 6;
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packet[7] = packet[5] * 5 + 11;
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packet[8] = packet[5] * 5 + 16;
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packet[9] = packet[5] * 5 + 21;
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packet[10] = packet[5] * 5 + 26;
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packet[11] = 0x00;
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packet[12] = 0x00;
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packet[13] = 0x00;
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packet[14] = FRSKY1_crc8(0x93, packet, 14, 0x07);
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}
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static uint8_t __attribute__((unused)) FRSKY1_calc_channel()
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{
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uint32_t temp=seed;
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temp = (temp * 0xaa) % 0x7673;
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seed = temp;
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return (seed & 0xff) % 0x32;
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}
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static void __attribute__((unused)) FRSKY1_build_data_packet()
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{
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packet[0] = 0x0e;
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packet[1] = rx_tx_addr[3];
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packet[2] = rx_tx_addr[2];
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packet[3] = seed & 0xff;
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packet[4] = seed >> 8;
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if (state == FRSKY_DATA1 || state == FRSKY_DATA3)
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packet[5] = 0x0f;
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else
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if(state == FRSKY_DATA2 || state == FRSKY_DATA4)
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packet[5] = 0xf0;
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else
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packet[5] = 0x00;
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uint8_t idx = 0; //= (state == FRSKY_DATA1) ? 4 : 0;
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for(uint8_t i = 0; i < 4; i++)
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{
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uint16_t value = convert_channel_frsky(i+idx);
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packet[2*i + 6] = value & 0xff;
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packet[2*i + 7] = value >> 8;
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}
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packet[14] = FRSKY1_crc8(crc8, packet, 14, 0x07);
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}
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static uint16_t ReadFRSKY1()
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{
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if (state < FRSKY_BIND_DONE)
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{
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FRSKY1_build_bind_packet();
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CC2500_Strobe(CC2500_SIDLE);
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CC2500_WriteReg(CC2500_0A_CHANNR, 0x00);
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CC2500_WriteData(packet, packet[0]+1);
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state++;
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return 53460;
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}
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if (state == FRSKY_BIND_DONE)
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{
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state++;
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BIND_DONE;
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}
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if (state >= FRSKY_DATA1)
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{
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CC2500_Strobe(CC2500_SIDLE);
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if (option != prev_option)
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{
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CC2500_WriteReg(CC2500_0C_FSCTRL0, option);
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prev_option=option;
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}
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uint8_t chan = FRSKY1_calc_channel();
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CC2500_WriteReg(CC2500_0A_CHANNR, chan * 5 + 6);
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FRSKY1_build_data_packet();
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CC2500_WriteData(packet, packet[0]+1);
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if (state == FRSKY_DATA5)
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{
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CC2500_SetPower();
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state = FRSKY_DATA1;
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}
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else
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state++;
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return 9006;
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}
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return 0;
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}
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uint16_t initFRSKY1()
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{
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//u8 data[2] = {(fixed_id >> 8) & 0xff, fixed_id & 0xff};
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crc8 = FRSKY1_crc8_le(0x6b, rx_tx_addr+2, 2); // Use rx_tx_addr[2] and rx_tx_addr[3] since we want to use RX_Num
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FRSKY1_init();
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seed = 1;
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if(IS_AUTOBIND_FLAG_on)
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state = FRSKY_BIND;
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else
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state = FRSKY_DATA1;
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return 10000;
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}
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#endif
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@ -17,26 +17,9 @@
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#include "iface_cc2500.h"
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//##########Variables########
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//uint32_t state;
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//uint8_t len;
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/*
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enum {
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FRSKY_BIND = 0,
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FRSKY_BIND_DONE = 1000,
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FRSKY_DATA1,
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FRSKY_DATA2,
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FRSKY_DATA3,
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FRSKY_DATA4,
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FRSKY_DATA5
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};
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*/
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static void __attribute__((unused)) frsky2way_init(uint8_t bind)
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{
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// Configure cc2500 for tx mode
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CC2500_Reset();
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//
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for(uint8_t i=0;i<36;i++)
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{
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@ -144,7 +127,7 @@ uint16_t initFrSky_2way()
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if(IS_AUTOBIND_FLAG_on)
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{
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frsky2way_init(1);
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state = FRSKY_BIND;//
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state = FRSKY_BIND;
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}
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else
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{
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@ -52,7 +52,8 @@ enum PROTOCOLS
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MODE_SFHSS = 21, // =>CC2500
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MODE_J6PRO = 22, // =>CYRF6936
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MODE_FQ777 = 23, // =>NRF24L01
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MODE_ASSAN = 24 // =>NRF24L01
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MODE_ASSAN = 24, // =>NRF24L01
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MODE_FRSKY1 = 25 // =>CC2500
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};
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enum Flysky
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@ -148,21 +149,22 @@ struct PPM_Parameters
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//*******************
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//*** Pinouts ***
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//*******************
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#define LED_pin 13 //Promini original led on B5
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#define PPM_pin 3 //PPM-D3
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#define LED_pin 5 //D13 = PB5
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#define BIND_pin 5 //D13 = PB5
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#define PPM_pin 3 //D3 = PD3
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#ifdef XMEGA
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#define SDI_pin 6 //SDIO-D6
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#else
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#define SDI_pin 5 //SDIO-D5
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#define SDI_pin 5 //D5 = PD5
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#endif
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#define SCLK_pin 4 //SCK-D4
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#define CS_pin 2 //CS-D2
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#define SDO_pin 6 //D6
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#define CC25_CSN_pin 7
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#define NRF_CSN_pin 8
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#define CYRF_CSN_pin 9
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#define CTRL1 1 //C1 (A1)
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#define CTRL2 2 //C2 (A2)
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#define SCLK_pin 4 //D4 = PD4
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#define A7105_CS_pin 2 //D2 = PD2
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#define SDO_pin 6 //D6 = PD6
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#define CC25_CSN_pin 7 //D7 = PD7
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#define NRF_CSN_pin 0 //D8 = PB0
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#define CYRF_CSN_pin 1 //D9 = PB1
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#define CTRL1_pin 1 //A1 = PC1
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#define CTRL2_pin 2 //A2 = PC2
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//
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#ifdef XMEGA
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#define CTRL1_on
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@ -177,11 +179,11 @@ struct PPM_Parameters
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#endif
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//
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#ifdef XMEGA
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#define CS_on PORTD.OUTSET = _BV(4) //D4
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#define CS_off PORTD.OUTCLR = _BV(4) //D4
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#define A7105_CS_on PORTD.OUTSET = _BV(4) //D4
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#define A7105_CS_off PORTD.OUTCLR = _BV(4) //D4
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#else
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#define CS_on PORTD |= _BV(2) //D2
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#define CS_off PORTD &= ~_BV(2) //D2
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#define A7105_CS_on PORTD |= _BV(2) //D2
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#define A7105_CS_off PORTD &= ~_BV(2) //D2
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#endif
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//
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#ifdef XMEGA
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@ -201,11 +203,11 @@ struct PPM_Parameters
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#endif
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//
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#ifdef XMEGA
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#define SDI_1 (PORTD.IN & (1<<SDI_pin)) == (1<<SDI_pin) //D5
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#define SDI_0 (PORTD.IN & (1<<SDI_pin)) == 0x00 //D5
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#define SDI_1 (PORTD.IN & _BV(SDI_pin)) == _BV(SDI_pin) //D5
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#define SDI_0 (PORTD.IN & _BV(SDI_pin)) == 0x00 //D5
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#else
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#define SDI_1 (PIND & (1<<SDI_pin)) == (1<<SDI_pin) //D5
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#define SDI_0 (PIND & (1<<SDI_pin)) == 0x00 //D5
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#define SDI_1 (PIND & _BV(SDI_pin)) == _BV(SDI_pin) //D5
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#define SDI_0 (PIND & _BV(SDI_pin)) == 0x00 //D5
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#endif
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//
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#define SDI_SET_INPUT DDRD &= ~_BV(5) //D5
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@ -230,19 +232,21 @@ struct PPM_Parameters
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#ifdef XMEGA
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#define CYRF_CSN_on PORTD.OUTSET = _BV(4)
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#define CYRF_CSN_off PORTD.OUTCLR = _BV(4)
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#define CYRF_RST 0
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#else
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#define CYRF_CSN_on PORTB |= _BV(1) //D9
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#define CYRF_CSN_off PORTB &= ~_BV(1) //D9
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#define CYRF_RST_HI PORTC |= _BV(5) //A5
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#define CYRF_RST_LO PORTC &= ~_BV(5) //A5
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#define CYRF_RST 5
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#endif
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//
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#ifdef XMEGA
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#define SDO_1 (PORTD.IN & (1<<SDO_pin)) == (1<<SDO_pin) //D6
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#define SDO_0 (PORTD.IN & (1<<SDO_pin)) == 0x00 //D6
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#define SDO_1 (PORTD.IN & _BV(SDO_pin)) == _BV(SDO_pin) //D6
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#define SDO_0 (PORTD.IN & _BV(SDO_pin)) == 0x00 //D6
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#else
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#define SDO_1 (PIND & (1<<SDO_pin)) == (1<<SDO_pin) //D6
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#define SDO_0 (PIND & (1<<SDO_pin)) == 0x00 //D6
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#define SDO_1 (PIND & _BV(SDO_pin)) == _BV(SDO_pin) //D6
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#define SDO_0 (PIND & _BV(SDO_pin)) == 0x00 //D6
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#endif
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//
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//
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@ -510,6 +514,7 @@ Serial: 100000 Baud 8e2 _ xxxx xxxx p --
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J6PRO 22
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FQ777 23
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ASSAN 24
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FRSKY1 25
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BindBit=> 0x80 1=Bind/0=No
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AutoBindBit=> 0x40 1=Yes /0=No
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RangeCheck=> 0x20 1=Yes /0=No
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@ -64,6 +64,8 @@ uint8_t rf_ch_num;
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uint8_t throttle, rudder, elevator, aileron;
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uint8_t flags;
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uint16_t crc;
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uint8_t crc8;
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uint16_t seed;
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//
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uint16_t state;
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uint8_t len;
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@ -148,16 +150,15 @@ void setup()
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PORTE.OUTCLR = 0x01 ;
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#else
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// General pinout
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DDRD = (1<<CS_pin)|(1<<SDI_pin)|(1<<SCLK_pin)|(1<<CS_pin)|(1<< CC25_CSN_pin);
|
||||
DDRC = (1<<CTRL1)|(1<<CTRL2); //output
|
||||
//DDRC |= (1<<5);//RST pin A5(C5) CYRF output
|
||||
DDRB = _BV(0)|_BV(1);
|
||||
PORTB = _BV(2)|_BV(3)|_BV(4)|_BV(5);//pullup 10,11,12 and bind button
|
||||
PORTC = _BV(0);//A0 high pullup
|
||||
DDRD = _BV(A7105_CS_pin)|_BV(SDI_pin)|_BV(SCLK_pin)|_BV( CC25_CSN_pin);//pin output
|
||||
DDRC = _BV(CTRL1_pin)|_BV(CTRL2_pin)|_BV(CYRF_RST); //pin output
|
||||
DDRB = _BV(NRF_CSN_pin)|_BV(CYRF_CSN_pin); //pin output
|
||||
PORTB = _BV(2)|_BV(3)|_BV(4)|_BV(BIND_pin); //pullup on dial (D10=PB2,D11=PB3,D12=PB4) and bind button
|
||||
PORTC = _BV(0); //pullup on dial (A0=PC0)
|
||||
#endif
|
||||
|
||||
// Set Chip selects
|
||||
CS_on;
|
||||
A7105_CS_on;
|
||||
CC25_CSN_on;
|
||||
NRF_CSN_on;
|
||||
CYRF_CSN_on;
|
||||
@ -237,8 +238,8 @@ void setup()
|
||||
|
||||
#ifndef XMEGA
|
||||
//Configure PPM interrupt
|
||||
EICRA |=(1<<ISC11); // The rising edge of INT1 pin D3 generates an interrupt request
|
||||
EIMSK |= (1<<INT1); // INT1 interrupt enable
|
||||
EICRA |=_BV(ISC11); // The rising edge of INT1 pin D3 generates an interrupt request
|
||||
EIMSK |= _BV(INT1); // INT1 interrupt enable
|
||||
#endif
|
||||
|
||||
#if defined(TELEMETRY)
|
||||
@ -285,14 +286,14 @@ void loop()
|
||||
else
|
||||
while((TCC1.INTFLAGS & TC1_CCAIF_bm) == 0); // wait before callback
|
||||
#else
|
||||
if( (TIFR1 & (1<<OCF1A)) != 0)
|
||||
if( (TIFR1 & _BV(OCF1A)) != 0)
|
||||
{
|
||||
cli(); // Disable global int due to RW of 16 bits registers
|
||||
OCR1A=TCNT1; // Callback should already have been called... Use "now" as new sync point.
|
||||
sei(); // Enable global int
|
||||
}
|
||||
else
|
||||
while((TIFR1 & (1<<OCF1A)) == 0); // Wait before callback
|
||||
while((TIFR1 & _BV(OCF1A)) == 0); // Wait before callback
|
||||
#endif
|
||||
do
|
||||
{
|
||||
@ -318,12 +319,12 @@ void loop()
|
||||
#else
|
||||
cli(); // Disable global int due to RW of 16 bits registers
|
||||
OCR1A += 2000*2 ; // set compare A for callback
|
||||
TIFR1=(1<<OCF1A); // clear compare A=callback flag
|
||||
TIFR1=_BV(OCF1A); // clear compare A=callback flag
|
||||
sei(); // enable global int
|
||||
Update_All();
|
||||
if(IS_CHANGE_PROTOCOL_FLAG_on)
|
||||
break; // Protocol has been changed
|
||||
while((TIFR1 & (1<<OCF1A)) == 0); // wait 2ms...
|
||||
while((TIFR1 & _BV(OCF1A)) == 0); // wait 2ms...
|
||||
#endif
|
||||
}
|
||||
// at this point we have a maximum of 4ms in next_callback
|
||||
@ -337,7 +338,7 @@ void loop()
|
||||
#else
|
||||
cli(); // Disable global int due to RW of 16 bits registers
|
||||
OCR1A+= next_callback ; // set compare A for callback
|
||||
TIFR1=(1<<OCF1A); // clear compare A=callback flag
|
||||
TIFR1=_BV(OCF1A); // clear compare A=callback flag
|
||||
diff=OCR1A-TCNT1; // compare timer and comparator
|
||||
sei(); // enable global int
|
||||
#endif
|
||||
@ -434,7 +435,7 @@ inline void tx_pause()
|
||||
USARTC0.CTRLA &= ~0x03 ; // Pause telemetry by disabling transmitter interrupt
|
||||
#else
|
||||
#ifndef BASH_SERIAL
|
||||
UCSR0B &= ~(1<<UDRIE0); // Pause telemetry by disabling transmitter interrupt
|
||||
UCSR0B &= ~_BV(UDRIE0); // Pause telemetry by disabling transmitter interrupt
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
@ -447,7 +448,7 @@ inline void tx_resume()
|
||||
#ifdef XMEGA
|
||||
USARTC0.CTRLA = (USARTC0.CTRLA & 0xFC) | 0x01 ; // Resume telemetry by enabling transmitter interrupt
|
||||
#else
|
||||
UCSR0B |= (1<<UDRIE0); // Resume telemetry by enabling transmitter interrupt
|
||||
UCSR0B |= _BV(UDRIE0); // Resume telemetry by enabling transmitter interrupt
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
@ -505,6 +506,14 @@ static void protocol_init()
|
||||
remote_callback = ReadFrSky_2way;
|
||||
break;
|
||||
#endif
|
||||
#if defined(FRSKY1_CC2500_INO)
|
||||
case MODE_FRSKY1:
|
||||
CTRL1_off; //antenna RF2
|
||||
CTRL2_on;
|
||||
next_callback = initFRSKY1();
|
||||
remote_callback = ReadFRSKY1;
|
||||
break;
|
||||
#endif
|
||||
#if defined(FRSKYX_CC2500_INO)
|
||||
case MODE_FRSKYX:
|
||||
CTRL1_off; //antenna RF2
|
||||
@ -670,7 +679,7 @@ static void protocol_init()
|
||||
#else
|
||||
OCR1A=TCNT1+next_callback*2; // set compare A for callback
|
||||
sei(); // enable global int
|
||||
TIFR1=(1<<OCF1A); // clear compare A flag
|
||||
TIFR1=_BV(OCF1A); // clear compare A flag
|
||||
#endif
|
||||
BIND_BUTTON_FLAG_off; // do not bind/reset id anymore even if protocol change
|
||||
}
|
||||
@ -728,7 +737,7 @@ void update_serial_data()
|
||||
#ifdef XMEGA
|
||||
cli();
|
||||
#else
|
||||
UCSR0B &= ~(1<<RXCIE0); // RX interrupt disable
|
||||
UCSR0B &= ~_BV(RXCIE0); // RX interrupt disable
|
||||
#endif
|
||||
if(IS_RX_MISSED_BUFF_on) // If the buffer is still valid
|
||||
{ memcpy((void*)rx_ok_buff,(const void*)rx_buff,RXBUFFER_SIZE);// Duplicate the buffer
|
||||
@ -738,7 +747,7 @@ void update_serial_data()
|
||||
#ifdef XMEGA
|
||||
sei();
|
||||
#else
|
||||
UCSR0B |= (1<<RXCIE0) ; // RX interrupt enable
|
||||
UCSR0B |= _BV(RXCIE0) ; // RX interrupt enable
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -847,11 +856,11 @@ void Mprotocol_serial_init()
|
||||
UBRR0L = UBRRL_VALUE;
|
||||
UCSR0A = 0 ; // Clear X2 bit
|
||||
//Set frame format to 8 data bits, even parity, 2 stop bits
|
||||
UCSR0C = (1<<UPM01)|(1<<USBS0)|(1<<UCSZ01)|(1<<UCSZ00);
|
||||
UCSR0C = _BV(UPM01)|_BV(USBS0)|_BV(UCSZ01)|_BV(UCSZ00);
|
||||
while ( UCSR0A & (1 << RXC0) )//flush receive buffer
|
||||
UDR0;
|
||||
//enable reception and RC complete interrupt
|
||||
UCSR0B = (1<<RXEN0)|(1<<RXCIE0);//rx enable and interrupt
|
||||
UCSR0B = _BV(RXEN0)|_BV(RXCIE0);//rx enable and interrupt
|
||||
#ifdef DEBUG_TX
|
||||
TX_SET_OUTPUT;
|
||||
#else
|
||||
@ -1104,7 +1113,7 @@ ISR(USART_RX_vect)
|
||||
#ifdef XMEGA
|
||||
if((USARTC0.STATUS & 0x1C)==0) // Check frame error, data overrun and parity error
|
||||
#else
|
||||
UCSR0B &= ~(1<<RXCIE0) ; // RX interrupt disable
|
||||
UCSR0B &= ~_BV(RXCIE0) ; // RX interrupt disable
|
||||
sei() ;
|
||||
if((UCSR0A&0x1C)==0) // Check frame error, data overrun and parity error
|
||||
#endif
|
||||
@ -1126,8 +1135,8 @@ ISR(USART_RX_vect)
|
||||
TCC1.INTCTRLB = (TCC1.INTCTRLB & 0xF3) | 0x04 ; // enable interrupt on compare B match
|
||||
#else
|
||||
OCR1B=TCNT1+6500L; // Full message should be received within timer of 3250us
|
||||
TIFR1=(1<<OCF1B); // clear OCR1B match flag
|
||||
TIMSK1 |=(1<<OCIE1B); // enable interrupt on compare B match
|
||||
TIFR1=_BV(OCF1B); // clear OCR1B match flag
|
||||
TIMSK1 |=_BV(OCIE1B); // enable interrupt on compare B match
|
||||
#endif
|
||||
idx++;
|
||||
}
|
||||
@ -1167,14 +1176,14 @@ ISR(USART_RX_vect)
|
||||
#ifdef XMEGA
|
||||
TCC1.INTCTRLB &=0xF3; // Disable interrupt on compare B match
|
||||
#else
|
||||
TIMSK1 &=~(1<<OCIE1B); // Disable interrupt on compare B match
|
||||
TIMSK1 &=~_BV(OCIE1B); // Disable interrupt on compare B match
|
||||
#endif
|
||||
TX_RX_PAUSE_off;
|
||||
tx_resume();
|
||||
}
|
||||
#ifndef XMEGA
|
||||
cli() ;
|
||||
UCSR0B |= (1<<RXCIE0) ; // RX interrupt enable
|
||||
UCSR0B |= _BV(RXCIE0) ; // RX interrupt enable
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -1190,7 +1199,7 @@ ISR(TIMER1_COMPB_vect, ISR_NOBLOCK )
|
||||
#ifdef XMEGA
|
||||
TCC1.INTCTRLB &=0xF3; // Disable interrupt on compare B match
|
||||
#else
|
||||
TIMSK1 &=~(1<<OCIE1B); // Disable interrupt on compare B match
|
||||
TIMSK1 &=~_BV(OCIE1B); // Disable interrupt on compare B match
|
||||
#endif
|
||||
tx_resume();
|
||||
}
|
||||
|
||||
@ -50,6 +50,7 @@
|
||||
#endif
|
||||
#ifdef CC2500_INSTALLED
|
||||
#define FRSKY_CC2500_INO
|
||||
#define FRSKY1_CC2500_INO
|
||||
#define FRSKYX_CC2500_INO
|
||||
#define SFHSS_CC2500_INO
|
||||
#endif
|
||||
@ -238,6 +239,8 @@ const PPM_Parameters PPM_prot[15]= {
|
||||
NONE
|
||||
MODE_ASSAN
|
||||
NONE
|
||||
MODE_FRSKY1
|
||||
NONE
|
||||
*/
|
||||
|
||||
// RX_Num is used for model match. Using RX_Num values different for each receiver will prevent starting a model with the false config loaded...
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user