mirror of
https://github.com/pascallanger/DIY-Multiprotocol-TX-Module.git
synced 2025-02-04 18:48:11 +00:00
initial working version of R9M, 8 CH and BINDING support only
This commit is contained in:
Tomer Abramovich
parent
7281c0b5bf
commit
77bf17967d
@ -17,7 +17,7 @@
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/** FrSky D and X routines **/
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/******************************/
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#if defined(FRSKYX_CC2500_INO) || defined(FRSKY_RX_CC2500_INO)
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#if defined(FRSKYX_CC2500_INO) || defined(FRSKY_RX_CC2500_INO) || defined(FRSKYR9_SX1276_INO)
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//**CRC**
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const uint16_t PROGMEM FrSkyX_CRC_Short[]={
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0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF,
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238
Multiprotocol/FrSkyR9_sx1276.ino
Normal file
238
Multiprotocol/FrSkyR9_sx1276.ino
Normal file
@ -0,0 +1,238 @@
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#if defined(FRSKYR9_SX1276_INO)
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#define REG_IRQ_FLAGS_MASK 0x11
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#define REG_PAYLOAD_LENGTH 0x22
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#define REG_FIFO_ADDR_PTR 0x0D
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#define REG_FIFO_TX_BASE_ADDR 0x0E
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#define REG_OP_MODE 0x01
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#define REG_DETECT_OPTIMIZE 0x31
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#define REG_DIO_MAPPING1 0x40
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#define REG_VERSION 0x42
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#define REG_MODEM_CONFIG1 0x1D
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#define REG_MODEM_CONFIG2 0x1E
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#define REG_MODEM_CONFIG3 0x26
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#define REG_PREAMBLE_LSB 0x21
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#define REG_DETECTION_THRESHOLD 0x37
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#define REG_LNA 0x0C
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#define REG_HOP_PERIOD 0x24
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#define REG_PA_DAC 0x4D
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#define REG_PA_CONFIG 0x09
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#define REG_FRF_MSB 0x06
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#define REG_FIFO 0x00
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#define REG_OCP 0x0B
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static uint32_t _freq_map[] =
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{
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914472960,
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914972672,
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915472384,
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915972096,
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916471808,
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916971520,
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917471232,
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917970944,
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918470656,
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918970368,
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919470080,
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919969792,
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920469504,
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920969216,
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921468928,
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921968640,
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922468352,
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922968064,
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923467776,
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923967488,
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924467200,
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924966912,
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925466624,
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925966336,
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926466048,
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926965760,
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927465472,
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// last two determined by _step
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0,
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0
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};
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static uint8_t _step = 1;
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static uint16_t __attribute__((unused)) FrSkyX_scaleForPXX_temp( uint8_t i )
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{ //mapped 860,2140(125%) range to 64,1984(PXX values);
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uint16_t chan_val=convert_channel_frsky(i)-1226;
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if(i>7) chan_val|=2048; // upper channels offset
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return chan_val;
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}
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uint16_t initFrSkyR9()
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{
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set_rx_tx_addr(MProtocol_id_master);
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_step = 1 + (random(0xfefefefe) % 24);
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_freq_map[27] = _freq_map[_step];
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_freq_map[28] = _freq_map[_step+1];
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SX1276_WriteReg(REG_OP_MODE, 0x80); // sleep
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SX1276_WriteReg(REG_OP_MODE, 0x81); // standby
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uint8_t buffer[2];
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buffer[0] = 0x00;
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buffer[1] = 0x00;
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SX1276_WriteRegisterMulti(REG_DIO_MAPPING1, buffer, 2);
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uint8_t val = SX1276_ReadReg(REG_DETECT_OPTIMIZE);
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val = (val & 0b11111000) | 0b00000101;
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SX1276_WriteReg(REG_DETECT_OPTIMIZE, val);
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// val = SX1276_ReadReg(REG_MODEM_CONFIG2);
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// val = (val & 0b00011111) | 0b11000000;
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// writeRegister(REG_MODEM_CONFIG2, val);
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SX1276_WriteReg(REG_MODEM_CONFIG1, 0x93);
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SX1276_WriteReg(REG_MODEM_CONFIG2, 0x60);
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val = SX1276_ReadReg(REG_MODEM_CONFIG3);
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val = (val & 0b11110011);
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SX1276_WriteReg(REG_MODEM_CONFIG3, val);
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SX1276_WriteReg(REG_PREAMBLE_LSB, 9);
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SX1276_WriteReg(REG_DETECTION_THRESHOLD, 0x0C);
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SX1276_WriteReg(REG_LNA, 0x23);
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SX1276_WriteReg(REG_HOP_PERIOD, 0x00);
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val = SX1276_ReadReg(REG_PA_DAC);
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val = (val & 0b11111000) | 0b00000111;
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SX1276_WriteReg(REG_PA_DAC, val);
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// TODO this can probably be shorter
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return 20000; // start calling FrSkyR9_callback in 20 milliseconds
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}
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uint16_t FrSkyR9_callback()
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{
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static uint16_t index = 0;
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uint8_t buffer[3];
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SX1276_WriteReg(REG_OP_MODE, 0x81); // STDBY
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SX1276_WriteReg(REG_IRQ_FLAGS_MASK, 0xbf); // use only RxDone interrupt
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buffer[0] = 0x00;
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buffer[1] = 0x00;
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SX1276_WriteRegisterMulti(REG_DIO_MAPPING1, buffer, 2); // RxDone interrupt mapped to DIO0 (the rest are not used because of the REG_IRQ_FLAGS_MASK)
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// SX1276_WriteReg(REG_PAYLOAD_LENGTH, 13);
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// SX1276_WriteReg(REG_FIFO_ADDR_PTR, 0x00);
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// SX1276_WriteReg(REG_OP_MODE, 0x85); // RXCONTINUOUS
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// delay(10); // 10 ms
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// SX1276_WriteReg(REG_OP_MODE, 0x81); // STDBY
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SX1276_WriteReg(REG_PA_CONFIG, 0xF0);
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uint32_t freq = _freq_map[index] / 61;
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buffer[0] = (freq & (0xFF << 16)) >> 16;
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buffer[1] = (freq & (0xFF << 8)) >> 8;
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buffer[2] = freq & 0xFF;
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SX1276_WriteRegisterMulti(REG_FRF_MSB, buffer, 3); // set current center frequency
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delayMicroseconds(500);
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SX1276_WriteReg(REG_PAYLOAD_LENGTH, 26);
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SX1276_WriteReg(REG_FIFO_TX_BASE_ADDR, 0x00);
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SX1276_WriteReg(REG_FIFO_ADDR_PTR, 0x00);
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uint8_t payload[26];
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payload[0] = 0x3C; // ????
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payload[1] = rx_tx_addr[3]; // unique radio id
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payload[2] = rx_tx_addr[2]; // unique radio id
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payload[3] = index; // current channel index
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payload[4] = _step; // step size and last 2 channels start index
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payload[5] = RX_num; // receiver number from OpenTX
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// binding mode: 0x00 regular / 0x41 bind?
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if(IS_BIND_IN_PROGRESS)
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payload[6] = 0x41;
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else
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payload[6] = 0x00;
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// TODO
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payload[7] = 0x00; // fail safe related (looks like the same sequence of numbers as FrskyX protocol)
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// two channel are spread over 3 bytes.
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// each channel is 11 bit + 1 bit (msb) that states whether
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// it's part of the upper channels (9-16) or lower (1-8) (0 - lower 1 - upper)
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const int payload_offset = 8;
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const bool is_upper = false;
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int chan_index = 0;
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for(int i = 0; i < 8; i += 3)
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{
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// map channel values (0-2047) to (64-1984)
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uint16_t ch1 = 64 + (uint16_t)((1920.0f / 2047.0f) * Channel_data[chan_index]);
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uint16_t ch2 = 64 + (uint16_t)((1920.0f / 2047.0f) * Channel_data[chan_index + 1]);
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chan_index += 2;
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payload[payload_offset + i] = ch1;
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if(is_upper)
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{
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payload[payload_offset + i + 1] = ((ch1 >> 8) | 0b1000) | (ch2 << 4);
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payload[payload_offset + i + 2] = (ch2 >> 4) | 0b10000000;
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}
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else
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{
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payload[payload_offset + i + 1] = ((ch1 >> 8) & 0b0111) | (ch2 << 4);
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payload[payload_offset + i + 2] = (ch2 >> 4) & 0b01111111;
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}
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}
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payload[20] = 0x08; // ????
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payload[21] = 0x00; // ????
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payload[22] = 0x00; // ????
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payload[23] = 0x00; // ????
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uint16_t crc = FrSkyX_crc(payload, 24);
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payload[24] = crc; // low byte
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payload[25] = crc >> 8; // high byte
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// write payload to fifo
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SX1276_WriteRegisterMulti(REG_FIFO, payload, 26);
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index = (index + _step) % 29;
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SX1276_WriteReg(REG_OP_MODE, 0x83); // TX
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// need to clear RegIrqFlags?
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return 19400;
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}
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#endif
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@ -78,6 +78,7 @@ const char STR_PELIKAN[] ="Pelikan";
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const char STR_TIGER[] ="Tiger";
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const char STR_XK[] ="XK";
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const char STR_XN297DUMP[] ="XN297DP";
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const char STR_FRSKYR9[] ="FrSkyR9";
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const char STR_SUBTYPE_FLYSKY[] = "\x04""Std\0""V9x9""V6x6""V912""CX20";
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const char STR_SUBTYPE_HUBSAN[] = "\x04""H107""H301""H501";
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@ -118,6 +119,7 @@ const char STR_SUBTYPE_XN297DUMP[] = "\x07""250Kbps""1Mbps\0 ""2Mbps\0 ""Auto\0
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const char STR_SUBTYPE_ESKY150[] = "\x03""4CH""7CH";
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const char STR_SUBTYPE_V911S[] = "\x04""Std\0""E119";
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const char STR_SUBTYPE_XK[] = "\x04""X450""X420";
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const char STR_SUBTYPE_FRSKYR9[] = "\x07""915MHz\0""868MHz";
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enum
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{
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@ -324,6 +326,9 @@ const mm_protocol_definition multi_protocols[] = {
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#endif
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#if defined(XN297DUMP_NRF24L01_INO)
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{PROTO_XN297DUMP, STR_XN297DUMP, 4, STR_SUBTYPE_XN297DUMP, OPTION_RFCHAN },
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#endif
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#if defined(FRSKYR9_SX1276_INO)
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{PROTO_FRSKY_R9, STR_FRSKYR9, 2, STR_SUBTYPE_FRSKYR9, OPTION_NONE },
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#endif
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{0x00, nullptr, 0, nullptr, 0 }
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};
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@ -91,6 +91,7 @@ enum PROTOCOLS
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PROTO_XK = 62, // =>NRF24L01
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PROTO_XN297DUMP = 63, // =>NRF24L01
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PROTO_FRSKYX2 = 64, // =>CC2500
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PROTO_FRSKY_R9 = 65 // =>SX1276
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};
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enum Flysky
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@ -1504,6 +1504,14 @@ static void protocol_init()
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break;
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#endif
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#endif
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#ifdef SX1276_INSTALLED
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#if defined(FRSKYR9_SX1276_INO)
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case PROTO_FRSKY_R9:
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next_callback = initFrSkyR9();
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remote_callback = FrSkyR9_callback;
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break;
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#endif
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#endif
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}
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debugln("Protocol selected: %d, sub proto %d, rxnum %d, option %d", protocol, sub_protocol, RX_num, option);
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#ifdef MULTI_NAMES
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@ -1723,8 +1731,8 @@ void update_serial_data()
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else
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if( ((rx_ok_buff[1]&0x80)==0) && ((cur_protocol[1]&0x80)!=0) ) // Bind flag has been reset
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{ // Request protocol to end bind
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#if defined(FRSKYD_CC2500_INO) || defined(FRSKYX_CC2500_INO) || defined(FRSKYV_CC2500_INO) || defined(AFHDS2A_A7105_INO)
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if(protocol==PROTO_FRSKYD || protocol==PROTO_FRSKYX || protocol==PROTO_FRSKYV || protocol==PROTO_AFHDS2A )
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#if defined(FRSKYD_CC2500_INO) || defined(FRSKYX_CC2500_INO) || defined(FRSKYV_CC2500_INO) || defined(AFHDS2A_A7105_INO) || defined(FRSKYR9_SX1276_INO)
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if(protocol==PROTO_FRSKYD || protocol==PROTO_FRSKYX || protocol==PROTO_FRSKYV || protocol==PROTO_AFHDS2A || protocol==PROTO_FRSKY_R9 )
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BIND_DONE;
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else
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#endif
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@ -1871,6 +1879,9 @@ void modules_reset()
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#ifdef NRF24L01_INSTALLED
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NRF24L01_Reset();
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#endif
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#ifdef SX1276_INSTALLED
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SX1276_Reset();
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#endif
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//Wait for every component to reset
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delayMilliseconds(100);
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38
Multiprotocol/SX1276_SPI.ino
Normal file
38
Multiprotocol/SX1276_SPI.ino
Normal file
@ -0,0 +1,38 @@
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#ifdef SX1276_INSTALLED
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void SX1276_WriteReg(uint8_t address, uint8_t data)
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{
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SPI_CSN_off;
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SPI_Write(address | 0x80); // MSB 1 = write
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NOP();
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SPI_Write(data);
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SPI_CSN_on;
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}
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uint8_t SX1276_ReadReg(uint8_t address)
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{
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SPI_CSN_off;
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SPI_Write(address & 0b01111111);
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uint8_t result = SPI_Read();
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SPI_CSN_on;
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return result;
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}
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void SX1276_WriteRegisterMulti(uint8_t address, const uint8_t data[], uint8_t length)
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{
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SPI_CSN_off;
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SPI_Write(address | 0x80); // MSB 1 = write
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for(uint8_t i = 0; i < length; i++)
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SPI_Write(data[i]);
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SPI_CSN_on;
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}
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uint8_t SX1276_Reset()
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{
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//TODO
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return 0;
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}
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#endif
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@ -77,6 +77,7 @@
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#define CYRF6936_INSTALLED
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#define CC2500_INSTALLED
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#define NRF24L01_INSTALLED
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//#define SX1276_INSTALLED
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/** OrangeRX TX **/
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//If you compile for the OrangeRX TX module you need to select the correct board type.
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@ -223,6 +224,8 @@
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#define YD717_NRF24L01_INO
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#define ZSX_NRF24L01_INO
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//The protocols below need a SX1276 to be installed
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//#define FRSKYR9_SX1276_INO
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/***************************/
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/*** PROTOCOLS SETTINGS ***/
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