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https://github.com/pascallanger/DIY-Multiprotocol-TX-Module.git
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Fix Traxxas for any RX
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parent
e6bafaabb7
commit
7549783741
@ -20,6 +20,7 @@
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#include "iface_cyrf6936.h"
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#include "iface_cyrf6936.h"
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//#define TRAXXAS_FORCE_ID
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//#define TRAXXAS_FORCE_ID
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//#define TRAXXAS_DEBUG
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#define TRAXXAS_CHANNEL 0x05
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#define TRAXXAS_CHANNEL 0x05
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#define TRAXXAS_BIND_CHANNEL 0x2B
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#define TRAXXAS_BIND_CHANNEL 0x2B
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@ -65,8 +66,9 @@ static void __attribute__((unused)) TRAXXAS_cyrf_data_config()
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CYRF_WriteRegister(CYRF_15_CRC_SEED_LSB, 0x1B);
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CYRF_WriteRegister(CYRF_15_CRC_SEED_LSB, 0x1B);
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CYRF_WriteRegister(CYRF_16_CRC_SEED_MSB, 0x3F);
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CYRF_WriteRegister(CYRF_16_CRC_SEED_MSB, 0x3F);
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#else
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#else
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CYRF_WriteRegister(CYRF_15_CRC_SEED_LSB, cyrfmfg_id[0]+0xB6);
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uint16_t addr=TRAXXAS_EEPROM_OFFSET+RX_num*2;
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CYRF_WriteRegister(CYRF_16_CRC_SEED_MSB, cyrfmfg_id[1]+0x5D);
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CYRF_WriteRegister(CYRF_15_CRC_SEED_LSB, cyrfmfg_id[0] - eeprom_read_byte((EE_ADDR)(addr + 0)));
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CYRF_WriteRegister(CYRF_16_CRC_SEED_MSB, cyrfmfg_id[1] - eeprom_read_byte((EE_ADDR)(addr + 1)));
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#endif
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#endif
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CYRF_ConfigRFChannel(TRAXXAS_CHANNEL);
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CYRF_ConfigRFChannel(TRAXXAS_CHANNEL);
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CYRF_SetTxRxMode(TX_EN);
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CYRF_SetTxRxMode(TX_EN);
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@ -115,19 +117,30 @@ uint16_t TRAXXAS_callback()
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status = CYRF_ReadRegister(CYRF_07_RX_IRQ_STATUS);
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status = CYRF_ReadRegister(CYRF_07_RX_IRQ_STATUS);
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if((status & 0x03) == 0x02) // RXC=1, RXE=0 then 2nd check is required (debouncing)
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if((status & 0x03) == 0x02) // RXC=1, RXE=0 then 2nd check is required (debouncing)
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status |= CYRF_ReadRegister(CYRF_07_RX_IRQ_STATUS);
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status |= CYRF_ReadRegister(CYRF_07_RX_IRQ_STATUS);
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#ifdef TRAXXAS_DEBUG
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debugln("s=%02X",status);
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debugln("s=%02X",status);
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#endif
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CYRF_WriteRegister(CYRF_07_RX_IRQ_STATUS, 0x80); // need to set RXOW before data read
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CYRF_WriteRegister(CYRF_07_RX_IRQ_STATUS, 0x80); // need to set RXOW before data read
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if((status & 0x07) == 0x02)
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if((status & 0x07) == 0x02)
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{ // Data received with no errors
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{ // Data received with no errors
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len=CYRF_ReadRegister(CYRF_09_RX_COUNT);
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len=CYRF_ReadRegister(CYRF_09_RX_COUNT);
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#ifdef TRAXXAS_DEBUG
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debugln("L=%02X",len)
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debugln("L=%02X",len)
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#endif
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if(len==TRAXXAS_PACKET_SIZE)
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if(len==TRAXXAS_PACKET_SIZE)
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{
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{
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CYRF_ReadDataPacketLen(packet, TRAXXAS_PACKET_SIZE);
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CYRF_ReadDataPacketLen(packet, TRAXXAS_PACKET_SIZE);
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#ifdef TRAXXAS_DEBUG
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debug("RX=");
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debug("RX=");
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for(uint8_t i=0;i<TRAXXAS_PACKET_SIZE;i++)
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for(uint8_t i=0;i<TRAXXAS_PACKET_SIZE;i++)
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debug(" %02X",packet[i]);
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debug(" %02X",packet[i]);
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debugln("");
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debugln("");
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#endif
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// Store RX ID
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uint16_t addr=TRAXXAS_EEPROM_OFFSET+RX_num*2;
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for(uint8_t i=0;i<2;i++)
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eeprom_write_byte((EE_ADDR)(addr+i),packet[i+1]);
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// Replace RX ID by TX ID
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for(uint8_t i=0;i<6;i++)
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for(uint8_t i=0;i<6;i++)
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packet[i+1]=cyrfmfg_id[i];
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packet[i+1]=cyrfmfg_id[i];
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packet[10]=0x01;
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packet[10]=0x01;
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@ -150,10 +163,12 @@ uint16_t TRAXXAS_callback()
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return 700;
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return 700;
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case TRAXXAS_BIND_TX1:
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case TRAXXAS_BIND_TX1:
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CYRF_WriteDataPacketLen(packet, TRAXXAS_PACKET_SIZE);
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CYRF_WriteDataPacketLen(packet, TRAXXAS_PACKET_SIZE);
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#ifdef TRAXXAS_DEBUG
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debug("P=");
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debug("P=");
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for(uint8_t i=0;i<TRAXXAS_PACKET_SIZE;i++)
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for(uint8_t i=0;i<TRAXXAS_PACKET_SIZE;i++)
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debug(" %02X",packet[i]);
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debug(" %02X",packet[i]);
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debugln("");
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debugln("");
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#endif
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if(--packet_count==0) // Switch to normal mode
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if(--packet_count==0) // Switch to normal mode
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phase=TRAXXAS_PREP_DATA;
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phase=TRAXXAS_PREP_DATA;
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break;
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break;
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@ -179,7 +194,7 @@ void TRAXXAS_init()
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//Read CYRF ID
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//Read CYRF ID
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CYRF_GetMfgData(cyrfmfg_id);
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CYRF_GetMfgData(cyrfmfg_id);
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cyrfmfg_id[0]+=RX_num;
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//cyrfmfg_id[0]+=RX_num; // Not needed since the TX and RX have to match
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#ifdef TRAXXAS_FORCE_ID // data taken from TX dump
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#ifdef TRAXXAS_FORCE_ID // data taken from TX dump
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cyrfmfg_id[0]=0x65; // CYRF MFG ID
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cyrfmfg_id[0]=0x65; // CYRF MFG ID
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@ -207,7 +222,14 @@ CRC_SEED_LSB: 0x5A
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CRC_SEED_MSB: 0x5A
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CRC_SEED_MSB: 0x5A
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RX1: 0x02 0x4A 0xA3 0x2D 0x1A 0x49 0xFE 0x06 0x00 0x00 0x02 0x01 0x06 0x06 0x00 0x00
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RX1: 0x02 0x4A 0xA3 0x2D 0x1A 0x49 0xFE 0x06 0x00 0x00 0x02 0x01 0x06 0x06 0x00 0x00
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TX1: 0x02 0x65 0xE2 0x5E 0x55 0x4D 0xFE 0xEE 0x00 0x00 0x01 0x01 0x06 0x05 0x00 0x00
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TX1: 0x02 0x65 0xE2 0x5E 0x55 0x4D 0xFE 0xEE 0x00 0x00 0x01 0x01 0x06 0x05 0x00 0x00
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Note: RX cyrfmfg_id is 0x4A,0xA3,0x2D,0x1A,0x49,0xFE and TX cyrfmfg_id is 0x65,0xE2,0x5E,0x55,0x4D,0xFE
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Notes:
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- RX cyrfmfg_id is 0x4A,0xA3,0x2D,0x1A,0x49,0xFE and TX cyrfmfg_id is 0x65,0xE2,0x5E,0x55,0x4D,0xFE
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- P[7] changes from 0x06 to 0xEE but not needed to complete the bind
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- P[8..9]=0x00 unchanged??
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- P[10] needs to be set to 0x01 to complete the bind -> normal packet P[0]??
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- P[11..12] unchanged ??
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- P[13] changes from 0x06 to 0x05 but not needed to complete the bind
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- P[14..15]=0x00 unchanged??
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Bind phase 2 (looks like normal mode?)
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Bind phase 2 (looks like normal mode?)
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CHANNEL: 0x05
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CHANNEL: 0x05
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@ -231,5 +253,11 @@ SOP_CODE: 0xA1 0x78 0xDC 0x3C 0x9E 0x82 0xDC 0x3C
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CRC_SEED_LSB: 0x1B
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CRC_SEED_LSB: 0x1B
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CRC_SEED_MSB: 0x3F
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CRC_SEED_MSB: 0x3F
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TX3: 0x01 0x00 0x02 0xA8 0x03 0xE7 0x02 0x08 0x00 0x00 0x01 0x01 0x02 0xEE 0x00 0x00
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TX3: 0x01 0x00 0x02 0xA8 0x03 0xE7 0x02 0x08 0x00 0x00 0x01 0x01 0x02 0xEE 0x00 0x00
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CRC_SEED:
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TX ID: \x65\xE2\x5E\x55\x4D\xFE
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RX ID: \x4A\xA3\x2D\x1A\x49\xFE CRC 0x1B 0x3F => CRC: 65-4A=1B E2-A3=3F
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RX ID: \x4B\xA3\x2D\x1A\x49\xFE CRC 0x1A 0x3F => CRC: 65-4B=1A E2-A3=3F
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RX ID: \x00\x00\x2D\x1A\x49\xFE CRC 0x65 0xE2 => CRC: 65-00=65 E2-00=E2
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*/
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*/
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#endif
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#endif
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