gomaomao/DIY-Multiprotocol-TX-Module
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AFHDS2A RX: trial to fix bind with original TX

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This commit is contained in:
Pascal Langer 2021-01-19 22:50:55 +01:00
parent 153ba2e090
commit 5cec22a757
2 changed files with 17 additions and 5 deletions
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20
Multiprotocol/AFHDS2A_Rx_a7105.ino
View File

@ -24,6 +24,7 @@
enum { enum {
AFHDS2A_RX_BIND1, AFHDS2A_RX_BIND1,
AFHDS2A_RX_BIND2, AFHDS2A_RX_BIND2,
AFHDS2A_RX_BIND3,
AFHDS2A_RX_DATA AFHDS2A_RX_DATA
}; };
@ -105,12 +106,14 @@ uint16_t AFHDS2A_Rx_callback()
switch(phase) { switch(phase) {
case AFHDS2A_RX_BIND1: case AFHDS2A_RX_BIND1:
if(IS_BIND_DONE) return initAFHDS2A_Rx(); // Abort bind if(IS_BIND_DONE) return initAFHDS2A_Rx(); // Abort bind
debugln("bind p=%d", phase+1);
if (AFHDS2A_Rx_data_ready()) { if (AFHDS2A_Rx_data_ready()) {
A7105_ReadData(AFHDS2A_RX_TXPACKET_SIZE); A7105_ReadData(AFHDS2A_RX_TXPACKET_SIZE);
if ((packet[0] == 0xbb && packet[9] == 0x01) || (packet[0] == 0xbc && packet[9] <= 0x02)) { if ((packet[0] == 0xbb && packet[9] == 0x01) || (packet[0] == 0xbc && packet[9] <= 0x02)) {
memcpy(rx_id, &packet[1], 4); // TX id actually memcpy(rx_id, &packet[1], 4); // TX id actually
memcpy(hopping_frequency, &packet[11], AFHDS2A_RX_NUMFREQ); memcpy(hopping_frequency, &packet[11], AFHDS2A_RX_NUMFREQ);
phase = AFHDS2A_RX_BIND2; phase = AFHDS2A_RX_BIND2;
debugln("phase bind2");
} }
} }
A7105_WriteReg(A7105_0F_PLL_I, (packet_count++ & 1) ? 0x0D : 0x8C); // bind channels A7105_WriteReg(A7105_0F_PLL_I, (packet_count++ & 1) ? 0x0D : 0x8C); // bind channels
@ -131,22 +134,30 @@ uint16_t AFHDS2A_Rx_callback()
eeprom_write_byte((EE_ADDR)temp++, rx_id[i]); eeprom_write_byte((EE_ADDR)temp++, rx_id[i]);
for (i = 0; i < AFHDS2A_RX_NUMFREQ; i++) for (i = 0; i < AFHDS2A_RX_NUMFREQ; i++)
eeprom_write_byte((EE_ADDR)temp++, hopping_frequency[i]); eeprom_write_byte((EE_ADDR)temp++, hopping_frequency[i]);
BIND_DONE; phase = AFHDS2A_RX_BIND3;
phase = AFHDS2A_RX_DATA; debugln("phase bind3");
return 3850; packet_count = 0;
} }
} }
case AFHDS2A_RX_BIND3:
debugln("bind p=%d", phase+1);
// transmit response packet // transmit response packet
packet[0] = 0xBC; packet[0] = 0xBC;
memcpy(&packet[1], rx_id, 4); memcpy(&packet[1], rx_id, 4);
memcpy(&packet[5], rx_tx_addr, 4); memcpy(&packet[5], rx_tx_addr, 4);
packet[9] = 0x01; //packet[9] = 0x01;
packet[10] = 0x00; packet[10] = 0x00;
memset(&packet[11], 0xFF, 26); memset(&packet[11], 0xFF, 26);
A7105_SetTxRxMode(TX_EN); A7105_SetTxRxMode(TX_EN);
rx_disable_lna = !IS_POWER_FLAG_on; rx_disable_lna = !IS_POWER_FLAG_on;
A7105_WriteData(AFHDS2A_RX_RXPACKET_SIZE, packet_count++ & 1 ? 0x0D : 0x8C); A7105_WriteData(AFHDS2A_RX_RXPACKET_SIZE, packet_count++ & 1 ? 0x0D : 0x8C);
if(phase == AFHDS2A_RX_BIND3 && packet_count > 20)
{
debugln("done");
BIND_DONE;
return initAFHDS2A_Rx(); // Restart protocol
}
phase |= AFHDS2A_RX_WAIT_WRITE; phase |= AFHDS2A_RX_WAIT_WRITE;
return 1700; return 1700;
@ -157,6 +168,7 @@ uint16_t AFHDS2A_Rx_callback()
if (!(A7105_ReadReg(A7105_00_MODE) & 0x01)) if (!(A7105_ReadReg(A7105_00_MODE) & 0x01))
break; break;
A7105_Strobe(A7105_RX); A7105_Strobe(A7105_RX);
case AFHDS2A_RX_BIND3 | AFHDS2A_RX_WAIT_WRITE:
phase &= ~AFHDS2A_RX_WAIT_WRITE; phase &= ~AFHDS2A_RX_WAIT_WRITE;
return 10000; return 10000;

2
Multiprotocol/Multiprotocol.h
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@ -19,7 +19,7 @@
#define VERSION_MAJOR 1 #define VERSION_MAJOR 1
#define VERSION_MINOR 3 #define VERSION_MINOR 3
#define VERSION_REVISION 2 #define VERSION_REVISION 2
#define VERSION_PATCH_LEVEL 7 #define VERSION_PATCH_LEVEL 8
//****************** //******************
// Protocols // Protocols