From 5cec22a7572673b5cd8df5d40e2a66fe937a1d0f Mon Sep 17 00:00:00 2001
From: Pascal Langer <planger@mathworks.com>
Date: Tue, 19 Jan 2021 22:50:55 +0100
Subject: [PATCH] AFHDS2A RX: trial to fix bind with original TX

---
 Multiprotocol/AFHDS2A_Rx_a7105.ino | 20 ++++++++++++++++----
 Multiprotocol/Multiprotocol.h      |  2 +-
 2 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/Multiprotocol/AFHDS2A_Rx_a7105.ino b/Multiprotocol/AFHDS2A_Rx_a7105.ino
index 7f860fc..37f187a 100644
--- a/Multiprotocol/AFHDS2A_Rx_a7105.ino
+++ b/Multiprotocol/AFHDS2A_Rx_a7105.ino
@@ -24,6 +24,7 @@
 enum {
 	AFHDS2A_RX_BIND1,
 	AFHDS2A_RX_BIND2,
+	AFHDS2A_RX_BIND3,
 	AFHDS2A_RX_DATA
 };
 
@@ -105,12 +106,14 @@ uint16_t AFHDS2A_Rx_callback()
 	switch(phase) {
 	case AFHDS2A_RX_BIND1:
 		if(IS_BIND_DONE) return initAFHDS2A_Rx();	// Abort bind
+		debugln("bind p=%d", phase+1);
 		if (AFHDS2A_Rx_data_ready()) {
 			A7105_ReadData(AFHDS2A_RX_TXPACKET_SIZE);
 			if ((packet[0] == 0xbb && packet[9] == 0x01) ||	(packet[0] == 0xbc && packet[9] <= 0x02)) {
 				memcpy(rx_id, &packet[1], 4); // TX id actually
 				memcpy(hopping_frequency, &packet[11], AFHDS2A_RX_NUMFREQ);
 				phase = AFHDS2A_RX_BIND2;
+				debugln("phase bind2");
 			}
 		}
 		A7105_WriteReg(A7105_0F_PLL_I, (packet_count++ & 1) ? 0x0D : 0x8C); // bind channels
@@ -131,22 +134,30 @@ uint16_t AFHDS2A_Rx_callback()
 					eeprom_write_byte((EE_ADDR)temp++, rx_id[i]);
 				for (i = 0; i < AFHDS2A_RX_NUMFREQ; i++)
 					eeprom_write_byte((EE_ADDR)temp++, hopping_frequency[i]);
-				BIND_DONE;
-				phase = AFHDS2A_RX_DATA;
-				return 3850;
+				phase = AFHDS2A_RX_BIND3;
+				debugln("phase bind3");
+				packet_count = 0;
 			}
 		}
 
+	case AFHDS2A_RX_BIND3:
+		debugln("bind p=%d", phase+1);
 		// transmit response packet
 		packet[0] = 0xBC;
 		memcpy(&packet[1], rx_id, 4);
 		memcpy(&packet[5], rx_tx_addr, 4);
-		packet[9] = 0x01;
+		//packet[9] = 0x01;
 		packet[10] = 0x00;
 		memset(&packet[11], 0xFF, 26);
 		A7105_SetTxRxMode(TX_EN);
 		rx_disable_lna = !IS_POWER_FLAG_on;
 		A7105_WriteData(AFHDS2A_RX_RXPACKET_SIZE, packet_count++ & 1 ? 0x0D : 0x8C);
+		if(phase == AFHDS2A_RX_BIND3 && packet_count > 20)
+		{
+			debugln("done");
+			BIND_DONE;
+			return initAFHDS2A_Rx();	// Restart protocol
+		}
 		phase |= AFHDS2A_RX_WAIT_WRITE;
 		return 1700;
 	
@@ -157,6 +168,7 @@ uint16_t AFHDS2A_Rx_callback()
 			if (!(A7105_ReadReg(A7105_00_MODE) & 0x01))
 				break;
 		A7105_Strobe(A7105_RX);
+	case AFHDS2A_RX_BIND3 | AFHDS2A_RX_WAIT_WRITE:
 		phase &= ~AFHDS2A_RX_WAIT_WRITE;
 		return 10000;
 	
diff --git a/Multiprotocol/Multiprotocol.h b/Multiprotocol/Multiprotocol.h
index d4288e9..9f71c05 100644
--- a/Multiprotocol/Multiprotocol.h
+++ b/Multiprotocol/Multiprotocol.h
@@ -19,7 +19,7 @@
 #define VERSION_MAJOR		1
 #define VERSION_MINOR		3
 #define VERSION_REVISION	2
-#define VERSION_PATCH_LEVEL	7
+#define VERSION_PATCH_LEVEL	8
 
 //******************
 // Protocols