mirror of
https://github.com/pascallanger/DIY-Multiprotocol-TX-Module.git
synced 2025-02-04 18:28:15 +00:00
New protocol WFLY (40)
Use the CYRF6936 RF component Extended limit supported No sub protocol option=number of channels between 4 and 9. If outside of the range default=9.
This commit is contained in:
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1647d3d841
commit
4bb4bd9792
@ -98,13 +98,15 @@ void CYRF_SetTxRxMode(uint8_t mode)
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{
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if(mode==TXRX_OFF)
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{
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CYRF_WriteRegister(CYRF_0F_XACT_CFG, 0x24); // 4=IDLE, 8=TX, C=RX
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if(protocol!=PROTO_WFLY)
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CYRF_WriteRegister(CYRF_0F_XACT_CFG, 0x24); // 4=IDLE, 8=TX, C=RX
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CYRF_WriteRegister(CYRF_0E_GPIO_CTRL,0x00); // XOUT=0 PACTL=0
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}
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else
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{
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//Set the post tx/rx state
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CYRF_WriteRegister(CYRF_0F_XACT_CFG, mode == TX_EN ? 0x28 : 0x2C); // 4=IDLE, 8=TX, C=RX
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if(protocol!=PROTO_WFLY)
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CYRF_WriteRegister(CYRF_0F_XACT_CFG, mode == TX_EN ? 0x28 : 0x2C); // 4=IDLE, 8=TX, C=RX
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if(mode == TX_EN)
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#ifdef ORANGE_TX_BLUE
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CYRF_WriteRegister(CYRF_0E_GPIO_CTRL,0x20); // XOUT=1, PACTL=0
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@ -203,9 +205,9 @@ void CYRF_ReadDataPacketLen(uint8_t dpbuffer[], uint8_t length)
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static void CYRF_WriteDataPacketLen(const uint8_t dpbuffer[], uint8_t len)
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{
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CYRF_WriteRegister(CYRF_01_TX_LENGTH, len);
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CYRF_WriteRegister(CYRF_02_TX_CTRL, 0x40);
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CYRF_WriteRegister(CYRF_02_TX_CTRL, 0x43); // 0x40
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CYRF_WriteRegisterMulti(CYRF_20_TX_BUFFER, dpbuffer, len);
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CYRF_WriteRegister(CYRF_02_TX_CTRL, 0xBF);
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CYRF_WriteRegister(CYRF_02_TX_CTRL, 0x83); // 0xBF
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}
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void CYRF_WriteDataPacket(const uint8_t dpbuffer[])
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@ -448,9 +448,9 @@ uint16_t ReadDsm()
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case DSM_CH1_CHECK_B:
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case DSM_CH2_CHECK_A:
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case DSM_CH2_CHECK_B:
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start=micros();
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while ((uint8_t)micros()-start < 100) // Wait max 100µs, max I've seen is 50µs
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if(CYRF_ReadRegister(CYRF_04_TX_IRQ_STATUS) & 0x02)
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start=(uint8_t)micros();
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while ((uint8_t)((uint8_t)micros()-(uint8_t)start) < 100) // Wait max 100µs, max I've seen is 50µs
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if((CYRF_ReadRegister(CYRF_02_TX_CTRL) & 0x80) == 0x00)
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break;
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if(phase==DSM_CH1_CHECK_A || phase==DSM_CH1_CHECK_B)
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{
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@ -39,13 +39,11 @@ enum {
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HITEC_RX2 = 0x08,
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};
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#define HITEC_FREQ0_VAL 0xE8
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const PROGMEM uint8_t HITEC_init_values[] = {
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/* 00 */ 0x2F, 0x2E, 0x2F, 0x07, 0xD3, 0x91, 0xFF, 0x04,
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/* 08 */ 0x45, 0x00, 0x00, 0x12, 0x00, 0x5C, 0x85, HITEC_FREQ0_VAL + HITEC_COARSE,
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/* 08 */ 0x45, 0x00, 0x00, 0x12, 0x00, 0x5C, 0x85, 0xE8 + HITEC_COARSE,
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/* 10 */ 0x3D, 0x3B, 0x73, 0x73, 0x7A, 0x01, 0x07, 0x30,
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/* 18 */ 0x08, 0x1D, 0x1C, 0xC7, 0x00, 0xB0, 0x87, 0x6B,
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/* 18 */ 0x08, 0x1D, 0x1C, 0xC7, 0x40, 0xB0, 0x87, 0x6B,
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/* 20 */ 0xF8, 0xB6, 0x10, 0xEA, 0x0A, 0x00, 0x11
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};
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@ -325,7 +323,7 @@ uint16_t ReadHITEC()
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// 0C,1C,A1,2B,00,16,00,00,00,00,00,16,00,2C,8E
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// 0C,1C,A1,2B,00,17,00,00,00,42,44,17,00,48,8D -> 42=>temperature3 0x42-0x28=26°C,44=>temperature4 0x44-0x28=28°C
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// 0C,1C,A1,2B,00,18,00,00,00,00,00,18,00,50,92
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debug(",telem");
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debug(",telem,%02x",pkt[14]&0x7F);
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#if defined(HITEC_FW_TELEMETRY)
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if(sub_protocol==OPT_FW)
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{
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@ -128,7 +128,7 @@ static void __attribute__((unused)) j6pro_set_radio_channels()
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uint16_t ReadJ6Pro()
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{
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uint32_t start;
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uint16_t start;
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switch(phase)
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{
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@ -144,11 +144,11 @@ uint16_t ReadJ6Pro()
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phase = J6PRO_BIND_03_START;
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return 3000; //3msec
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case J6PRO_BIND_03_START:
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start=micros();
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while (micros()-start < 500) // Wait max 500µs
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if(CYRF_ReadRegister(CYRF_04_TX_IRQ_STATUS) & 0x06)
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break;
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CYRF_ConfigRFChannel(0x53);
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start=(uint16_t)micros();
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while ((uint16_t)((uint16_t)micros()-(uint16_t)start) < 500) // Wait max 500µs
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if((CYRF_ReadRegister(CYRF_02_TX_CTRL) & 0x80) == 0x00)
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break; // Packet transmission complete
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CYRF_ConfigRFChannel(0x53);
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CYRF_SetTxRxMode(RX_EN);
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//CYRF_WriteRegister(CYRF_06_RX_CFG, 0x4a);
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CYRF_WriteRegister(CYRF_05_RX_CTRL, 0x80);
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@ -37,3 +37,4 @@
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37,CORONA,COR_V1,COR_V2,FD_V3
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38,CFlie
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39,Hitec,OPT_FW,OPT_HUB,MINIMA
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40,WFLY
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@ -19,7 +19,7 @@
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#define VERSION_MAJOR 1
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#define VERSION_MINOR 2
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#define VERSION_REVISION 0
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#define VERSION_PATCH_LEVEL 31
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#define VERSION_PATCH_LEVEL 32
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//******************
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// Protocols
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@ -66,6 +66,7 @@ enum PROTOCOLS
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PROTO_CORONA = 37, // =>CC2500
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PROTO_CFLIE = 38, // =>NRF24L01
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PROTO_HITEC = 39, // =>CC2500
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PROTO_WFLY = 40, // =>CYRF6936
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};
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enum Flysky
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@ -569,6 +570,7 @@ Serial: 100000 Baud 8e2 _ xxxx xxxx p --
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CORONA 37
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CFlie 38
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Hitec 39
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WFLY 40
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BindBit=> 0x80 1=Bind/0=No
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AutoBindBit=> 0x40 1=Yes /0=No
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RangeCheck=> 0x20 1=Yes /0=No
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@ -108,10 +108,8 @@ uint16_t crc;
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uint8_t crc8;
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uint16_t seed;
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uint16_t failsafe_count;
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//
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uint16_t state;
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uint8_t len;
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uint8_t RX_num;
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#if defined(FRSKYX_CC2500_INO) || defined(SFHSS_CC2500_INO)
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uint8_t calData[48];
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@ -157,6 +155,7 @@ uint8_t option;
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uint8_t cur_protocol[3];
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uint8_t prev_option;
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uint8_t prev_power=0xFD; // unused power value
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uint8_t RX_num;
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//Serial RX variables
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#define BAUD 100000
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@ -975,6 +974,13 @@ static void protocol_init()
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remote_callback = ReadDsm;
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break;
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#endif
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#if defined(WFLY_CYRF6936_INO)
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case PROTO_WFLY:
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PE2_on; //antenna RF4
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next_callback = initWFLY();
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remote_callback = ReadWFLY;
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break;
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#endif
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#if defined(DEVO_CYRF6936_INO)
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case PROTO_DEVO:
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#ifdef ENABLE_PPM
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@ -143,6 +143,7 @@
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#undef DEVO_CYRF6936_INO
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#undef DSM_CYRF6936_INO
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#undef J6PRO_CYRF6936_INO
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#undef WFLY_CYRF6936_INO
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#undef WK2x01_CYRF6936_INO
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#endif
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#ifndef CC2500_INSTALLED
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Multiprotocol/WFLY_cyrf6936.ino
Normal file
294
Multiprotocol/WFLY_cyrf6936.ino
Normal file
@ -0,0 +1,294 @@
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/*
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This project is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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Multiprotocol is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Multiprotocol. If not, see <http://www.gnu.org/licenses/>.
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*/
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#if defined(WFLY_CYRF6936_INO)
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#include "iface_cyrf6936.h"
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//#define WFLY_FORCE_ID
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#define WFLY_BIND_COUNT 1500 // around 15s
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#define WFLY_NUM_FREQUENCE 4
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#define WFLY_BIND_CHANNEL 0x09
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enum {
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WFLY_BIND_TX=0,
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WFLY_BIND_PREP_RX,
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WFLY_BIND_RX,
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WFLY_PREP_DATA,
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WFLY_DATA,
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};
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const uint8_t PROGMEM WFLY_sop_bind[]={ 0x5A, 0xCC, 0xAE, 0x46, 0xB6, 0x31, 0xAE, 0x46 };
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const uint8_t PROGMEM WFLY_sop_data[]={ 0xEF, 0x64, 0xB0, 0x2A, 0xD2, 0x8F, 0xB1, 0x2A };
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//Most of the bytes are unknown... 1C A7 looks to be the bind ID, BF 13 is the TX ID, 15 is the channel used to send the hopping frequencies.
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const uint8_t PROGMEM WFLY_bind_packet[]={ 0x1C, 0xA7, 0x60, 0x04, 0x04, 0xBF, 0x13, 0x15, 0xC5, 0x40, 0x8A, 0x37, 0xE0, 0xE8, 0x03, 0xA3 };
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const uint8_t PROGMEM WFLY_init_vals[][2] = {
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//Init from dump
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{CYRF_1D_MODE_OVERRIDE, 0x19}, // Reset
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{CYRF_32_AUTO_CAL_TIME, 0x3C}, // Default init value
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{CYRF_35_AUTOCAL_OFFSET, 0x14}, // Default init value
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{CYRF_1B_TX_OFFSET_LSB, 0x55}, // Default init value
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{CYRF_1C_TX_OFFSET_MSB, 0x05}, // Default init value
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{CYRF_06_RX_CFG, 0x48 | 0x02}, // LNA enabled, Fast Turn Mode enabled, adding overwrite enable to not lockup RX
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{CYRF_10_FRAMING_CFG, 0xE8}, // SOP enable
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{CYRF_03_TX_CFG, 0x08 | CYRF_BIND_POWER}, // Original=0x0F, 8DR Mode, 32 chip codes
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{CYRF_0C_XTAL_CTRL, 0xC4}, // Enable XOUT as GPIO
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{CYRF_0D_IO_CFG, 0x04}, // Enable PACTL as GPIO
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{CYRF_0F_XACT_CFG, 0x21}, // Abort current operation
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{CYRF_1E_RX_OVERRIDE, 0x00}, // Accept packets with 0 seed for bind
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{CYRF_15_CRC_SEED_LSB, 0x00}, // CRC seed for bind
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{CYRF_16_CRC_SEED_MSB, 0x00}, // CRC seed for bind
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};
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static void __attribute__((unused)) WFLY_cyrf_bind_config()
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{
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for(uint8_t i = 0; i < sizeof(init_vals) / 2; i++)
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CYRF_WriteRegister(pgm_read_byte_near(&WFLY_init_vals[i][0]), pgm_read_byte_near(&WFLY_init_vals[i][1]));
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CYRF_PROGMEM_ConfigSOPCode(WFLY_sop_bind);
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CYRF_ConfigRFChannel(WFLY_BIND_CHANNEL);
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CYRF_SetTxRxMode(TX_EN);
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}
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static void __attribute__((unused)) WFLY_cyrf_data_config()
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{
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for(uint8_t i = 0; i < (sizeof(init_vals) / 2)-3; i++)
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CYRF_WriteRegister(pgm_read_byte_near(&WFLY_init_vals[i][0]), pgm_read_byte_near(&WFLY_init_vals[i][1]));
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//CYRF_WriteRegister(CYRF_1E_RX_OVERRIDE, 0x08); // Do not accept CRC with 0 seed but not needed since the RX is not sending any data...
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CYRF_WriteRegister(CYRF_15_CRC_SEED_LSB, rx_tx_addr[2]);
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CYRF_WriteRegister(CYRF_16_CRC_SEED_MSB, rx_tx_addr[3]);
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CYRF_PROGMEM_ConfigSOPCode(WFLY_sop_data);
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CYRF_SetTxRxMode(TX_EN);
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}
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static uint16_t __attribute__((unused)) WFLY_send_data_packet()
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{
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packet_count++;
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packet[0] = rx_tx_addr[2];
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packet[1] = rx_tx_addr[3];
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if(packet_count%4==3)
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{ // Send the hopping frequencies
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packet[2]=0x70; // packet type
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packet[3]=0x04; // unknown
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packet[4]=0x00; // unknown
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packet[5]=0x04; // unknown
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packet[6]=hopping_frequency[0];
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packet[7]=hopping_frequency[0];
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packet[8]=hopping_frequency[1];
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packet[9]=hopping_frequency[2];
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len=10; // packet[10] contains the checksum
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}
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else
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{ // Send sticks packet
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uint8_t nbr_ch=option;
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if(nbr_ch<4) nbr_ch=9; // 4 channels min can be sent, default to 9
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if(nbr_ch>9) nbr_ch=9; // 9 channels max can be sent
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packet[2]=nbr_ch-3; // nbr of channels to follow
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packet[3]=packet_count>>2; // packet counter 0x00..0x3F
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len=4;
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for(uint8_t i=0;i<3;i++)
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{ // Channels
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uint16_t ch = convert_channel_16b_nolimit(i*4+0,151,847);
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uint8_t offset=i*5;
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packet[3+offset]|=ch<<6;
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packet[4+offset]=ch>>2;
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len++;
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if(--nbr_ch==0) break;
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ch = convert_channel_16b_nolimit(i*4+1,151,847);
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packet[5+offset]=ch;
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packet[6+offset]=ch>>8;
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len+=2;
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if(--nbr_ch==0) break;
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ch = convert_channel_16b_nolimit(i*4+2,151,847);
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packet[6+offset]|=ch<<2;
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packet[7+offset]=ch>>6;
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len++;
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if(--nbr_ch==0) break;
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ch = convert_channel_16b_nolimit(i*4+3,151,847);
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packet[7+offset]|=ch<<4;
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packet[8+offset]=ch>>4;
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len++;
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if(--nbr_ch==0) break;
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}
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}
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uint8_t sum=0;
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for(uint8_t i = 0; i < len; i++)
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sum += packet[i];
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packet[len] = sum;
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CYRF_ConfigRFChannel(hopping_frequency[(packet_count)%4]);
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CYRF_SetPower(0x08);
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CYRF_WriteDataPacketLen(packet, len+1);
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switch(packet_count%4)
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{
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case 0:
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return 1393;
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case 1:
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return 1330;
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case 2:
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return 1555;
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}
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return 1093; // case 3
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}
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uint16_t ReadWFLY()
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{
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uint8_t status,len,sum=0,check=0;
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uint8_t start;
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static uint8_t retry;
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switch(phase)
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{
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case WFLY_BIND_TX:
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CYRF_SetTxRxMode(TX_EN);
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CYRF_WriteDataPacketLen(packet, sizeof(WFLY_bind_packet));
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debug("P=");
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for(uint8_t i=0;i<sizeof(WFLY_bind_packet);i++)
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debug(" %02X",packet[i]);
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debugln(" , L=%02X", sizeof(WFLY_bind_packet));
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phase++;
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if(--bind_counter==0)
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{ // Switch to normal mode
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BIND_DONE;
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phase=WFLY_PREP_DATA;
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}
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return 2500;
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case WFLY_BIND_PREP_RX:
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start=micros();
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while ((uint8_t)((uint8_t)micros()-(uint8_t)start) < 200) // Wait max 200µs for TX to finish
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if((CYRF_ReadRegister(CYRF_02_TX_CTRL) & 0x80) == 0x00)
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break; // Packet transmission complete
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CYRF_SetTxRxMode(RX_EN); //Receive mode
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CYRF_WriteRegister(CYRF_05_RX_CTRL, 0x83); //Prepare to receive
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retry=10; //Timeout for RX
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phase=WFLY_BIND_RX;
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return 700;
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case WFLY_BIND_RX:
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//Read data from RX
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status = CYRF_ReadRegister(CYRF_07_RX_IRQ_STATUS);
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if((status & 0x03) == 0x02) // RXC=1, RXE=0 then 2nd check is required (debouncing)
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status |= CYRF_ReadRegister(CYRF_07_RX_IRQ_STATUS);
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CYRF_WriteRegister(CYRF_07_RX_IRQ_STATUS, 0x80); // need to set RXOW before data read
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if((status & 0x07) == 0x02)
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{ // Data received with no errors
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len=CYRF_ReadRegister(CYRF_09_RX_COUNT);
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debugln("L=%02X",len)
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if(len==0x10)
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{
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CYRF_ReadDataPacketLen(pkt, len);
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debug("RX=");
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for(uint8_t i=0;i<0x0F;i++)
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{
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debug(" %02X",pkt[i]);
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if(pkt[i]==packet[i])
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check++; // Verify quickly the content
|
||||
sum+=pkt[i];
|
||||
}
|
||||
debugln(" %02X",pkt[15]);
|
||||
if(sum==pkt[15] && check>=10)
|
||||
{ // Good packet received
|
||||
if(pkt[2]==0x64)
|
||||
{ // Switch to normal mode
|
||||
BIND_DONE;
|
||||
phase=WFLY_PREP_DATA;
|
||||
return 10000;
|
||||
}
|
||||
memcpy((void *)packet,(void *)pkt,0x10); // Send back to the RX what we've just received with no modifications
|
||||
}
|
||||
phase=WFLY_BIND_TX;
|
||||
return 200;
|
||||
}
|
||||
}
|
||||
if(status & 0x85 || --retry == 0)
|
||||
{ // RX error or no answer
|
||||
debugln("Abort");
|
||||
CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x20); // Enable RX abort
|
||||
CYRF_WriteRegister(CYRF_0F_XACT_CFG, 0x21); // Force end state
|
||||
CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x00); // Disable RX abort
|
||||
phase=WFLY_BIND_TX; // Retry sending bind packet
|
||||
}
|
||||
return 700;
|
||||
case WFLY_PREP_DATA:
|
||||
WFLY_cyrf_data_config();
|
||||
packet_count=0;
|
||||
phase++;
|
||||
case WFLY_DATA:
|
||||
start=micros();
|
||||
while ((uint8_t)((uint8_t)micros()-(uint8_t)start) < 200)
|
||||
if((CYRF_ReadRegister(CYRF_02_TX_CTRL) & 0x80) == 0x00)
|
||||
break; // Packet transmission complete
|
||||
return WFLY_send_data_packet();
|
||||
}
|
||||
return 1000;
|
||||
}
|
||||
|
||||
uint16_t initWFLY()
|
||||
{
|
||||
//Random start channel
|
||||
uint8_t ch=0x0A+random(0xfefefefe)%0x0E;
|
||||
if(ch%3==0)
|
||||
ch++; // remove these channels as they seem to not be working...
|
||||
rf_ch_num=0x0C+(rx_tx_addr[1]%4)*3; // use the start channels which do not seem to work to send the hopping table instead
|
||||
|
||||
#ifdef WFLY_FORCE_ID // data taken from TX dump
|
||||
rx_tx_addr[2]=0xBF; // ID
|
||||
rx_tx_addr[3]=0x13; // ID
|
||||
ch=0x16; // value seen between 0x0A and 0x17
|
||||
rc_ch_num=0x15 // RF channel to send the current hopping table
|
||||
#endif
|
||||
|
||||
debug("ID:")
|
||||
for(uint8_t i=0;i<2;i++)
|
||||
debug(" %02X", rx_tx_addr[2+i]);
|
||||
debugln("");
|
||||
|
||||
hopping_frequency[0]=ch;
|
||||
hopping_frequency[1]=ch+0x1E;
|
||||
hopping_frequency[2]=ch+0x2D;
|
||||
hopping_frequency[3]=rf_ch_num; // RF channel used to send the current hopping table
|
||||
|
||||
debug("RF Channels:")
|
||||
for(uint8_t i=0;i<WFLY_NUM_FREQUENCE;i++)
|
||||
debug(" %02X", hopping_frequency[i]);
|
||||
debugln("");
|
||||
|
||||
if(IS_BIND_IN_PROGRESS)
|
||||
{
|
||||
bind_counter=WFLY_BIND_COUNT;
|
||||
WFLY_cyrf_bind_config();
|
||||
for(uint8_t i=0;i<sizeof(WFLY_bind_packet);i++)
|
||||
packet[i]=pgm_read_byte_near(&WFLY_bind_packet[i]);
|
||||
packet[5]=rx_tx_addr[2];
|
||||
packet[6]=rx_tx_addr[3];
|
||||
packet[7]=rf_ch_num;
|
||||
uint8_t sum=0;
|
||||
for(uint8_t i = 0; i < 15; i++)
|
||||
sum += packet[i];
|
||||
packet[15] = sum;
|
||||
phase=WFLY_BIND_TX;
|
||||
}
|
||||
else
|
||||
phase = WFLY_PREP_DATA;
|
||||
return 10000;
|
||||
}
|
||||
|
||||
#endif
|
@ -148,49 +148,50 @@
|
||||
//Comment the protocols you are not using with "//" to save Flash space.
|
||||
|
||||
//The protocols below need an A7105 to be installed
|
||||
#define AFHDS2A_A7105_INO
|
||||
#define FLYSKY_A7105_INO
|
||||
#define HUBSAN_A7105_INO
|
||||
#define AFHDS2A_A7105_INO
|
||||
|
||||
//The protocols below need a CYRF6936 to be installed
|
||||
#define DEVO_CYRF6936_INO
|
||||
#define DSM_CYRF6936_INO
|
||||
#define J6PRO_CYRF6936_INO
|
||||
#define WFLY_CYRF6936_INO
|
||||
#define WK2x01_CYRF6936_INO
|
||||
|
||||
//The protocols below need a CC2500 to be installed
|
||||
#define FRSKYV_CC2500_INO
|
||||
#define FRSKYD_CC2500_INO
|
||||
#define FRSKYX_CC2500_INO
|
||||
#define SFHSS_CC2500_INO
|
||||
#define CORONA_CC2500_INO
|
||||
#define FRSKYD_CC2500_INO
|
||||
#define FRSKYV_CC2500_INO
|
||||
#define FRSKYX_CC2500_INO
|
||||
#define HITEC_CC2500_INO
|
||||
#define SFHSS_CC2500_INO
|
||||
|
||||
//The protocols below need a NRF24L01 to be installed
|
||||
#define ASSAN_NRF24L01_INO
|
||||
#define BAYANG_NRF24L01_INO
|
||||
#define CABELL_NRF24L01_INO
|
||||
#define CFLIE_NRF24L01_INO
|
||||
#define CG023_NRF24L01_INO
|
||||
#define CX10_NRF24L01_INO // Include Q2X2 protocol
|
||||
#define DM002_NRF24L01_INO
|
||||
#define ESKY_NRF24L01_INO
|
||||
#define ESKY150_NRF24L01_INO
|
||||
#define FQ777_NRF24L01_INO
|
||||
#define FY326_NRF24L01_INO
|
||||
#define GW008_NRF24L01_INO
|
||||
#define HISKY_NRF24L01_INO
|
||||
#define HONTAI_NRF24L01_INO
|
||||
#define H8_3D_NRF24L01_INO
|
||||
#define KN_NRF24L01_INO
|
||||
#define MJXQ_NRF24L01_INO
|
||||
#define MT99XX_NRF24L01_INO
|
||||
#define Q303_NRF24L01_INO
|
||||
#define SHENQI_NRF24L01_INO
|
||||
#define SLT_NRF24L01_INO
|
||||
#define SYMAX_NRF24L01_INO
|
||||
#define V2X2_NRF24L01_INO
|
||||
#define YD717_NRF24L01_INO
|
||||
#define MT99XX_NRF24L01_INO
|
||||
#define MJXQ_NRF24L01_INO
|
||||
#define SHENQI_NRF24L01_INO
|
||||
#define FY326_NRF24L01_INO
|
||||
#define FQ777_NRF24L01_INO
|
||||
#define ASSAN_NRF24L01_INO
|
||||
#define HONTAI_NRF24L01_INO
|
||||
#define Q303_NRF24L01_INO
|
||||
#define GW008_NRF24L01_INO
|
||||
#define DM002_NRF24L01_INO
|
||||
#define CABELL_NRF24L01_INO
|
||||
#define ESKY150_NRF24L01_INO
|
||||
#define H8_3D_NRF24L01_INO
|
||||
#define CFLIE_NRF24L01_INO
|
||||
|
||||
|
||||
/**************************/
|
||||
@ -554,6 +555,8 @@ const PPM_Parameters PPM_prot[14*NBR_BANKS]= {
|
||||
OPT_FW
|
||||
OPT_HUB
|
||||
MINIMA
|
||||
PROTO_WFLY
|
||||
NONE
|
||||
*/
|
||||
|
||||
// RX_Num is used for TX & RX match. Using different RX_Num values for each receiver will prevent starting a model with the false config loaded...
|
||||
|
Loading…
x
Reference in New Issue
Block a user