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https://github.com/pascallanger/DIY-Multiprotocol-TX-Module.git
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DSM2 random channels
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pascallanger
parent
cfcd6e5f93
commit
449ad6cd0d
@ -17,8 +17,6 @@
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#include "iface_cyrf6936.h"
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#define DSM2_RANDOM_CHANNELS 0 // disabled
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//#define DSM2_RANDOM_CHANNELS 1 // enabled
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#define DSM_BIND_CHANNEL 0x0d //13 This can be any odd channel
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//During binding we will send BIND_COUNT/2 packets
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@ -140,6 +138,46 @@ static void __attribute__((unused)) read_code(uint8_t *buf, uint8_t row, uint8_t
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buf[i]=pgm_read_byte_near( &pncodes[row][col][i] );
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}
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static uint8_t __attribute__((unused)) get_pn_row(uint8_t channel)
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{
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return ((sub_protocol == DSMX_11 || sub_protocol == DSMX_22 )? (channel - 2) % 5 : channel % 5);
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}
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const uint8_t PROGMEM init_vals[][2] = {
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{CYRF_02_TX_CTRL, 0x02}, //0x00 in deviation but needed to know when transmit is over
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{CYRF_05_RX_CTRL, 0x00},
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{CYRF_28_CLK_EN, 0x02},
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{CYRF_32_AUTO_CAL_TIME, 0x3c},
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{CYRF_35_AUTOCAL_OFFSET, 0x14},
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{CYRF_06_RX_CFG, 0x4A},
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{CYRF_1B_TX_OFFSET_LSB, 0x55},
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{CYRF_1C_TX_OFFSET_MSB, 0x05},
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{CYRF_0F_XACT_CFG, 0x24}, // Force Idle
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{CYRF_03_TX_CFG, 0x38 | CYRF_BIND_POWER}, //Set 64chip, SDR mode
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{CYRF_12_DATA64_THOLD, 0x0a},
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{CYRF_0F_XACT_CFG, 0x04}, // Idle
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{CYRF_39_ANALOG_CTRL, 0x01},
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{CYRF_0F_XACT_CFG, 0x24}, //Force IDLE
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{CYRF_29_RX_ABORT, 0x00}, //Clear RX abort
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{CYRF_12_DATA64_THOLD, 0x0a}, //set pn correlation threshold
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{CYRF_10_FRAMING_CFG, 0x4a}, //set sop len and threshold
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{CYRF_29_RX_ABORT, 0x0f}, //Clear RX abort?
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{CYRF_03_TX_CFG, 0x38 | CYRF_BIND_POWER}, //Set 64chip, SDR mode
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{CYRF_10_FRAMING_CFG, 0x4E}, //0x4a}, //set sop len and threshold
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{CYRF_1F_TX_OVERRIDE, 0x04}, //disable tx CRC
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{CYRF_1E_RX_OVERRIDE, 0x14}, //disable rx crc
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{CYRF_14_EOP_CTRL, 0x02}, //set EOP sync == 2
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{CYRF_01_TX_LENGTH, 0x10}, //16byte packet
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};
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static void __attribute__((unused)) cyrf_config()
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{
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for(uint8_t i = 0; i < sizeof(init_vals) / 2; i++)
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CYRF_WriteRegister(pgm_read_byte_near(&init_vals[i][0]), pgm_read_byte_near(&init_vals[i][1]));
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CYRF_WritePreamble(0x333304);
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CYRF_ConfigRFChannel(0x61);
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}
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static void __attribute__((unused)) build_bind_packet()
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{
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uint8_t i;
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@ -179,6 +217,49 @@ static void __attribute__((unused)) build_bind_packet()
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packet[15] = sum & 0xff;
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}
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static void __attribute__((unused)) initialize_bind_phase()
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{
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uint8_t code[32];
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CYRF_ConfigRFChannel(DSM_BIND_CHANNEL); //This seems to be random?
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uint8_t pn_row = get_pn_row(DSM_BIND_CHANNEL);
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//printf("Ch: %d Row: %d SOP: %d Data: %d\n", DSM_BIND_CHANNEL, pn_row, sop_col, 7 - sop_col);
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CYRF_ConfigCRCSeed(crc);
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read_code(code,pn_row,sop_col,8);
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CYRF_ConfigSOPCode(code);
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read_code(code,pn_row,7 - sop_col,16);
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read_code(code+16,0,8,8);
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memcpy(code + 24, (void *)"\xc6\x94\x22\xfe\x48\xe6\x57\x4e", 8);
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CYRF_ConfigDataCode(code, 32);
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build_bind_packet();
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}
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const uint8_t PROGMEM data_vals[][2] = {
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{CYRF_05_RX_CTRL, 0x83}, //Initialize for reading RSSI
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{CYRF_29_RX_ABORT, 0x20},
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{CYRF_0F_XACT_CFG, 0x24},
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{CYRF_29_RX_ABORT, 0x00},
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{CYRF_03_TX_CFG, 0x08 | CYRF_HIGH_POWER},
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{CYRF_10_FRAMING_CFG, 0xea},
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{CYRF_1F_TX_OVERRIDE, 0x00},
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{CYRF_1E_RX_OVERRIDE, 0x00},
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{CYRF_03_TX_CFG, 0x28 | CYRF_HIGH_POWER},
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{CYRF_12_DATA64_THOLD, 0x3f},
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{CYRF_10_FRAMING_CFG, 0xff},
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{CYRF_0F_XACT_CFG, 0x24}, //Switch from reading RSSI to Writing
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{CYRF_29_RX_ABORT, 0x00},
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{CYRF_12_DATA64_THOLD, 0x0a},
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{CYRF_10_FRAMING_CFG, 0xea},
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};
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static void __attribute__((unused)) cyrf_configdata()
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{
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for(uint8_t i = 0; i < sizeof(data_vals) / 2; i++)
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CYRF_WriteRegister(pgm_read_byte_near(&data_vals[i][0]), pgm_read_byte_near(&data_vals[i][1]));
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}
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static void __attribute__((unused)) update_channels()
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{
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prev_option=option;
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@ -254,107 +335,29 @@ static void __attribute__((unused)) build_data_packet(uint8_t upper)
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}
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}
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static uint8_t __attribute__((unused)) get_pn_row(uint8_t channel)
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{
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return ((sub_protocol == DSMX_11 || sub_protocol == DSMX_22 )? (channel - 2) % 5 : channel % 5);
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}
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const uint8_t PROGMEM init_vals[][2] = {
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{CYRF_02_TX_CTRL, 0x02}, //0x00 in deviation but needed to know when transmit is over
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{CYRF_05_RX_CTRL, 0x00},
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{CYRF_28_CLK_EN, 0x02},
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{CYRF_32_AUTO_CAL_TIME, 0x3c},
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{CYRF_35_AUTOCAL_OFFSET, 0x14},
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{CYRF_06_RX_CFG, 0x4A},
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{CYRF_1B_TX_OFFSET_LSB, 0x55},
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{CYRF_1C_TX_OFFSET_MSB, 0x05},
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{CYRF_0F_XACT_CFG, 0x24}, // Force Idle
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{CYRF_03_TX_CFG, 0x38 | CYRF_BIND_POWER}, //Set 64chip, SDR mode
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{CYRF_12_DATA64_THOLD, 0x0a},
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{CYRF_0F_XACT_CFG, 0x04}, // Idle
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{CYRF_39_ANALOG_CTRL, 0x01},
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{CYRF_0F_XACT_CFG, 0x24}, //Force IDLE
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{CYRF_29_RX_ABORT, 0x00}, //Clear RX abort
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{CYRF_12_DATA64_THOLD, 0x0a}, //set pn correlation threshold
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{CYRF_10_FRAMING_CFG, 0x4a}, //set sop len and threshold
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{CYRF_29_RX_ABORT, 0x0f}, //Clear RX abort?
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{CYRF_03_TX_CFG, 0x38 | CYRF_BIND_POWER}, //Set 64chip, SDR mode
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{CYRF_10_FRAMING_CFG, 0x4E}, //0x4a}, //set sop len and threshold
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{CYRF_1F_TX_OVERRIDE, 0x04}, //disable tx CRC
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{CYRF_1E_RX_OVERRIDE, 0x14}, //disable rx crc
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{CYRF_14_EOP_CTRL, 0x02}, //set EOP sync == 2
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{CYRF_01_TX_LENGTH, 0x10}, //16byte packet
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};
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static void __attribute__((unused)) cyrf_config()
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{
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for(uint8_t i = 0; i < sizeof(init_vals) / 2; i++)
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CYRF_WriteRegister(pgm_read_byte_near(&init_vals[i][0]), pgm_read_byte_near(&init_vals[i][1]));
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CYRF_WritePreamble(0x333304);
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CYRF_ConfigRFChannel(0x61);
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}
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static void __attribute__((unused)) initialize_bind_phase()
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{
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uint8_t code[32];
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CYRF_ConfigRFChannel(DSM_BIND_CHANNEL); //This seems to be random?
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uint8_t pn_row = get_pn_row(DSM_BIND_CHANNEL);
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//printf("Ch: %d Row: %d SOP: %d Data: %d\n", DSM_BIND_CHANNEL, pn_row, sop_col, 7 - sop_col);
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CYRF_ConfigCRCSeed(crc);
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read_code(code,pn_row,sop_col,8);
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CYRF_ConfigSOPCode(code);
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read_code(code,pn_row,7 - sop_col,16);
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read_code(code+16,0,8,8);
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memcpy(code + 24, (void *)"\xc6\x94\x22\xfe\x48\xe6\x57\x4e", 8);
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CYRF_ConfigDataCode(code, 32);
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build_bind_packet();
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}
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const uint8_t PROGMEM data_vals[][2] = {
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{CYRF_05_RX_CTRL, 0x83}, //Initialize for reading RSSI
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{CYRF_29_RX_ABORT, 0x20},
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{CYRF_0F_XACT_CFG, 0x24},
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{CYRF_29_RX_ABORT, 0x00},
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{CYRF_03_TX_CFG, 0x08 | CYRF_HIGH_POWER},
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{CYRF_10_FRAMING_CFG, 0xea},
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{CYRF_1F_TX_OVERRIDE, 0x00},
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{CYRF_1E_RX_OVERRIDE, 0x00},
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{CYRF_03_TX_CFG, 0x28 | CYRF_HIGH_POWER},
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{CYRF_12_DATA64_THOLD, 0x3f},
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{CYRF_10_FRAMING_CFG, 0xff},
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{CYRF_0F_XACT_CFG, 0x24}, //Switch from reading RSSI to Writing
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{CYRF_29_RX_ABORT, 0x00},
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{CYRF_12_DATA64_THOLD, 0x0a},
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{CYRF_10_FRAMING_CFG, 0xea},
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};
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static void __attribute__((unused)) cyrf_configdata()
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{
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for(uint8_t i = 0; i < sizeof(data_vals) / 2; i++)
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CYRF_WriteRegister(pgm_read_byte_near(&data_vals[i][0]), pgm_read_byte_near(&data_vals[i][1]));
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}
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static void __attribute__((unused)) set_sop_data_crc()
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{
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uint8_t code[16];
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uint8_t pn_row = get_pn_row(hopping_frequency[hopping_frequency_no]);
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//printf("Ch: %d Row: %d SOP: %d Data: %d\n", ch[hopping_frequency_no], pn_row, sop_col, 7 - sop_col);
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CYRF_ConfigRFChannel(hopping_frequency[hopping_frequency_no]);
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CYRF_ConfigCRCSeed(crc);
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crc=~crc;
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//The crc for channel '1' is NOT(mfgid[0] << 8 + mfgid[1])
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//The crc for channel '2' is (mfgid[0] << 8 + mfgid[1])
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uint16_t crc = (cyrfmfg_id[0] << 8) + cyrfmfg_id[1];
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if(phase==DSM_CH1_CHECK_A||phase==DSM_CH1_CHECK_B)
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CYRF_ConfigCRCSeed(crc); //CH2
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else
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CYRF_ConfigCRCSeed(~crc); //CH1
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uint8_t pn_row = get_pn_row(hopping_frequency[hopping_frequency_no]);
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uint8_t code[16];
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read_code(code,pn_row,sop_col,8);
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CYRF_ConfigSOPCode(code);
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read_code(code,pn_row,7 - sop_col,16);
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CYRF_ConfigDataCode(code, 16);
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CYRF_ConfigRFChannel(hopping_frequency[hopping_frequency_no]);
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hopping_frequency_no++;
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if(sub_protocol == DSMX_11 || sub_protocol == DSMX_22)
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hopping_frequency_no = (hopping_frequency_no + 1) % 23;
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hopping_frequency_no %=23;
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else
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hopping_frequency_no = (hopping_frequency_no + 1) % 2;
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hopping_frequency_no %=2;
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}
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static void __attribute__((unused)) calc_dsmx_channel()
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@ -477,8 +480,6 @@ uint16_t ReadDsm()
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#endif
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case DSM_CHANSEL:
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BIND_DONE;
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//Select channels and configure for writing data
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//CYRF_FindBestChannels(ch, 2, 10, 1, 79);
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cyrf_configdata();
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CYRF_SetTxRxMode(TX_EN);
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hopping_frequency_no = 0;
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@ -585,7 +586,6 @@ uint16_t initDsm()
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calc_dsmx_channel();
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else
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{
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#if DSM2_RANDOM_CHANNELS == 1
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uint8_t tmpch[10];
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CYRF_FindBestChannels(tmpch, 10, 5, 3, 75);
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//
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@ -598,15 +598,8 @@ uint16_t initDsm()
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break;
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}
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hopping_frequency[1] = tmpch[idx];
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#else
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hopping_frequency[0] = (cyrfmfg_id[0] + cyrfmfg_id[2] + cyrfmfg_id[4]) % 39 + 1;
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hopping_frequency[1] = (cyrfmfg_id[1] + cyrfmfg_id[3] + cyrfmfg_id[5]) % 40 + 40;
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#endif
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}
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//The crc for channel '1' is NOT(mfgid[0] << 8 + mfgid[1])
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//The crc for channel '2' is (mfgid[0] << 8 + mfgid[1])
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crc = ~((cyrfmfg_id[0] << 8) + cyrfmfg_id[1]);
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//
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sop_col = (cyrfmfg_id[0] + cyrfmfg_id[1] + cyrfmfg_id[2] + 2) & 0x07;
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