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Fix for STM32

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This commit is contained in:
Pascal Langer 2017-12-15 17:31:25 +01:00
parent 8da03940e8
commit 337216efac
3 changed files with 15 additions and 8 deletions
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8
Multiprotocol/Multiprotocol.h
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@ -19,7 +19,7 @@
#define VERSION_MAJOR 1 #define VERSION_MAJOR 1
#define VERSION_MINOR 1 #define VERSION_MINOR 1
#define VERSION_REVISION 6 #define VERSION_REVISION 6
#define VERSION_PATCH_LEVEL 42 #define VERSION_PATCH_LEVEL 43
//****************** //******************
// Protocols // Protocols
//****************** //******************
@ -324,10 +324,14 @@ enum MultiPacketTypes {
#define FAILSAFE_CHANNEL_HOLD 2047 #define FAILSAFE_CHANNEL_HOLD 2047
#define FAILSAFE_CHANNEL_NOPULSES 0 #define FAILSAFE_CHANNEL_NOPULSES 0
//Debug messages //********************
//** Debug messages **
//********************
#if defined(STM32_BOARD) && defined (DEBUG_SERIAL) #if defined(STM32_BOARD) && defined (DEBUG_SERIAL)
uint16_t debug_time=0;
#define debug(msg, ...) {char buf[64]; sprintf(buf, msg, ##__VA_ARGS__); Serial.write(buf);} #define debug(msg, ...) {char buf[64]; sprintf(buf, msg, ##__VA_ARGS__); Serial.write(buf);}
#define debugln(msg, ...) {char buf[64]; sprintf(buf, msg "\r\n", ##__VA_ARGS__); Serial.write(buf);} #define debugln(msg, ...) {char buf[64]; sprintf(buf, msg "\r\n", ##__VA_ARGS__); Serial.write(buf);}
#define debug_time(msg) { uint16_t debug_time_TCNT1=TCNT1; debug_time=debug_time_TCNT1-debug_time; debugln(msg "%u", debug_time); debug_time=debug_time_TCNT1; }
#else #else
#define debug(...) { } #define debug(...) { }
#define debugln(...) { } #define debugln(...) { }

13
Multiprotocol/Multiprotocol.ino
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@ -1102,7 +1102,7 @@ void update_serial_data()
protocol=(rx_ok_buff[0]==0x55?0:32) + (rx_ok_buff[1]&0x1F); //protocol no (0-63) bits 4-6 of buff[1] and bit 0 of buf[0] protocol=(rx_ok_buff[0]==0x55?0:32) + (rx_ok_buff[1]&0x1F); //protocol no (0-63) bits 4-6 of buff[1] and bit 0 of buf[0]
sub_protocol=(rx_ok_buff[2]>>4)& 0x07; //subprotocol no (0-7) bits 4-6 sub_protocol=(rx_ok_buff[2]>>4)& 0x07; //subprotocol no (0-7) bits 4-6
RX_num=rx_ok_buff[2]& 0x0F; // rx_num bits 0---3 RX_num=rx_ok_buff[2]& 0x0F; // rx_num bits 0---3
debugln("New protocol selected: %d, sub proto %d, rxnum %d", protocol, sub_protocol, RX_num); debugln("New protocol selected: %d, sub proto %d, rxnum %d, option %d", protocol, sub_protocol, RX_num, option);
} }
else else
if( ((rx_ok_buff[1]&0x80)!=0) && ((cur_protocol[1]&0x80)==0) ) // Bind flag has been set if( ((rx_ok_buff[1]&0x80)!=0) && ((cur_protocol[1]&0x80)==0) ) // Bind flag has been set
@ -1503,7 +1503,7 @@ static uint32_t random_id(uint16_t address, uint8_t create_new)
uint16_t OCR1B; uint16_t OCR1B;
OCR1B =TCNT1+(6500L); OCR1B =TCNT1+(6500L);
timer.setCompare(TIMER_CH2,OCR1B); timer.setCompare(TIMER_CH2,OCR1B);
timer.attachCompare2Interrupt(ISR_COMPB); timer.attachInterrupt(TIMER_CH2,ISR_COMPB);
#else #else
OCR1B = TCNT1+(6500L) ; // Full message should be received within timer of 3250us OCR1B = TCNT1+(6500L) ; // Full message should be received within timer of 3250us
TIFR1 = OCF1B_bm ; // clear OCR1B match flag TIFR1 = OCF1B_bm ; // clear OCR1B match flag
@ -1532,12 +1532,12 @@ static uint32_t random_id(uint16_t address, uint8_t create_new)
{ {
idx=UDR0; // Dummy read idx=UDR0; // Dummy read
discard_frame=1; // Error encountered discard full frame... discard_frame=1; // Error encountered discard full frame...
debugln("Bad frame"); debugln("Bad frame RX");
} }
if(discard_frame==1) if(discard_frame==1)
{ {
#ifdef STM32_BOARD #ifdef STM32_BOARD
detachInterrupt(2); // Disable interrupt on ch2 timer.detachInterrupt(TIMER_CH2); // Disable interrupt on ch2
#else #else
CLR_TIMSK1_OCIE1B; // Disable interrupt on compare B match CLR_TIMSK1_OCIE1B; // Disable interrupt on compare B match
#endif #endif
@ -1561,7 +1561,8 @@ static uint32_t random_id(uint16_t address, uint8_t create_new)
{ // Timer1 compare B interrupt { // Timer1 compare B interrupt
discard_frame=1; discard_frame=1;
#ifdef STM32_BOARD #ifdef STM32_BOARD
detachInterrupt(2); // Disable interrupt on ch2 timer.detachInterrupt(TIMER_CH2); // Disable interrupt on ch2
debugln("Bad frame timer");
#else #else
CLR_TIMSK1_OCIE1B; // Disable interrupt on compare B match CLR_TIMSK1_OCIE1B; // Disable interrupt on compare B match
#endif #endif
@ -1610,3 +1611,5 @@ static uint32_t random_id(uint16_t address, uint8_t create_new)
} }
} }
#endif #endif

2
Multiprotocol/Pins.h
View File

@ -322,9 +322,9 @@
#ifdef STM32_BOARD #ifdef STM32_BOARD
#define OCR1A TIMER2_BASE->CCR1 #define OCR1A TIMER2_BASE->CCR1
#define TCNT1 TIMER2_BASE->CNT #define TCNT1 TIMER2_BASE->CNT
#define UDR0 USART2_BASE->DR
#define TIFR1 TIMER2_BASE->SR #define TIFR1 TIMER2_BASE->SR
#define OCF1A_bm TIMER_SR_CC1IF #define OCF1A_bm TIMER_SR_CC1IF
#define UDR0 USART2_BASE->DR
#define UCSR0B USART2_BASE->CR1 #define UCSR0B USART2_BASE->CR1
#define RXCIE0 USART_CR1_RXNEIE_BIT #define RXCIE0 USART_CR1_RXNEIE_BIT
#define TXCIE0 USART_CR1_TXEIE_BIT #define TXCIE0 USART_CR1_TXEIE_BIT