diff --git a/Multiprotocol/Multiprotocol.h b/Multiprotocol/Multiprotocol.h
index 955196e..52a7fd0 100644
--- a/Multiprotocol/Multiprotocol.h
+++ b/Multiprotocol/Multiprotocol.h
@@ -19,7 +19,7 @@
 #define VERSION_MAJOR		1
 #define VERSION_MINOR		1
 #define VERSION_REVISION	6
-#define VERSION_PATCH_LEVEL	45
+#define VERSION_PATCH_LEVEL	46
 //******************
 // Protocols
 //******************
diff --git a/Multiprotocol/Multiprotocol.ino b/Multiprotocol/Multiprotocol.ino
index f2a2a32..eadecb3 100644
--- a/Multiprotocol/Multiprotocol.ino
+++ b/Multiprotocol/Multiprotocol.ino
@@ -54,7 +54,6 @@
 	#include <SPI.h>	
 	#include <EEPROM.h>	
 	HardwareTimer HWTimer2(2);
-	HardwareTimer HWTimer3(3);
 	void PPM_decode();
 	void ISR_COMPB();
 	extern "C"
@@ -495,7 +494,7 @@ void loop()
 				#ifndef STM32_BOARD	
 					TIFR1=OCF1A_bm;					// clear compare A=callback flag
 				#else
-					TIMER2_BASE->SR &= ~TIMER_SR_CC1IF;	// clear compare flag on channel 1
+					TIMER2_BASE->SR = 0x1E5F & ~TIMER_SR_CC1IF;	// Clear Timer2/Comp1 interrupt flag
 				#endif
 				sei();								// enable global int
 				if(Update_All())					// Protocol changed?
@@ -516,7 +515,7 @@ void loop()
 			#ifndef STM32_BOARD			
 				TIFR1=OCF1A_bm;						// clear compare A=callback flag
 			#else
-				TIMER2_BASE->SR &= ~TIMER_SR_CC1IF;	// clear compare flag on channel 1
+				TIMER2_BASE->SR = 0x1E5F & ~TIMER_SR_CC1IF;	// Clear Timer2/Comp1 interrupt flag
 			#endif		
 			diff=OCR1A-TCNT1;						// compare timer and comparator
 			sei();									// enable global int
@@ -1047,7 +1046,7 @@ static void protocol_init()
 	#ifndef STM32_BOARD
 		TIFR1 = OCF1A_bm ;						// clear compare A flag
 	#else
-		TIMER2_BASE->SR &= ~TIMER_SR_CC1IF;		//clear compare Flag write zero 
+		TIMER2_BASE->SR = 0x1E5F & ~TIMER_SR_CC1IF;	// Clear Timer2/Comp1 interrupt flag
 	#endif	
 	sei();										// enable global int
 	BIND_BUTTON_FLAG_off;						// do not bind/reset id anymore even if protocol change
@@ -1268,25 +1267,20 @@ void modules_reset()
 	}
 	void init_HWTimer()
 	{	
-		// Pause the timer while we're configuring it
-		HWTimer2.pause();
-		TIMER2_BASE->PSC = 35;			//36-1;for 72 MHZ /0.5sec/(35+1)
-		TIMER2_BASE->ARR = 0xFFFF;		//count till max
-		HWTimer2.setMode(TIMER_CH1, TIMER_OUTPUT_COMPARE);
-		// Refresh the timer's count, prescale, and overflow
-		HWTimer2.refresh();
-		HWTimer2.resume();
+		HWTimer2.pause();									// Pause the timer2 while we're configuring it
+		
+		TIMER2_BASE->PSC = 35;								// 36-1;for 72 MHZ /0.5sec/(35+1)
+		TIMER2_BASE->ARR = 0xFFFF;							// Count until 0xFFFF
+		
+		HWTimer2.setMode(TIMER_CH1, TIMER_OUTPUT_COMPARE);	// Main scheduler
+		HWTimer2.setMode(TIMER_CH2, TIMER_OUTPUT_COMPARE);	// Serial check
 
-		HWTimer3.pause();
-		TIMER3_BASE->PSC = 35;			//36-1;for 72 MHZ /0.5sec/(35+1)
-		TIMER3_BASE->ARR = 0xFFFF;		//count till max
-		HWTimer3.setMode(TIMER_CH2, TIMER_OUTPUT_COMPARE);
-		TIMER3_BASE->SR &= ~TIMER_SR_CC2IF;					// Clear Timer3/Comp2 interrupt flag
-		HWTimer3.attachInterrupt(TIMER_CH2,ISR_COMPB);		// assign function to Timer2/Comp2 interrupt
-		TIMER3_BASE->DIER &= ~TIMER_DIER_CC2IE;				// disable Timer2/Comp2 interrupt
-		// Refresh the timer's count, prescale, and overflow
-		HWTimer3.refresh();
-		HWTimer3.resume();
+		TIMER2_BASE->SR = 0x1E5F & ~TIMER_SR_CC2IF;			// Clear Timer2/Comp2 interrupt flag
+		HWTimer2.attachInterrupt(TIMER_CH2,ISR_COMPB);		// Assign function to Timer2/Comp2 interrupt
+		TIMER2_BASE->DIER &= ~TIMER_DIER_CC2IE;				// Disable Timer2/Comp2 interrupt
+		
+		HWTimer2.refresh();									// Refresh the timer's count, prescale, and overflow
+		HWTimer2.resume();
 	}
 #endif
 
@@ -1508,9 +1502,9 @@ static uint32_t random_id(uint16_t address, uint8_t create_new)
 					TX_RX_PAUSE_on;
 					tx_pause();
 					#if defined STM32_BOARD
-						TIMER3_BASE->CCR2=TIMER2_BASE->CNT+(6500L);	// Full message should be received within timer of 3250us
-						TIMER3_BASE->SR &= ~TIMER_SR_CC2IF;			// Clear Timer3/Comp2 interrupt flag
-						TIMER3_BASE->DIER |= TIMER_DIER_CC2IE;		// Enable Timer3/Comp2 interrupt
+						TIMER2_BASE->CCR2=TIMER2_BASE->CNT+(6500L);	// Full message should be received within timer of 3250us
+						TIMER2_BASE->SR = 0x1E5F & ~TIMER_SR_CC2IF;	// Clear Timer2/Comp2 interrupt flag
+						TIMER2_BASE->DIER |= TIMER_DIER_CC2IE;		// Enable Timer2/Comp2 interrupt
 					#else
 						OCR1B = TCNT1+(6500L) ;	// Full message should be received within timer of 3250us
 						TIFR1 = OCF1B_bm ;		// clear OCR1B match flag
@@ -1544,7 +1538,7 @@ static uint32_t random_id(uint16_t address, uint8_t create_new)
 		if(discard_frame==1)
 		{
 			#ifdef STM32_BOARD
-				TIMER3_BASE->DIER &= ~TIMER_DIER_CC2IE;	// Disable Timer3/Comp2 interrupt
+				TIMER2_BASE->DIER &= ~TIMER_DIER_CC2IE;	// Disable Timer2/Comp2 interrupt
 			#else							
 				CLR_TIMSK1_OCIE1B;			// Disable interrupt on compare B match
 			#endif
@@ -1568,7 +1562,7 @@ static uint32_t random_id(uint16_t address, uint8_t create_new)
 	{	// Timer1 compare B interrupt
 		discard_frame=1;
 		#ifdef STM32_BOARD
-			TIMER3_BASE->DIER &= ~TIMER_DIER_CC2IE;	// Disable Timer3/Comp2 interrupt
+			TIMER2_BASE->DIER &= ~TIMER_DIER_CC2IE;	// Disable Timer2/Comp2 interrupt
 			debugln("Bad frame timer");
 		#else
 			CLR_TIMSK1_OCIE1B;						// Disable interrupt on compare B match