DSM2SFC timing update

This commit is contained in:
pascallanger 2024-03-19 20:52:50 +01:00
parent 91af921d98
commit 2e3520acad
3 changed files with 8 additions and 15 deletions

View File

@ -294,7 +294,7 @@ uint16_t DSM_callback()
uint8_t len; uint8_t len;
#endif #endif
uint8_t start; uint8_t start;
//debugln("P=%d",phase);
switch(phase) switch(phase)
{ {
case DSM_BIND_WRITE: case DSM_BIND_WRITE:
@ -400,6 +400,7 @@ uint16_t DSM_callback()
case DSM_CH2_WRITE_A: case DSM_CH2_WRITE_A:
case DSM_CH2_WRITE_B: case DSM_CH2_WRITE_B:
CYRF_ReadRegister(CYRF_04_TX_IRQ_STATUS); // clear IRQ flags CYRF_ReadRegister(CYRF_04_TX_IRQ_STATUS); // clear IRQ flags
//debugln_time("");
CYRF_WriteDataPacket(packet); CYRF_WriteDataPacket(packet);
#if 0 #if 0
for(uint8_t i=0;i<16;i++) for(uint8_t i=0;i<16;i++)
@ -438,13 +439,13 @@ uint16_t DSM_callback()
CYRF_SetTxRxMode(RX_EN); //Receive mode CYRF_SetTxRxMode(RX_EN); //Receive mode
CYRF_WriteRegister(CYRF_05_RX_CTRL, 0x87); //0x80??? //Prepare to receive CYRF_WriteRegister(CYRF_05_RX_CTRL, 0x87); //0x80??? //Prepare to receive
#ifndef MULTI_AIR #ifndef MULTI_AIR
if(sub_protocol==DSMR) if(sub_protocol==DSMR || sub_protocol == DSM2_SFC)
{ {
phase = DSM_CH2_READ_B; phase = DSM_CH2_READ_B;
if(sub_protocol == DSM2_SFC)
return DSM2_SFC_PERIOD - DSM_CH1_CH2_DELAY - DSM_WRITE_DELAY - DSM_READ_DELAY;
return 11000 - DSM_WRITE_DELAY - DSM_READ_DELAY; return 11000 - DSM_WRITE_DELAY - DSM_READ_DELAY;
} }
if(sub_protocol==DSM2_SFC)
return DSM2_SFC_PERIOD - DSM_CH1_CH2_DELAY - DSM_WRITE_DELAY - DSM_READ_DELAY;
#endif #endif
return 11000 - DSM_CH1_CH2_DELAY - DSM_WRITE_DELAY - DSM_READ_DELAY; return 11000 - DSM_CH1_CH2_DELAY - DSM_WRITE_DELAY - DSM_READ_DELAY;
case DSM_CH2_READ_A: case DSM_CH2_READ_A:
@ -473,16 +474,12 @@ uint16_t DSM_callback()
telemetry_link=1; telemetry_link=1;
} }
CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x20); // Abort RX operation CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x20); // Abort RX operation
if (phase == DSM_CH2_READ_A && (sub_protocol==DSM2_1F || sub_protocol==DSMX_1F || sub_protocol==DSM2_SFC) && num_ch < 8) // 22ms mode if (phase == DSM_CH2_READ_A && (sub_protocol==DSM2_1F || sub_protocol==DSMX_1F) && num_ch < 8) // 22ms mode
{ {
CYRF_SetTxRxMode(RX_EN); // Force end state read CYRF_SetTxRxMode(RX_EN); // Force end state read
CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x00); // Clear abort RX operation CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x00); // Clear abort RX operation
CYRF_WriteRegister(CYRF_05_RX_CTRL, 0x87); //0x80??? //Prepare to receive CYRF_WriteRegister(CYRF_05_RX_CTRL, 0x87); //0x80??? //Prepare to receive
phase = DSM_CH2_READ_B; phase = DSM_CH2_READ_B;
#ifndef MULTI_AIR
if(sub_protocol==DSM2_SFC)
return DSM2_SFC_PERIOD;
#endif
return 11000; return 11000;
} }
if (phase == DSM_CH2_READ_A) if (phase == DSM_CH2_READ_A)
@ -512,10 +509,6 @@ uint16_t DSM_callback()
} }
else else
phase = DSM_CH1_WRITE_A; // change from CH2_CHECK_B to CH1_WRITE_A (upper already transmitted so transmit lower) phase = DSM_CH1_WRITE_A; // change from CH2_CHECK_B to CH1_WRITE_A (upper already transmitted so transmit lower)
#ifndef MULTI_AIR
if(sub_protocol==DSM2_SFC)
return DSM2_SFC_PERIOD - DSM_CH1_CH2_DELAY - DSM_WRITE_DELAY ;
#endif
return 11000 - DSM_CH1_CH2_DELAY - DSM_WRITE_DELAY; return 11000 - DSM_CH1_CH2_DELAY - DSM_WRITE_DELAY;
#endif #endif
} }

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@ -19,7 +19,7 @@
#define VERSION_MAJOR 1 #define VERSION_MAJOR 1
#define VERSION_MINOR 3 #define VERSION_MINOR 3
#define VERSION_REVISION 4 #define VERSION_REVISION 4
#define VERSION_PATCH_LEVEL 1 #define VERSION_PATCH_LEVEL 2
#define MODE_SERIAL 0 #define MODE_SERIAL 0

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@ -547,7 +547,7 @@ CH1|CH2|CH3|CH4|CH5|CH6|CH7
STR|THR|AUX1|AUX2|AUX3|AUX4|AUX5 STR|THR|AUX1|AUX2|AUX3|AUX4|AUX5
### Sub_protocol DSM2SFC - *6* ### Sub_protocol DSM2SFC - *6*
Surface DSM2 receivers Surface DSM2 receivers, tested with a SR3100
Extended limits available and no channel mapping. Do not use DSM/AUTO to bind but DSM/2SFC instead. Extended limits available and no channel mapping. Do not use DSM/AUTO to bind but DSM/2SFC instead.