mirror of
https://github.com/pascallanger/DIY-Multiprotocol-TX-Module.git
synced 2025-02-04 18:28:15 +00:00
TRAXXAS TQ WIP
It still won't work unless you have some luck. I still need to work on the RF frequency.
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pascallanger
parent
3d989a47db
commit
2888d3e937
@ -298,7 +298,7 @@ void CYRF_FindBestChannels(uint8_t *channels, uint8_t len, uint8_t minspace, uin
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CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x00); // Clear abort RX
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}
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#if defined(DEVO_CYRF6936_INO) || defined(J6PRO_CYRF6936_INO)
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#if defined(DEVO_CYRF6936_INO) || defined(J6PRO_CYRF6936_INO) || defined(TRAXXAS_CYRF6936_INO)
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const uint8_t PROGMEM DEVO_j6pro_sopcodes[][8] = {
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/* Note these are in order transmitted (LSB 1st) */
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{0x3C, 0x37, 0xCC, 0x91, 0xE2, 0xF8, 0xCC, 0x91},
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@ -311,7 +311,7 @@ const uint8_t PROGMEM DEVO_j6pro_sopcodes[][8] = {
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{0xB9, 0x8E, 0x19, 0x74, 0x6F, 0x65, 0x18, 0x74},
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{0xDF, 0xB1, 0xC0, 0x49, 0x62, 0xDF, 0xC1, 0x49},
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{0x97, 0xE5, 0x14, 0x72, 0x7F, 0x1A, 0x14, 0x72},
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#if defined(J6PRO_CYRF6936_INO)
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#if defined(J6PRO_CYRF6936_INO) || defined(TRAXXAS_CYRF6936_INO)
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{0x82, 0xC7, 0x90, 0x36, 0x21, 0x03, 0xFF, 0x17},
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{0xE2, 0xF8, 0xCC, 0x91, 0x3C, 0x37, 0xCC, 0x91}, //Note: the '03' was '9E' in the Cypress recommended table
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{0xAD, 0x39, 0xA2, 0x0F, 0x9B, 0xC5, 0xA1, 0x0F}, //The following are the same as the 1st 8 above,
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@ -322,14 +322,22 @@ const uint8_t PROGMEM DEVO_j6pro_sopcodes[][8] = {
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{0x9E, 0x82, 0xDC, 0x3C, 0xA1, 0x78, 0xDC, 0x3C},
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{0x6F, 0x65, 0x18, 0x74, 0xB9, 0x8E, 0x19, 0x74},
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#endif
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#if defined(TRAXXAS_CYRF6936_INO)
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{0x62, 0xDF, 0xC1, 0x49, 0xDF, 0xB1, 0xC0, 0x49},
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#endif
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};
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#endif
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static void __attribute__((unused)) CYRF_PROGMEM_ConfigSOPCode(const uint8_t *data)
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{
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uint8_t code[8];
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//debug("SOP:");
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for(uint8_t i=0;i<8;i++)
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{
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code[i]=pgm_read_byte_near(&data[i]);
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//debug(" %02X",code[i]);
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}
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//debugln("");
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CYRF_ConfigSOPCode(code);
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}
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@ -20,10 +20,11 @@
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#include "iface_cyrf6936.h"
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//#define TRAXXAS_FORCE_ID
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//#define TRAXXAS_DEBUG
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#define TRAXXAS_DEBUG
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#define TRAXXAS_CHANNEL 0x05
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#define TRAXXAS_CHANNEL 0x0F
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#define TRAXXAS_BIND_CHANNEL 0x2B
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#define TRAXXAS_BIND_CHECK 0x22
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#define TRAXXAS_PACKET_SIZE 16
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enum {
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@ -34,10 +35,6 @@ enum {
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TRAXXAS_DATA,
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};
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const uint8_t PROGMEM TRAXXAS_sop_bind[] ={ 0x3C, 0x37, 0xCC, 0x91, 0xE2, 0xF8, 0xCC, 0x91 };
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const uint8_t PROGMEM TRAXXAS_sop_data[] ={ 0xA1, 0x78, 0xDC, 0x3C, 0x9E, 0x82, 0xDC, 0x3C };
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//const uint8_t PROGMEM TRAXXAS_sop_check[]={ 0x97, 0xE5, 0x14, 0x72, 0x7F, 0x1A, 0x14, 0x72 };
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const uint8_t PROGMEM TRAXXAS_init_vals[][2] = {
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//Init from dump
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{CYRF_0B_PWR_CTRL, 0x00}, // PMU
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@ -53,7 +50,7 @@ const uint8_t PROGMEM TRAXXAS_init_vals[][2] = {
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static void __attribute__((unused)) TRAXXAS_cyrf_bind_config()
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{
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CYRF_PROGMEM_ConfigSOPCode(TRAXXAS_sop_bind);
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CYRF_PROGMEM_ConfigSOPCode(DEVO_j6pro_sopcodes[0]);
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CYRF_WriteRegister(CYRF_15_CRC_SEED_LSB, 0x5A);
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CYRF_WriteRegister(CYRF_16_CRC_SEED_MSB, 0x5A);
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CYRF_ConfigRFChannel(TRAXXAS_BIND_CHANNEL);
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@ -61,14 +58,15 @@ static void __attribute__((unused)) TRAXXAS_cyrf_bind_config()
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static void __attribute__((unused)) TRAXXAS_cyrf_data_config()
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{
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CYRF_PROGMEM_ConfigSOPCode(TRAXXAS_sop_data);
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#ifdef TRAXXAS_FORCE_ID // data taken from TX dump
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CYRF_WriteRegister(CYRF_15_CRC_SEED_LSB, 0x1B);
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CYRF_WriteRegister(CYRF_16_CRC_SEED_MSB, 0x3F);
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CYRF_PROGMEM_ConfigSOPCode(DEVO_j6pro_sopcodes[6]);
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#else
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uint16_t addr=TRAXXAS_EEPROM_OFFSET+RX_num*2;
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uint16_t addr=TRAXXAS_EEPROM_OFFSET+RX_num*3;
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CYRF_WriteRegister(CYRF_15_CRC_SEED_LSB, cyrfmfg_id[0] - eeprom_read_byte((EE_ADDR)(addr + 0)));
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CYRF_WriteRegister(CYRF_16_CRC_SEED_MSB, cyrfmfg_id[1] - eeprom_read_byte((EE_ADDR)(addr + 1)));
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CYRF_PROGMEM_ConfigSOPCode(DEVO_j6pro_sopcodes[eeprom_read_byte((EE_ADDR)(addr + 2)) % 20]);
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#endif
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CYRF_ConfigRFChannel(TRAXXAS_CHANNEL);
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CYRF_SetTxRxMode(TX_EN);
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@ -108,6 +106,7 @@ uint16_t TRAXXAS_callback()
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switch(phase)
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{
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case TRAXXAS_BIND_PREP_RX:
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//debugln("BIND_PREP_RX");
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TRAXXAS_cyrf_bind_config();
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CYRF_SetTxRxMode(RX_EN); //Receive mode
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CYRF_WriteRegister(CYRF_05_RX_CTRL, 0x83); //Prepare to receive
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@ -115,6 +114,7 @@ uint16_t TRAXXAS_callback()
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phase=TRAXXAS_BIND_RX;
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return 700;
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case TRAXXAS_BIND_RX:
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//debugln("BIND_RX");
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//Read data from RX
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status = CYRF_ReadRegister(CYRF_07_RX_IRQ_STATUS);
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if((status & 0x03) == 0x02) // RXC=1, RXE=0 then 2nd check is required (debouncing)
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@ -139,15 +139,18 @@ uint16_t TRAXXAS_callback()
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debugln("");
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#endif
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// Store RX ID
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uint16_t addr=TRAXXAS_EEPROM_OFFSET+RX_num*2;
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uint16_t addr=TRAXXAS_EEPROM_OFFSET+RX_num*3;
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for(uint8_t i=0;i<2;i++)
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eeprom_write_byte((EE_ADDR)(addr+i),packet[i+1]);
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//Store SOP index
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eeprom_write_byte((EE_ADDR)(addr+2),packet[7]);
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// Replace RX ID by TX ID
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for(uint8_t i=0;i<6;i++)
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packet[i+1]=cyrfmfg_id[i];
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packet[7 ] = 0xEE; // Not needed ??
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//packet[7 ] = 0xEE; // Not needed ??
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packet[8] = TRAXXAS_CHANNEL - 1;
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packet[10] = 0x01; // Must change otherwise bind doesn't complete
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packet[13] = 0x05; // Not needed ??
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//packet[13] = 0x05; // Not needed ??
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packet_count=12;
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CYRF_SetTxRxMode(TX_EN);
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phase=TRAXXAS_BIND_TX1;
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@ -166,6 +169,7 @@ uint16_t TRAXXAS_callback()
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}
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return 700;
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case TRAXXAS_BIND_TX1:
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//debugln("BIND_TX1");
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CYRF_WriteDataPacketLen(packet, TRAXXAS_PACKET_SIZE);
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#ifdef TRAXXAS_DEBUG
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debug("P=");
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@ -177,10 +181,12 @@ uint16_t TRAXXAS_callback()
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phase=TRAXXAS_PREP_DATA;
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break;
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case TRAXXAS_PREP_DATA:
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//debugln("PREP_DATA");
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BIND_DONE;
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TRAXXAS_cyrf_data_config();
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phase++;
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case TRAXXAS_DATA:
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//debugln("DATA");
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#ifdef MULTI_SYNC
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telemetry_set_input_sync(13940);
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#endif
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@ -222,7 +228,7 @@ void TRAXXAS_init()
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// TRAXXAS_cyrf_bind_config();
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// CYRF_SetTxRxMode(TX_EN);
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// memcpy(packet,(uint8_t *)"\x02\x4A\xA3\x2D\x1A\x49\xFE\x06\x00\x00\x02\x01\x06\x06\x00\x00",TRAXXAS_PACKET_SIZE);
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// memcpy(packet,(uint8_t *)"\x02\xFF\xFF\xFF\xFF\xFF\xFF\x01\x01\x01\x02\x01\x06\x00\x00\x00",TRAXXAS_PACKET_SIZE);
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// memcpy(packet,(uint8_t *)"\x02\x49\xAC\x4F\x55\x4D\xFE\x05\x00\x00\x02\x01\x06\x06\x00\x00",TRAXXAS_PACKET_SIZE);
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}
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/*
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@ -274,4 +280,33 @@ RX ID: \x00\x00\x2D\x1A\x49\xFE CRC 0x65 0xE2 => CRC: 65-00=65 E2-00=E2
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RX ID: \x00\xFF\x2D\x1A\x49\xFE CRC 0x65 0xE3 => CRC: 65-00=65 E2-FF=E3
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RX ID: \xFF\x00\x2D\x1A\x49\xFE CRC 0x66 0xE2 => CRC: 65-FF=66 E2-00=E2
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*/
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/*
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RX1: 02 4A A3 2D 1A 49 FE 06 00 00 02 01 06 06 00 00
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SOP: A1 78 DC 3C 9E 82 DC 3C
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RX2: 02 49 AC 4F 55 4D FE 05 00 00 02 01 06 06 00 00
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SOP: 5A CC AE 46 B6 31 AE 46
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RX3: 02 CA F3 62 55 4D FE 03 00 00 02 01 06 06 00 00
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SOP: 66 CD 7C 50 DD 26 7C 50
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Dump of SOP Codes:
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00: 3C 37 CC 91 E2 F8 CC 91 => bind
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01: 9B C5 A1 0F AD 39 A2 0F
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02: EF 64 B0 2A D2 8F B1 2A
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03: 66 CD 7C 50 DD 26 7C 50
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04: 5C E1 F6 44 AD 16 F6 44
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05: 5A CC AE 46 B6 31 AE 46
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06: A1 78 DC 3C 9E 82 DC 3C
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07: B9 8E 19 74 6F 65 18 74
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08: DF B1 C0 49 62 DF C1 49
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09: 97 E5 14 72 7F 1A 14 72 => check
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10: 82 C7 90 36 21 03 FF 17
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11: E2 F8 CC 91 3C 37 CC 91 => bind 4 bytes group swapped
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12: AD 39 A2 0F 9B C5 A1 0F => 01 4 bytes group swapped
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13: D2 8F B1 2A EF 64 B0 2A => 02 4 bytes group swapped
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14: DD 26 7C 50 66 CD 7C 50 => 03 4 bytes group swapped
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...
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19: 62 DF C1 49 DF B1 C0 49 => 08 4 bytes group swapped
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20: 00 00 00 33 DE AD BA BE ??over??
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*/
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#endif
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