mirror of
https://github.com/pascallanger/DIY-Multiprotocol-TX-Module.git
synced 2025-12-14 19:53:14 +00:00
E016Hv2 and ESKY150V2 don't need the NRF code anymore
This commit is contained in:
Pascal Langer
@@ -163,4 +163,174 @@ void CC2500_SetPower()
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prev_power=power;
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}
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}
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void __attribute__((unused)) CC2500_SetFreqOffset()
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{
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if(prev_option != option)
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{
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prev_option = option;
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CC2500_WriteReg(CC2500_0C_FSCTRL0, option);
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}
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}
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void __attribute__((unused)) CC2500_250K_Init()
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{
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CC2500_Strobe(CC2500_SIDLE);
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// Address Config = No address check
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// Base Frequency = 2400
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// CRC Autoflush = false
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// CRC Enable = false
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// Channel Spacing = 333.251953
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// Data Format = Normal mode
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// Data Rate = 249.939
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// Deviation = 126.953125
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// Device Address = 0
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// Manchester Enable = false
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// Modulated = true
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// Modulation Format = GFSK
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// Packet Length Mode = Variable packet length mode. Packet length configured by the first byte after sync word
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// RX Filter BW = 203.125000
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// Sync Word Qualifier Mode = No preamble/sync
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// TX Power = 0
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// Whitening = false
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// Fast Frequency Hopping - no PLL auto calibration
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CC2500_WriteReg(CC2500_08_PKTCTRL0, 0x01); // Packet Automation Control
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CC2500_WriteReg(CC2500_0B_FSCTRL1, 0x0A); // Frequency Synthesizer Control
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CC2500_WriteReg(CC2500_0C_FSCTRL0, option); // Frequency offset hack
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CC2500_WriteReg(CC2500_0D_FREQ2, 0x5C); // Frequency Control Word, High Byte
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CC2500_WriteReg(CC2500_0E_FREQ1, 0x4E); // Frequency Control Word, Middle Byte
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CC2500_WriteReg(CC2500_0F_FREQ0, 0xC3); // Frequency Control Word, Low Byte
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CC2500_WriteReg(CC2500_10_MDMCFG4, 0x8D); // Modem Configuration
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CC2500_WriteReg(CC2500_11_MDMCFG3, 0x3B); // Modem Configuration
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CC2500_WriteReg(CC2500_12_MDMCFG2, 0x10); // Modem Configuration
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CC2500_WriteReg(CC2500_13_MDMCFG1, 0x23); // Modem Configuration
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CC2500_WriteReg(CC2500_14_MDMCFG0, 0xA4); // Modem Configuration
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CC2500_WriteReg(CC2500_15_DEVIATN, 0x62); // Modem Deviation Setting
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CC2500_WriteReg(CC2500_18_MCSM0, 0x08); // Main Radio Control State Machine Configuration
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CC2500_WriteReg(CC2500_19_FOCCFG, 0x1D); // Frequency Offset Compensation Configuration
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CC2500_WriteReg(CC2500_1A_BSCFG, 0x1C); // Bit Synchronization Configuration
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CC2500_WriteReg(CC2500_1B_AGCCTRL2, 0xC7); // AGC Control
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CC2500_WriteReg(CC2500_1C_AGCCTRL1, 0x00); // AGC Control
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CC2500_WriteReg(CC2500_1D_AGCCTRL0, 0xB0); // AGC Control
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CC2500_WriteReg(CC2500_21_FREND1, 0xB6); // Front End RX Configuration
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CC2500_WriteReg(CC2500_23_FSCAL3, 0xEA); // Frequency Synthesizer Calibration
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CC2500_WriteReg(CC2500_25_FSCAL1, 0x00); // Frequency Synthesizer Calibration
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CC2500_WriteReg(CC2500_26_FSCAL0, 0x11); // Frequency Synthesizer Calibration
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CC2500_SetTxRxMode(TX_EN);
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CC2500_SetPower();
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}
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void __attribute__((unused)) CC2500_250K_HoppingCalib(uint8_t num_freq)
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{
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for (uint8_t i = 0; i < num_freq; i++)
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{
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CC2500_Strobe(CC2500_SIDLE);
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// spacing is 333.25 kHz, must multiply channel by 3
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CC2500_WriteReg(CC2500_0A_CHANNR, hopping_frequency[i]*3);
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// calibrate
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CC2500_Strobe(CC2500_SCAL);
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delayMicroseconds(900);
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calData[i]=CC2500_ReadReg(CC2500_25_FSCAL1);
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}
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}
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void __attribute__((unused)) CC2500_250K_Hopping(uint8_t index)
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{
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// spacing is 333.25 kHz, must multiply channel by 3
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CC2500_WriteReg(CC2500_0A_CHANNR, hopping_frequency[index] * 3);
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// set PLL calibration
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CC2500_WriteReg(CC2500_25_FSCAL1, calData[index]);
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}
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void __attribute__((unused)) CC2500_250K_RFChannel(uint8_t number)
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{
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CC2500_Strobe(CC2500_SIDLE);
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// spacing is 333.25 kHz, must multiply channel by 3
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CC2500_WriteReg(CC2500_0A_CHANNR, number*3);
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// calibrate
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CC2500_Strobe(CC2500_SCAL);
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delayMicroseconds(900);
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}
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//NRF emulation layer with CRC16 enabled
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uint8_t cc2500_nrf_tx_addr[5], cc2500_nrf_addr_len;
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void __attribute__((unused)) CC2500_250K_NRF_SetTXAddr(uint8_t* addr, uint8_t len)
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{
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cc2500_nrf_addr_len = len;
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memcpy(cc2500_nrf_tx_addr, addr, len);
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}
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void __attribute__((unused)) CC2500_250K_NRF_WritePayload(uint8_t* msg, uint8_t len)
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{
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#if defined(ESKY150V2_CC2500_INO)
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uint8_t buf[158];
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#else
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uint8_t buf[35];
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#endif
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uint8_t last = 0;
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uint8_t i;
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//nrf preamble
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if(cc2500_nrf_tx_addr[cc2500_nrf_addr_len - 1] & 0x80)
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buf[0]=0xAA;
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else
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buf[0]=0x55;
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last++;
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// address
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for (i = 0; i < cc2500_nrf_addr_len; ++i)
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buf[last++] = cc2500_nrf_tx_addr[cc2500_nrf_addr_len - i - 1];
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// payload
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for (i = 0; i < len; ++i)
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buf[last++] = msg[i];
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// crc
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crc = 0xffff;
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for (uint8_t i = 1; i < last; ++i)
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crc16_update( buf[i], 8);
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buf[last++] = crc >> 8;
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buf[last++] = crc & 0xff;
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buf[last++] = 0;
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//for(uint8_t i=0;i<last;i++)
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// debug("%02X ",buf[i]);
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//debugln("");
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// stop TX/RX
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CC2500_Strobe(CC2500_SIDLE);
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// flush tx FIFO
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CC2500_Strobe(CC2500_SFTX);
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// packet length
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CC2500_WriteReg(CC2500_3F_TXFIFO, last);
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// transmit nrf packet
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uint8_t *buff=buf;
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uint8_t status;
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if(last>63)
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{
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CC2500_WriteRegisterMulti(CC2500_3F_TXFIFO, buff, 63);
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CC2500_Strobe(CC2500_STX);
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last-=63;
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buff+=63;
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while(last)
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{//Loop until all the data is sent
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do
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{// Wait for the FIFO to become available
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status=CC2500_ReadReg(CC2500_3A_TXBYTES | CC2500_READ_BURST);
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}
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while((status&0x7F)>31 && (status&0x80)==0);
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if(last>31)
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{//Send 31 bytes
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CC2500_WriteRegisterMulti(CC2500_3F_TXFIFO, buff, 31);
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last-=31;
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buff+=31;
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}
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else
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{//Send last bytes
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CC2500_WriteRegisterMulti(CC2500_3F_TXFIFO, buff, last);
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last=0;
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}
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}
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}
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else
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{//Send packet
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CC2500_WriteRegisterMulti(CC2500_3F_TXFIFO, buff, last);
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CC2500_Strobe(CC2500_STX);
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}
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}
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#endif
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