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FrskyX_RX documentation
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@ -183,7 +183,7 @@ uint16_t initFrSkyX_Rx()
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phase = FRSKYX_RX_BIND;
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phase = FRSKYX_RX_BIND;
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}
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}
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else {
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else {
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uint16_t temp = FRSKYX_RX_EEPROM_OFFSET + ((RX_num & 0x03) * 50);
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uint16_t temp = FRSKYX_RX_EEPROM_OFFSET;
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rx_tx_addr[0] = eeprom_read_byte(temp++);
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rx_tx_addr[0] = eeprom_read_byte(temp++);
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rx_tx_addr[1] = eeprom_read_byte(temp++);
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rx_tx_addr[1] = eeprom_read_byte(temp++);
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rx_tx_addr[2] = eeprom_read_byte(temp++);
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rx_tx_addr[2] = eeprom_read_byte(temp++);
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@ -239,7 +239,7 @@ uint16_t FrSkyX_Rx_callback()
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phase = FRSKYX_RX_DATA;
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phase = FRSKYX_RX_DATA;
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frskyx_rx_set_channel(hopping_frequency_no);
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frskyx_rx_set_channel(hopping_frequency_no);
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// store txid and channel list
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// store txid and channel list
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uint16_t temp = FRSKYX_RX_EEPROM_OFFSET+((RX_num & 0x03) * 50);
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uint16_t temp = FRSKYX_RX_EEPROM_OFFSET;
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eeprom_write_byte((EE_ADDR)temp++, rx_tx_addr[0]);
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eeprom_write_byte((EE_ADDR)temp++, rx_tx_addr[0]);
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eeprom_write_byte((EE_ADDR)temp++, rx_tx_addr[1]);
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eeprom_write_byte((EE_ADDR)temp++, rx_tx_addr[1]);
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eeprom_write_byte((EE_ADDR)temp++, rx_tx_addr[2]);
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eeprom_write_byte((EE_ADDR)temp++, rx_tx_addr[2]);
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@ -550,8 +550,8 @@ const PPM_Parameters PPM_prot[14*NBR_BANKS]= {
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EU_16
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EU_16
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EU_8
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EU_8
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PROTO_FRSKYX_RX
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PROTO_FRSKYX_RX
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FCC
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FRSKYX_FCC
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LBT
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FRSKYX_LBT
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PROTO_FY326
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PROTO_FY326
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FY326
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FY326
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FY319
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FY319
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@ -89,6 +89,7 @@ CFlie|38|CFlie||||||||NRF24L01|
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[FrskyD](Protocols_Details.md#FRSKYD---3)|3|FrskyD||||||||CC2500|
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[FrskyD](Protocols_Details.md#FRSKYD---3)|3|FrskyD||||||||CC2500|
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[FrskyV](Protocols_Details.md#FRSKYV---25)|25|FrskyV||||||||CC2500|
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[FrskyV](Protocols_Details.md#FRSKYV---25)|25|FrskyV||||||||CC2500|
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[FrskyX](Protocols_Details.md#FRSKYX---15)|15|CH_16|CH_8|EU_16|EU_8|||||CC2500|
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[FrskyX](Protocols_Details.md#FRSKYX---15)|15|CH_16|CH_8|EU_16|EU_8|||||CC2500|
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[FrskyX_RX](Protocols_Details.md#FRSKYX_RX---55)|55|FCC|EU_LBT|||||CC2500|
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[FY326](Protocols_Details.md#FY326---20)|20|FY326|FY319|||||||NRF24L01|
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[FY326](Protocols_Details.md#FY326---20)|20|FY326|FY319|||||||NRF24L01|
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[GD00X](Protocols_Details.md#GD00X---47)|47|GD_V1*|GD_V2*|||||||NRF24L01|
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[GD00X](Protocols_Details.md#GD00X---47)|47|GD_V1*|GD_V2*|||||||NRF24L01|
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[GW008](Protocols_Details.md#GW008---32)|32|GW008||||||||NRF24L01|XN297
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[GW008](Protocols_Details.md#GW008---32)|32|GW008||||||||NRF24L01|XN297
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@ -341,6 +342,32 @@ CH1|CH2|CH3|CH4|CH5|CH6|CH7|CH8
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---|---|---|---|---|---|---|---
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---|---|---|---|---|---|---|---
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CH1|CH2|CH3|CH4|CH5|CH6|CH7|CH8
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CH1|CH2|CH3|CH4|CH5|CH6|CH7|CH8
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## FRSKYX_RX - *55*
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The FrSkyX receiver protocol enables master/slave trainning, separate access from 2 different radios to the same model,...
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Extended limits supported
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Option for this protocol corresponds to fine frequency tuning.
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If the value is equal to 0, the RX will auto tune otherwise it will use the indicated value.
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This value is different for each Module and **must** be accurate otherwise the link will not be stable.
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Check the [Frequency Tuning page](/docs/Frequency_Tuning.md) to determine it.
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Low power: enable/disable the LNA stage on the RF component to use depending on the distance with the TX.
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### Sub_protocol FCC - *0*
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FCC protocol 8 or 16 channels.
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CH1|CH2|CH3|CH4|CH5|CH6|CH7|CH8|CH9|CH10|CH11|CH12|CH13|CH14|CH15|CH16
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---|---|---|---|---|---|---|---|---|----|----|----|----|----|----|----
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CH1|CH2|CH3|CH4|CH5|CH6|CH7|CH8|CH9|CH10|CH11|CH12|CH13|CH14|CH15|CH16
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### Sub_protocol EU_LBT - *1*
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EU_LBT protocol 8 or 16 channels.
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CH1|CH2|CH3|CH4|CH5|CH6|CH7|CH8|CH9|CH10|CH11|CH12|CH13|CH14|CH15|CH16
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---|---|---|---|---|---|---|---|---|----|----|----|----|----|----|----
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CH1|CH2|CH3|CH4|CH5|CH6|CH7|CH8|CH9|CH10|CH11|CH12|CH13|CH14|CH15|CH16
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## HITEC - *39*
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## HITEC - *39*
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Models: OPTIMA, MINIMA and MICRO receivers.
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Models: OPTIMA, MINIMA and MICRO receivers.
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