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https://github.com/pascallanger/DIY-Multiprotocol-TX-Module.git
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New protocol: E010r5
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Pascal Langer
213
Multiprotocol/E010R5_cyrf6936.ino
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213
Multiprotocol/E010R5_cyrf6936.ino
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/*
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This project is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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Multiprotocol is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Multiprotocol. If not, see <http://www.gnu.org/licenses/>.
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*/
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#if defined(E010R5_CYRF6936_INO)
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#include "iface_cyrf6936.h"
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#define E010R5_FORCE_ID
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static uint8_t __attribute__((unused)) E010R5_BR(uint8_t byte)
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{
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uint8_t result = 0;
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for(uint8_t i=0;i<8;i++)
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{
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result = (result<<1) | (byte & 0x01);
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byte >>= 1;
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}
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return result;
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}
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static void __attribute__((unused)) E010R5_build_data_packet()
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{
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uint8_t buf[16];
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//Build the packet
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buf[ 0] = 0x0D; // Packet length
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buf[ 1] = convert_channel_8b(THROTTLE);
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buf[ 2] = convert_channel_s8b(RUDDER);
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buf[ 3] = convert_channel_s8b(ELEVATOR);
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buf[ 4] = convert_channel_s8b(AILERON);
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buf[ 5] = 0x20; // Trim Rudder
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buf[ 6] = 0x20; // Trim Elevator
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buf[ 7] = 0x20; // Trim Aileron
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buf[ 8] = 0x01 // Flags: high=0x01, low=0x00
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| GET_FLAG(CH6_SW, 0x10) // headless=0x10
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| GET_FLAG(CH7_SW, 0x20); // one key return=0x20
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buf[ 9] = IS_BIND_IN_PROGRESS ? 0x80 : 0x00 // Flags: bind=0x80
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| GET_FLAG(CH5_SW, 0x01); // flip=0x01
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buf[10] = rx_tx_addr[0];
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buf[11] = rx_tx_addr[1];
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buf[12] = rx_tx_addr[2];
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buf[13] = 0x9D; // Check
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for(uint8_t i=0;i<13;i++)
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buf[13] += buf[i];
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//Add CRC
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crc=0x00;
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for(uint8_t i=0;i<14;i++)
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crc=crc16_update(crc,E010R5_BR(buf[i]),8);
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buf[14] = E010R5_BR(crc>>8);
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buf[15] = E010R5_BR(crc);
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#if 0
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debug("B:");
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for(uint8_t i=0; i<16; i++)
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debug(" %02X",buf[i]);
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debugln("");
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#endif
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//Build the payload
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memcpy(packet,"\x0E\x54\x96\xEE\xC3\xC3",6); // 4 bytes of address followed by 5 FEC encoded
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memset(&packet[6],0x00,70-6);
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//FEC encode
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for(uint8_t i=0; i<16; i++)
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{
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for(uint8_t j=0;j<8;j++)
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{
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uint8_t offset=6 + (i<<2) + (j>>1);
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packet[offset] <<= 4;
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if( (buf[i]>>j) & 0x01 )
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packet[offset] |= 0x0C;
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else
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packet[offset] |= 0x03;
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}
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}
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#if 0
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debug("E:");
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for(uint8_t i=0; i<70; i++)
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debug(" %02X",packet[i]);
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debugln("");
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#endif
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//CYRF wants LSB first
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for(uint8_t i=0;i<71;i++)
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packet[i]=E010R5_BR(packet[i]);
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}
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const uint8_t PROGMEM E010R5_init_vals[][2] = {
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{CYRF_02_TX_CTRL, 0x00}, // transmit err & complete interrupts disabled
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{CYRF_05_RX_CTRL, 0x00}, // receive err & complete interrupts disabled
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{CYRF_28_CLK_EN, 0x02}, // Force Receive Clock Enable, MUST be set
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{CYRF_32_AUTO_CAL_TIME, 0x3c}, // must be set to 3C
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{CYRF_35_AUTOCAL_OFFSET, 0x14}, // must be set to 14
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{CYRF_06_RX_CFG, 0x48}, // LNA manual control, Rx Fast Turn Mode Enable
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{CYRF_1B_TX_OFFSET_LSB, 0x00}, // Tx frequency offset LSB
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{CYRF_1C_TX_OFFSET_MSB, 0x00}, // Tx frequency offset MSB
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{CYRF_0F_XACT_CFG, 0x24}, // Force End State, transaction end state = idle
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{CYRF_03_TX_CFG, 0x00 | 7}, // GFSK mode, PA = +4 dBm
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{CYRF_12_DATA64_THOLD, 0x0a}, // 64 Chip Data PN Code Correlator Threshold = 10
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{CYRF_0F_XACT_CFG, 0x04}, // Transaction End State = idle
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{CYRF_39_ANALOG_CTRL, 0x01}, // synth setting time for all channels is the same as for slow channels
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{CYRF_0F_XACT_CFG, 0x24}, //Force IDLE
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{CYRF_29_RX_ABORT, 0x00}, //Clear RX abort
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{CYRF_12_DATA64_THOLD, 0x0a}, //set pn correlation threshold
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{CYRF_10_FRAMING_CFG, 0x4a}, //set sop len and threshold
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{CYRF_29_RX_ABORT, 0x0f}, //Clear RX abort?
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{CYRF_03_TX_CFG, 0x00 | 4}, // GFSK mode, set power (0-7)
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{CYRF_10_FRAMING_CFG, 0x4a}, // 0b11000000 //set sop len and threshold
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{CYRF_1F_TX_OVERRIDE, 0x04}, //disable tx CRC
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{CYRF_1E_RX_OVERRIDE, 0x14}, //disable rx crc
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{CYRF_14_EOP_CTRL, 0x00}, //set EOP sync == 0
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{CYRF_01_TX_LENGTH, 70 }, // payload length
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};
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static void __attribute__((unused)) E010R5_cyrf_init()
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{
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for(uint8_t i = 0; i < sizeof(E010R5_init_vals) / 2; i++)
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CYRF_WriteRegister(pgm_read_byte_near(&E010R5_init_vals[i][0]), pgm_read_byte_near(&E010R5_init_vals[i][1]));
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CYRF_WritePreamble(0xAAAA02);
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CYRF_SetTxRxMode(TX_EN);
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}
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uint16_t ReadE010R5()
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{
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//Bind
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if(bind_counter)
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{
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bind_counter--;
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if(bind_counter==0)
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BIND_DONE;
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}
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//Send packet of 71 bytes...
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uint8_t *buffer=packet;
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CYRF_WriteRegister(CYRF_02_TX_CTRL, 0x40);
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CYRF_WriteRegisterMulti(CYRF_20_TX_BUFFER, buffer, 16);
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CYRF_WriteRegister(CYRF_02_TX_CTRL, 0x80);
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buffer+=16;
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for(uint8_t i=0;i<6;i++)
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{
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while((CYRF_ReadRegister(CYRF_04_TX_IRQ_STATUS)&0x10) == 0);
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CYRF_WriteRegisterMulti(CYRF_20_TX_BUFFER, buffer, 8);
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buffer+=8;
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}
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while((CYRF_ReadRegister(CYRF_04_TX_IRQ_STATUS)&0x10) == 0);
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CYRF_WriteRegisterMulti(CYRF_20_TX_BUFFER, buffer, 6);
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//Timing and hopping
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packet_count++;
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switch(packet_count)
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{
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case 1:
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case 2:
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case 4:
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case 5:
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return 1183;
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default:
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hopping_frequency_no++;
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hopping_frequency_no &= 3;
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if(IS_BIND_IN_PROGRESS)
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rf_ch_num = 48 + (hopping_frequency_no<<3);
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else
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rf_ch_num = hopping_frequency[hopping_frequency_no];
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CYRF_ConfigRFChannel(rf_ch_num);
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debugln("%d",hopping_frequency[hopping_frequency_no]);
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packet_count = 0;
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case 3:
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E010R5_build_data_packet();
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return 3400;
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}
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return 0;
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}
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uint16_t initE010R5()
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{
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BIND_IN_PROGRESS; // autobind protocol
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bind_counter = 2600;
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E010R5_cyrf_init();
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#ifdef E010R5_FORCE_ID
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hopping_frequency[0]=48;
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hopping_frequency[1]=69;
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hopping_frequency[2]=64;
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hopping_frequency[3]=53;
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rx_tx_addr[0]=0x00;
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rx_tx_addr[1]=0x45;
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rx_tx_addr[2]=0x46;
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#endif
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E010R5_build_data_packet();
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CYRF_ConfigRFChannel(hopping_frequency[0]);
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hopping_frequency_no=0;
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packet_count=0;
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return 3400;
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}
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#endif
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